Abstract: A matrix type liquid-crystal display unit includes: a plurality of pixel portions which are arranged in the form of a matrix; a plurality of signal lines through which a display signal is supplied to the pixel portions; a plurality of scanning lines through which a scanning signal is supplied to the pixel portions; a signal-line drive circuit for driving the signal lines; a scanning-line drive circuit for driving the scanning-lines; a plurality of first thin-film transistors that form the signal-line drive circuit; a plurality of second thin-film transistors that form the scanning-line drive circuit; and a threshold value control circuit being connected to the signal-line drive circuit and the scanning-line drive circuit, for commonly controlling threshold values of the first and second thin-film transistors.

Abstract: The present invention provides an optical device and a surface emitting type device which have high efficiency and a stable operation and are manufactured at high manufacturing yield. The optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) including a plurality of semiconductor layers made of a nitride semiconductor with substantially same gaps therbetween. Further, the optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) in which a plurality of semiconductor layers made of nitride semiconductor and a plurality of organic layers made of organic material are alternately laminated.

Abstract: Disclosed is a semiconductor light-emitting element, comprising a double hetero structure formed of III-V group compound semiconductor layers including an active layer acting as a light emitting layer and an n-type cladding layer and a p-type cladding layer having the active layer sandwiched therebetween, a p-type layer laminated on the double hetero structure and containing a concentration of zn as a dopant, and a Zn diffusion preventing layer interposed between the active layer of the double hetero structure and the p-type layer having a high Zn concentration.

Abstract: The present invention is directed to an Organic Light Emitting Device (OLED) that provides improved sputter protection of the organics in the OLED, and a method of making the OLED. The top emitting OLED of the present invention has a substrate, an anode layer overlying the substrate, and a stack of one or more layers of light emitting organic material overlying the anode layer. The top emitting OLED of the present invention also has a first cathode layer overlying the stack of light emitting organic material, a second cathode layer overlying the first cathode layer, and a third cathode layer overlying the second cathode layer. The second cathode layer comprises a metal, alloy, or intermetallic of: Zr, Au, or Ta.

Abstract: A photoelectric conversion device comprising a semiconductor and an organic electrically conducting agent, wherein the organic electrically conducting agent exhibits a melting temperature Tm which is lower than the operation temperature of the photoelectric conversion device.

Abstract: The present planar photonic bandgap structures achieve improved control over radiation losses by employing layered dielectric structures. These structures control radiation losses incurred in connection with planar photonic bandgap structures and waveguides, waveguide bends, waveguide crossings, filters, switches and fiber-coupling structures in which such planar photonic bandgap structures are used.

Abstract: An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node.

Abstract: A semiconductor integrated circuit device comprises a register circuit receives a data signal, a delay adjustment circuit receives an output of the register circuit and a driver circuit receives an output of the delay adjustment circuit. An output timing of the register circuit is controlled by a clock signal. A delay time of the delay adjustment circuit is adjusted by a delay adjustment signal based on the data signal.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.

Abstract: A switch includes a conductive region, a membrane, and a dielectric region. The dielectric region is formed from a dielectric material and is disposed between the membrane and the conductive region. When a sufficient voltage is applied between the conductive region and the membrane, a capacitive coupling between the membrane and the conductive region is effected. The dielectric material has a resistivity sufficiently low to inhibit charge accumulation in the dielectric region during operation of the switch.

Abstract: A ferroelectric memory device includes a first interlayer film. This first interlayer film has a first contact hole in which a plug is buried by W-CVD. Thereafter, a ferroelectric capacitor, a second interlayer film, etc. are formed on the first interlayer film so that a second contact hole can be formed on the second interlayer film. A second contact hole is formed through the second interlayer film. This second contact hole is filled with a metal interconnection for connection to the plug.

Abstract: A semiconductor device includes a nitride film between a gate electrode and an ohmic electrode contacting to a diffusion region adjacent to the gate electrode, at least on a side of the gate electrode facing the ohmic electrode.

Abstract: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A barrier metal film of a metal whose conductivity will not be lost when the metal is oxidized or of a conductive metal oxide and a conductive wiring film of copper or a copper alloy are sequentially formed on a semiconductor substrate with an insulating film interposed therebetween.

Abstract: A trench capacitor has a bottle-shaped trench in a semiconductor substrate. The bottle-shaped trench has a wider lower region and a narrower upper region. An outer electrode layer is formed in the semiconductor substrate around a lower section of the wider lower region of the trench. A dielectric intermediate layer is provided on the lower section of the trench wall in the wider lower region of the trench. A first, thick insulation layer, which adjoins the dielectric intermediate layer, is provided on an upper section of the trench wall in the wider lower region of the trench. A second, thin insulation layer, which adjoins the first thick insulation layer, is formed on the trench wall in the narrower upper region of the trench. An inner electrode layer substantially fills the trench. A method of producing a trench capacitor is also provided.

Abstract: A power semiconductor device includes a base layer of first conductivity. A base layer of second conductivity is selectively formed on one surface of the base layer of first conductivity. An emitter layer or source layer of first conductivity is selectively formed on the surface of the base layer of second conductivity. A collector layer or drain layer is selectively formed on the other surface of the base layer of first conductivity or selectively formed on the one surface thereof. A gate electrode is formed on first and second gate insulating films which are formed on part of the base layer of second conductivity which lies between the emitter layer or source layer of first conductivity and the base layer of first conductivity. The capacitance of a capacitor formed of the second gate insulating film is different from that of a capacitor formed of the first gate insulating film.

Abstract: A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Abstract: An improved dynamic random access memory (DRAM) device with a capacitor having reduced current leakage from the dielectric layer, and materials and methods for fabricating the improved DRAM device are disclosed. The capacitor is formed using an oxygen anneal after a top conducting layer of the capacitor is formed.

Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

Abstract: A magnetoresistive element with an improved magnetoresistive effect achieved by interposing a titanium nitride layer between a substrate and a spinel-type magnetic substance is provided. The magnetoresistive element comprises a substrate and a multilayer film formed on the substrate, and the multilayer film includes a first magnetic layer, a nonmagnetic layer formed on the first magnetic layer and a second magnetic layer formed on this nonmagnetic layer. An electric current is supplied in a direction perpendicular to a film surface of the multilayer film, and a change in electrical resistance is detected by the electric current based on a change in a relative angle between a magnetization direction of the first magnetic layer and a magnetization direction of the second magnetic layer. The first magnetic layer has a spinel crystal structure, and the multilayer film further includes a titanium nitride layer interposed between the substrate and the first magnetic layer.

Abstract: A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an N+ substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a P− drift lower layer. In each case the top of the epitixial layer is N+. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the N+ top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

Abstract: Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a first direction. A plurality of buried insulated source electrodes are formed in the in the plurality of deep stripe-shaped trenches. A plurality of insulated gate electrodes are also provided that extend in parallel across the plurality of semiconductor mesas and into shallow trenches defined within the plurality of buried insulated source electrodes. A surface source electrode is provided on the substrate. The surface source electrode is electrically connected to each of the buried source electrodes at multiple locations along the length of each buried source electrode and these multiple connections decrease the effective source electrode resistance and enhance device switching speed.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

Abstract: A semiconductor device comprises an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulating layer on a first conductivity type semiconductor substrate; a MIS type field-effect transistor provided within a device region defined by isolating said mono-crystalline semiconductor layer with a device isolation region and having a gate electrode; an opening formed penetrating said device isolation region and said embedded insulating layer and reaching said semiconductor substrate; and a substrate electrode provided covering said opening and taken out up to the surface flush with said gate electrode.

Abstract: A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Abstract: A semiconductor device comprising an electrostatic protective element of the semiconductor device including a first conductivity type substrate and a second conductivity type high concentration diffusion layer formed on a surface of the substrate, and a semiconductor element including a source/drain and a gate electrode, wherein a first conductivity type diffusion layer having a higher concentration than the first conductivity type substrate is provided in an entire region under the second conductivity type high concentration diffusion layer.

Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor (20) is arranged along at least one side of a silicon bipolar transistor (1) on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor (1). The added integrated resistor (20) is a diffused p+ resistor on said semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added resistor or resistors (20) will be manufactured in a step simultaneously as producing the ballast resistors.

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat; digital CMOS devices are formed behind the other moat.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.

Abstract: An offset drain Fermi-threshold field effect transistor (Fermi-FET) includes spaced apart source and drain regions in an integrated circuit substrate, and a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is on the integrated circuit substrate between the spaced apart source and drain regions, and a gate electrode is on the gate insulating layer. The gate electrode is closer to the source region than to the drain region. Stated differently, the drain region is spaced farther away from the gate electrode than the source region. The offset drain Fermi-FET can introduce a drift region between the drain region and the Fermi-FET channel that can provide the high voltage and/or high frequency Fermi-FETs, while retaining the Fermi-FET advantages in the channel.

Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

Abstract: A semiconductor device includes a conductive semiconductor substrate laminated or bonded on a conductive support substrate through a first insulating film, a separation trench which separates a device formation region where at least a desired element is formed, from a region of the semiconductor substrate, a separation trench, and a substrate contact region where the semiconductor substrate is not present. The semiconductor device further includes a second insulating film which fills the separation trench and covers a surface of the substrate contact region, an external connection electrode formed above the semiconductor substrate, and a support substrate connecting section which passes through the first insulating film and the second insulating film in the substrate contact region to connect the external connection electrode and the support substrate.

Abstract: A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.

Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: The passive component (1) has a first part (22) of a material with a first resistance value, which value can be lowered to a second value by laser trimming. The second value is at most one tenth of the first value and preferably less. Said material crystallizes in a laser trimming process, which locally heats the material to at least a transition temperature. Said material contains at least two different elements, which are preferably aluminum and germanium.

Abstract: A spiral inductor comprising: a substrate; a protruding portion which is formed on the top face of the substrate and the top of which serves as a dummy element for controlling a chemical mechanical polishing process; and a conductive layer which is formed on the substrate so as to have a spiral shape and which serves as an induction element, wherein the protruding portion is formed in a region other than a region directly below the conductive layer.

Abstract: An integrated circuit (IC) including an integral, high k dielectric de-coupling capacitor constructed using a single conductive layer within the IC structure. The IC comprises a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line, and a high k dielectric material disposed between the first line and the second line. The capacitor is formed between the first line and the second line separated by the high k dielectric material. The capacitor is connected by coupling the first line to a signal and coupling the second line to a capacitor signal.

Abstract: The present invention relates to a semiconductor device and a fabricating method therefor. According to the semiconductor device of the present invention, a phased layer of under bump metallurgy (UBM) is formed by repeatedly depositing chrome and copper layers with sputtering equipment in which chrome and copper targets are installed in singular or plural chambers. The chrome and copper layers of the phased layer are deposited in the structure of the same, thin multi-layers possible for mutual diffusion, wherein the chrome layers gradually get thinner and the copper layers gradually get thicker. As a consequence, reliability in the phased layer of the present invention is achieved with increase in the speed of depositing UBM to reduce the time and cost for all the fabricating processes of the semiconductor device.

Abstract: Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.

Abstract: An object is to suppress resonance phenomenon. A pair of reinforcing members (18) are fixed on a gate drive substrate (7) with spacers (37) interposed therebetween and upright portions (40) of the pair of reinforcing members (18) are fastened with screws on a side wall of a cathode flange. A spacer (118) is fixed on the gate drive substrate (7) and a projection (118a) of the spacer (118) is inserted in an engaging member (119) fixed on the bottom of the cathode fin electrode (5) and thus fixed on the bottom of the cathode fin electrode (5). The pair of upright portions (40) as the first and second supporting points and the projection (118a) as the third supporting point stably support the gate drive substrate (7) on the cathode fin electrode (5) without freedom of rotation at the three positions arranged to surround an opening (49).

Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.

Abstract: A printed board unit is provided, which unit includes a printed board including lands thereon, a semiconductor device unit, and an attachment mechanism for attaching the semiconductor device unit to the printed board. The semiconductor device unit includes: a heat transfer member; a semiconductor device including first and second surfaces parallel to each other, the first surface having lands thereon; and a socket including contacts protruding from first and second surfaces of the socket, the first and second surfaces being parallel to each other. In the semiconductor device unit, the semiconductor device and the socket are attached to the heat transfer member so that the second surface of the semiconductor device opposes the heat transfer member. The lands of the semiconductor device are electrically connected to the lands of the printed board unit via the contacts of the socket.

Abstract: Expansion and contraction of water-cooling packs are easily carried out. A three way valve is provided at the upstream side of each water-cooling pack and a check valve is provided at the downstream side of each water-cooling pack, while a second branched pipe is connected to a pump so as to suck a cooling medium of each water-cooling pack, thereby constituting a substrate cooling unit. When the upstream and downstream sides of each water-cooling pack are closed, the cooling medium is forcibly discharged from each water-cooling pack by the pump.

Abstract: A semiconductor fabrication device includes a processing chamber in which the interior is substantially sealed. An upper processing electrode and a lower processing electrode are provided inside the processing chamber, and a stage made from a material having high thermal conductivity and on which semiconductor substrate is mounted is provided above the lower processing electrode. In this semiconductor fabrication device, for example, processing gas is introduced into the processing chamber, a radio-frequency voltage is applied between the two electrodes to generate plasma, and a process of etching a deposited film on the semiconductor substrate is carried out. While the process is being carried out, the semiconductor substrate is cooled by causing a cooling medium to flow but without allowing the cooling medium to pass through the processing chamber and thus without causing extraneous particles to occur in the processing chamber.