Abstract: The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension.

Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.

Abstract: A group 3-5 compound semiconductor comprising an interface of two layers having lattice mismatch, an intermediate layer having a film thickness of 25 nm or more and a quantum well layer, in this order. The compound semiconductor has high crystallinity and high quality, and suitably used for a light emitting diode.

Abstract: This invention relates to organic based spintronic devices, and electronic devices comprising them, including spin valves, spin tunnel junctions, spin transistors and spin light-emitting devices. New polymer-, organic- and molecular-based electronic devices in which the electron spin degree of freedom controls the electric current to enhance device performance. Polymer-, organic-, and molecular-based spintronic devices have enhanced functionality, ease of manufacture, are less costly than inorganic ones. The long spin coherence times due to the weak spin-orbit interaction of carbon and other low atomic number atoms that comprise organic materials make them ideal for exploiting the concepts of spin quantum devices. The hopping mechanism of charge transport that dominates in semiconducting polymers (vs. band transport in crystalline inorganic semiconductors) enhances spin-magneto sensitivity and reduces the expected power loss.

Abstract: A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.

Abstract: A Schottky barrier diode and process of making is disclosed. The process forms a metal contact pattern in masked areas on a silicon carbide wafer. A preferred embodiment includes on insulating layer that is etched in the windows of the mask. An inert edge termination is implanted into the wafer beneath the oxide layer and adjacent the metal contacts to improve reliability. A further oxide layer may be added to improve surface resistance to physical damage.

Abstract: Thin film transistors TFT2a and TFT2b for driving elements are formed in parallel between a power source line and an organic EL element, and active layers of the transistors TFT2a and TFT2b are spaced apart in a scanning direction of a laser used for annealing for polycrystallization. As a result, the annealing conditions for the transistors TFT2a and TFT2b will not be exactly the same, thereby reducing the chance of a same problem being caused in both transistors TFT2a and TFT2b.

Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.

Abstract: A semiconductor thin film having extremely superior crystallinity and a semiconductor device using the semiconductor thin film having high performance are provided. The semiconductor thin film is manufactured in such a manner that after an amorphous semiconductor thin film is crystallized by using a catalytic element, a heat treatment is carried out in an atmosphere containing a halogen element to remove the catalytic element. The thus obtained crystalline semiconductor thin film has substantially {110} orientation. The concentration of C, N, and S remaining in the final semiconductor thin film is less than 5×1018 atoms/cm3, and the concentration of O is less than 1.5×1019 atoms/cm3.

Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter.

Abstract: A nitride semiconductor device is composed of Group III nitride semiconductors. The device includes an active layer, and a barrier layer made from a predetermined material and provided adjacent to the active layer. The barrier layer has a greater band-gap than that of the active layer. The device also includes a barrier portion formed of the predetermined material for surrounding a threading dislocation in the active layer. The barrier portion has a vertex. The device also includes a semiconductor layer having an impurity concentration ranging from 1E16/cc to 1E17/cc in which the vertex is placed.

Abstract: A boron phosphide-based semiconductor device including a substrate having thereon an oxygen-containing boron phosphide-based semiconductor layer having boron and phosphorus as constituent elements and oxygen, and a production process therefor.

Abstract: A first GaN layer (2) is formed on a substrate (1), mask layer (3) having opening parts (3a) are formed thereon, a second GaN layer (4) is selectively grown in the lateral direction from the opening parts on the mask layer, and further a nitride type compound semiconductor layered part (15) is so laminated as to form a light emitting layer. Recessed parts (3b) are formed in the upper face side of the mask layer. In other words, owing to the recessed parts in the upper face side of the mask layer, the second GaN type compound semiconductor layer (4) is grown as to form approximately parallel gap (3c) between the bottom face of the second GaN type compound semiconductor layer and the mask layer. Further, it is preferable for the mask to be formed in a manner that the opening parts for exposing the seeds are not arranged only continuous in one single direction in the entire surface of the wafer type substrate.

Abstract: The invention provides a semiconductor laser module and an optical transmission system, with which noise caused by light reflected back from a transmission path can be suppressed. The semiconductor laser module, includes a package having a window, a semiconductor laser chip outputting light, a lens that is optically designed such that it couples the light that is output by the semiconductor laser chip into an optical transmission path, an optical isolator that is disposed between the lens and the window, a temperature control mechanism for keeping temperature of these components constant, and a tubular ferrule that is holds and covers the optical transmission path. The semiconductor laser chip, the lens, the optical isolator, and the temperature control mechanism are arranged inside the package. A polarizer is arranged at an end face of the ferrule on the side of the package, such that the polarizer matches a polarization plane of the light that is emitted through the window of the package.

Abstract: In a light-emitting element in which an n-type layer of a Group III nitride compound semiconductor, a light-emitting layer of a Group III nitride compound semiconductor and a p-type layer of a Group III nitride compound semiconductor are laminated successively on a substrate, a semiconductor layer of ZnxCd1−xSySe1−y (0<x<1, 0<y<1) which receives a part of blue light from the light-emitting layer to thereby emit yellow light, is interposed between the n-type Group III nitride compound semiconductor layer and the light-emitting layer.

Abstract: A light-emitting diode comprising a light-emitting diode die, a lead frame, a reflector cup and a dome encapsulating at least the light-emitting diode die and the reflector cup, wherein the reflector cup is made of a plastic material.

Abstract: A photodetector includes a detector responsive to incident light to generate an output signal and one or more band gap filters upstream of the broadband detector for absorbing incident photons of predetermined wavelength. The bandgap filters have a bandgap gradient across their width. The photodetector can act as a selective detector without the need for a separate optical filter.

Abstract: A light-emitting device has a light-emitting layer of nitride semiconductor containing As, P or Sb and accordingly its emission efficiency or emission intensity is enhanced. The light-emitting device includes a substrate, and further includes n-type and p-type nitride semiconductor layers and a light-emitting layer between the n-type and p-type semiconductor layers that are formed on the substrate. Light-emitting layer includes one or a plurality of well layers formed of nitride semiconductor containing N and element X (element X is As, P or Sb). The nitride semiconductor of the well layer has at most 30% in atomic percent represented by expression {NX/(NN+NX)}×100 where NX represents the number of atoms of element X and NN represents the number of atoms of N. The thickness of the well layer ranges from 0.4 nm to 4.8 nm.

Abstract: The invention concerns a bidirectional electronic switch of the pulse-controlled bistable type comprising a monolithic semiconductor circuit including a vertical bidirectional switch structure (TR; ACS) provided with a gate terminal (G1), first (Th1) and second (Th2) thyristor structures whereof the anodes are formed on the front face side, the first thyristor anode region containing a supplementary P-type region (6), and a metallization (A1, A2) connected to the main surface of the front face of the vertical bidirectional component and to the second thyristor anode; a capacitor (C) connected to the first thyristor anode and to the second thyristor supplementary N-type region; and a switch (SW) for short-circuiting the capacitor.

Abstract: Disclosed is a Group III nitride compound semiconductor light-emitting element formed of Group III nitride compound semiconductor layers, including a multi-layer containing light-emitting layers; a p-type semiconductor layer; and an n-type semiconductor layer, wherein the multi-layer includes a multiple quantum barrier-well layer containing quantum-barrier-formation barrier layers formed from a Group III nitride compound semiconductor and quantum-barrier-formation well layers formed from a Group III nitride compound semiconductor, the barrier layers and the well layers being laminated alternately and cyclically, and a plurality of low-energy-band-gap layers which emit light of different wavelengths; and the multiple quantum barrier-well layer is provided between the low-energy-band-gap layers.

Abstract: The present invention enables to design a semiconductor integrated circuit with a small chip area and the number of wiring layers at a low cost for a short time. In the present design method of the semiconductor integrated circuit, a first wiring group (a horizontal power wiring and horizontal ground wirings) and a second wiring group (a horizontal power wiring and horizontal ground wirings), which are opposite to each other, are arranged at the outside of a macro outer frame, a third wiring group (a vertical power wiring and a vertical ground wring) is arranged to correspond to a power terminal and a ground terminal on a macro cell, and these first and second wiring groups are connected to the power terminal and the ground terminal by the third wiring group.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: The invention is directed to a programmable IC (integrated circuit) arrangement. Included are: at least one input/output terminal; at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal; and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals. The selectably providable electrically conductive components include ones of selectably providable vias, switch-contacts and well regions.

Abstract: A filter that can achieve miniaturization and low power consumption at the same time without reducing operation precision, and a modulation semiconductor integrated circuit suitable for a wireless communication system using the filter are realized. In a modulation semiconductor integrated circuit including a digital filter that sample a digital transmission data signal an odd number of times for each two symbol cycles to perform product-sum operations, and a DA conversion circuit that subjects the output of the digital filter to DA conversion, a compensating circuit is provided which inserts predetermined values different from two types of symbols to the input of the digital filter.

Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions.

Abstract: By depositing a diffusion prevention film 7 constructed of an oxide of aluminum containing barium and heat-treating the diffusion prevention film 7 in the atmosphere of a mixed gas of oxygen and carbon dioxide, carbon dioxide is made to adsorb to the barium contained in the diffusion prevention film 7. The diffusion prevention film can effectively restrain the permeation of hydrogen and has an excellent hydrogen barrier property. By using the diffusion prevention film for a capacitor, a high-yield semiconductor storage device having the capacitor of a stable ferroelectric characteristic or high dielectric characteristic can be obtained.

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: Lead interconnection layers and are electrically connected to the respective source and drain regions of a pair of a monitor transistor MT. Lead interconnection layers and are both formed on same insulating layer and on same insulating layer as is a bit line conductive layer of a memory cell area. Furthermore, lead interconnection layers and have respective contact sections each with a large width and to each of which a needle of a probe can be connected externally. With such a structure adopted, there can be obtained a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a fabrication process therefor.

Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation in the presence of contaminants. An enhanced capacitor in a dynamic random access memory cell is discussed. The enhanced capacitor includes a first electrode, a dielectric coupled to the first electrode, a second electrode coupled to the dielectric, and at least one inhibiting layer that couples to the first electrode, the dielectric, and the second electrode. The inhibiting layer defines a chamber that encloses the capacitor and renders the capacitor impervious to disturbance in its physical or chemical forces in the presence of contaminants. The inhibiting layer includes a nitride compound, an oxynitride compound, and an oxide compound. In one embodiment, the nitride compound includes SixNy. In another embodiment, the oxynitride compound includes SiOxNy. In another embodiment, the oxide compound includes Al2O3 and (SrRu)O3. The variables x and y are indicative of a desired number of atoms.

Abstract: A method or process of manufacturing on-chip capacitors on a VLSI device (or chip) is improved by utilizing a high-dielectric constant metal-insulator-metal (MIM) capacitor manufacturing process. The high-k constant MIM capacitor may include a lower electrode in a first metal layer of a VLSI device, a substantially thin layer of high-k insulator (e.g., silicon nitride at an interface of the first metal layer and a via, and an upper electrode form in a second metal layer. The via provides a channel between the second metal layer to the high-k insulator. The on-chip capacitors may be fabricated in a variety of configurations such as a parallel line, parallel plate or in a cross-over area of two different metal lines.

Abstract: A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: Wiring layers through that come into direct contact with an electrode of a ferroelectric capacitor provide a wiring layer structure configured so that the characteristic of the ferroelectric substance is not degraded by production of a reducing agent. One of coating layers through is provided on the periphery of the Al main wiring layer. A single Ti film or TiN film or a combination of both is used as the coating film. The TiN film suppresses reaction between water and aluminum. The Ti film occludes hydrogen. Therefore, the coating layer provided on the periphery of the Al wiring layer inhibits water or molecular hydrogen from entering the Al wiring layer from the outside and therefore there is no degradation of the characteristics of the ferroelectric capacitor.

Abstract: A method for forming capacitor using a tantalum oxide (TaO5) layer is disclosed. Tantalum oxide is deposited by an atomic layer deposition ALD process so that the step-coverage of the tantalum oxide layer is improved, and accordingly the electrical characteristics of the capacitor are improved.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.

Abstract: A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode.

Abstract: A floating gate for use in a memory cell is provided which comprises a first end region adjacent a first lateral end of the floating gate; a second end region adjacent a second lateral end of the floating gate opposite the first lateral end; and a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.