Abstract: A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained.

Abstract: A lateral MOSFET exhibiting a high breakdown voltage includes a plurality of unit devices formed in a semiconductor substrate; each unit device including a trench, the side face thereof being extended at any angle from 30 degrees to 90 degrees with respect to the surface of trench; an offset drain region surrounding the side face and the bottom face of trench; an insulator filling trench; a gate electrode extended onto trench such that gate electrode works as a field plate; a source electrode extended above trench such that source electrode works as a field plate; and a drain electrode extended above trench such that drain electrode works as a field plate.

Abstract: A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivity type provided on the base layer, a gate insulating film formed on an inner wall surface of a trench penetrating the base layer and reaching at the drift layer, and a gate electrode provided on the gate insulating film inside the trench, wherein the gate insulating film is formed such that a portion thereof adjacent to the drift layer is thicker than a portion thereof adjacent to the base layer, and the drift layer has an impurity concentration gradient higher in the vicinity of the drain layer and lower in the vicinity of the source region along a depth direction of trench.

Abstract: The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second side-wall insulator layers formed on side walls and on a portion of first surface, and a nitrogen-containing extending from the portion of silicon substrate that is in the vicinity of second surface to the portion of silicon substrate that is in the vicinity of the interface between first and second side-wall insulator layers and silicon substrate.

Abstract: The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stacked upper having a first gate electrode and a second gate electrode. The second gate electrode may have a broader width than the lower first gate electrode.

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: Many integrated circuits, particularly digital memories, include millions of field-effect transistors which operate simultaneously and thus consume considerable power. One way to reduce power consumption is to lower transistor threshold, or turn-on, voltage, and then use lower-voltage power supplies. Although conventional techniques of lowering threshold voltage have enabled use of 2-volt power supplies, even lower voltages are needed. Several proposals involving a dynamic threshold concept have been promising, but have failed, primarily because of circuit-space considerations, to yield practical devices. Accordingly, the present invention provides a space-saving structure for a field-effect transistor having a dynamic threshold voltage. One embodiment includes a vertical gate-to-body coupling capacitor that reduces the surface area required to realize the dynamic threshold concept. Other embodiments include an inverter, voltage sense amplifier, and a memory.

Abstract: A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.

Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: The invention relates to a high density read only memory and fabrication method thereof through fabricating a plurality of spaced post transistors on a wafer by implanting and trench etching wherein each post transistor has four vertical surfaces with one of vertical surfaces as a short circuit junction between substrate and source and a read only memory (ROM) cell formed on each of the three remaining vertical surfaces. Therefore, the invention can fabricate three ROM cells in a single post transistor having a high density feature for storing. three-bit data.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.

Abstract: A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench.

Abstract: A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: A gate insulating film is formed of an oxynitride film prepared by adding nitrogen atoms to a thermal oxide film. The Si—N bonds each having a second adjacent oxygen atom as viewed on the basis of the nitrogen atom within the oxynitride film are positioned at least one atomic layer inside the interface between the silicon substrate and the oxynitride film to allow the gate insulating film to prevent boron atoms contained in the gate electrode from being migrated through the gate insulating film without lowering the driving force of the transistor.

Abstract: A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: A micromechanical component having a substrate beneath at least one structured layer, in the structured layer at least one functional structure being formed, a cap which covers the functional structure, between the cap and the functional structure at least one cavity being formed, and a connecting layer which connects the cap to structured layer, as well as a method for producing the micromechanical component. To obtain a compact and robust component, the connecting layer is formed from an anodically bondable glass, i.e. a bond glass, which has a thickness in the range of 300 nm to 100 &mgr;m, which may in particular be in the range of 300 nm to 50 &mgr;m.

Abstract: The signal-to-noise ratio of amorphous silicon (a-Si:H) image sensor arrays is limited by electronic noise, which is largely due to data line capacitance. To reduce data line capacitance, an air-gap (i.e., vacuum or gas-filled space) is produced at crossover points separating the data lines and gate lines. This air-gap crossover structure is formed by depositing a release material on the gate lines, forming the data lines on the release material, and then removing (etching) the release material such that the data lines form an arch extending over the gate lines. A dielectric material is then applied to strengthen the data line, and the sensor pixels are then formed.

Abstract: A circuit layout for several sensor elements of touch switches is described. It is subdivided into a control part with a control signal and a sensor part with several sensor branches, which in each case contain a capacitive sensor element. An evaluating part inter alia has a capacitor, where an analog output signal can be tapped. By means of connecting means, e.g. in the form of transistors or diodes, with a corresponding control in each case precisely one sensor branch is connected to the remaining circuit and the corresponding sensor element is controlled and evaluated.

Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Abstract: The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.

Abstract: A semiconductor device has a bump electrode formed on a flat surface of a passivation film of the device. The bump electrode is connected to a top wiring layer through a plurality of openings in the passivation film underneath the bump electrode, which are filled with a conductive material. The bump electrode is formed away from via holes, which connects the top wiring layer for the bump electrode and a lower wiring layer connected to source and drain layers of the device.

Abstract: A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate top surface, and electrically insulated from said semiconductor substrate by a gate insulating film, a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface, a first boundary end portion, which is defined between a substrate side surface of said semiconductor substrate forming a part of the side surface of said trench and said substrate top surface, and a second boundary end portion, which is defined between a gate side surface of said gate electrode forming another part of the side surface of said trench and said opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom

Abstract: An integrated circuit on a silicon substrate includes at least one polysilicon line and at least one antistatic contact connecting the polysilicon line to the silicon substrate. The antistatic contact includes a thin oxide layer between the polysilicon line and the silicon substrate. The thin oxide layer is of a sufficiently small thickness so that a current flows across it by the tunnel effect when the polysilicon line is brought, relatively to the substrate, to a voltage greater or less than determined thresholds.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal, mass outer surfaces and diffuse at least some of the projecting metal, mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.

Abstract: A thin-film multi-layer high Q inductor spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical communications with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The plurality of first metal runners are in a different vertical than the plurality of second metal runners such that the planes intersect. Thus one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias.

Abstract: A composite integrated circuit is characterized in that to put an oxide thin film into practical use as an electronic device, a highly crystalline oxide thin film is grown on a silicon substrate. A MOS circuit and a thin film capacitor are formed independently, and the two substrates are laminated using an epoxy resin. They are connected through buried wiring, thereby constituting a composite circuit package. As a second substrate 1 a, a (110) plane orientation silicon substrate is used which differs from the IC substrate with a (100) plane. On the (110) silicon substrate after the termination processing, a dielectric layer is film deposited, followed by forming an upper electrode, and by forming a thin film coil. Insulating magnetic gel is filled between coil wires and its upper portion. Thus, the fabrication process of the thin film coil and the composite integrated circuit is completed.

Abstract: A semiconductor memory device of the present invention includes: a substrate; a plurality of memory cells arranged in a matrix pattern on a primary surface of the substrate; a sense amplifier provided in each column for detecting data of the memory cells that are arranged along the column; a plurality of wiring layers formed on the substrate; and a plurality of data lines provided in each column and connected to the memory cells that are arranged in the column, wherein the data lines are connected commonly to the sense amplifier but via different paths, and a data line having a longer path length is provided by using a wiring layer that is on a higher level.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.

Abstract: A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.

Abstract: A flexible circuit having a polyimide substrate containing at least one chemically etched feature, wherein such etched feature has sidewalls having a predetermined slope angle. It is possible to create etched features having predetermined slopes of from about 10 to about 70 degrees. Preferably, the flexible circuit was formed from a polyamic acid containing multiple ester groups in its main polymer chain.

Abstract: A GaN-based compound semiconductor epi-wafer includes: a substrate 11 made of a first nitride semiconductor belonging to a hexagonal system; and an element layer 12 for forming a semiconductor element, which is made of a second nitride semiconductor belonging to the hexagonal system and which is grown on a principal surface of the substrate 11. An orientation of the principal surface of the substrate 11 has an off-angle in a predetermined direction with respect to a (0001) plane, and the element layer 12 has a surface morphology of a stripe pattern extending substantially in parallel to the predetermined direction.

Abstract: Porous dielectric materials having low dielectric constants, ≧30% porosity and a closed cell pore structure are disclosed along with methods of preparing the materials. Such materials are particularly suitable for use in the manufacture of electronic devices.

Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a programmable material is formed on the adhesive and on the electrode. In an aspect, a method is provided such that an adhesive is formed on a dielectric, an opening is formed through the dielectric exposing a contact formed on a substrate, and a programmable material is formed on the adhesive and on a portion of the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A method for monitoring the uniformity or quality of ultra-thin silicon nitride film uses wet re-oxidation of thin nitride to monitor its thickness variation to evaluate its quality. For nitride films with similar thicknesses, thinner oxide implies superior quality of the original nitride film and vice versa. The method of the present invention extends the use of ellipsometer measurement tools to the sub 10 Å level.

Abstract: A lead frame has a die pad portion supported internally of a framework portion by suspension leads and a plurality of leads each having one end connected to the framework portion and the other end opposed to the die pad portion. The die pad portion has a holding region formed from a part of an upper surface of the die pad portion which has been elevated above the remaining part of the upper surface. Openings are formed in the holding region to extend therethrough in a front-to-back direction of the die pad portion.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A semiconductor device is shown and described which includes a metal can that receives a semiconductor die in an interior thereof. The metal can has a recess formed on a top portion thereof. The recess provides rigidity to the top portion of the metal can which allows the wall of the can to be spaced farther apart from the die, thereby providing a much larger open channel which allows for the easier cleaning of flux residue after soldering.

Abstract: A stress-relieving heatsink structure and method of forming thereof for an electronic package, for instance, that including a semiconductor chip package which is mounted on a wired carrier, such as a circuitized substrate. The heatsink structure is constituted from a plurality of base structures which are joined along slits so as to impart a degree of flexibility to the electronic package inhibiting the forming of stresses tending to cause delamination of the package components.

Abstract: A semiconductor device is disclosed which includes a tub (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tub suspension lead (4) for support of the tub (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer

Abstract: An optical device with a tape carrier package is provided for low cost packaging and better stability. The optical device comprises: an optical sensor chip having a plurality of electrodes on its sensible surface; a flexible circuit board having an upside surface, an underside surface and a window; a plurality of metal circuits formed on the flexible circuit board and each of them having an inner lead extending into the window for bonding with the corresponding electrode; a base having a recession which is corresponding to the window and located under the underside surface of the flexible circuit board, and having a surrounding dam which extends onto the upside surface of the flexible circuit boars; and a transparent cover fixed attached to the surrounding dam for sealing the optical sensor chip.