Abstract: RF MicroElectroMechanical Systems (MEMs) circuitry(15) on a first high resistivity substrate (17)is combined with circuitry (11) onsecond low-resisitivity substrate (13) by overlapping the first high resisitivity substrate (17)and MEMs circuitry (15) with the low resisitivity substrate(13) and circuitry (11) with the MEMs circuitry (15)facing the second circuitry (11). A dielectric lid (19) is placed over the MEMs circuitry (15)and between the first substrate (17)and second substrate (13)with an inert gas in a gap (21)over the MEMs circuitry (15). Interconnecting conductors (25,31,35,37,39,41) extend perpendicular and through the high resistivity substrate (17)and through the dielectric lid (19) to make electrical connection with the low resisitivity substrate (13).

Abstract: Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.

Abstract: A semiconductor device according to the invention is provided with an electrode used for connecting a semiconductor chip and a wiring board or plural semiconductor chips, an additive layer formed by doping an additive including at least one type of atom different from an atom forming the electrode in the vicinity of the surface of the electrode and an insulator formed on the surface of the electrode.

Abstract: A electronic assembly is disclosed and claimed. The electronic assembly includes a first substrate and a second substrate. A plurality of power connections are coupled between the first substrate and the second substrate and a multiplicity of signal connections separate from the plurality of power connections are also coupled between the first substrate and the second substrate. Each of the plurality of power connections have a substantially different size and shape compared to each of the multiplicity of signal connections.

Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.

Abstract: A wiring board for a semiconductor package comprises a base substrate having first and second surfaces; a wiring layer consisting of necessary wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information provided for the respective semiconductor element mounting areas, the individual patterns having a particular shape for the respective semiconductor element mounting area. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.

Abstract: In a semiconductor device, a plurality of linear semiconductors of a predetermined length, on which electronic element are formed, are aligned laterally and in parallel. A semiconductor assembly apparatus for assembling the semiconductor device, aligns the linear semiconductors in parallel via an arranging member. The linear semiconductors are interconnected by a connecting member in the semiconductor assembly apparatus.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies in its portion is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on respective of main plane of the semiconductor element and a main electrode plate.

Abstract: A hermetically sealing enclosure for housing photo-semiconductor devices that reduces the heat generated in the wiring strips at the ceramic terminal member, increases the allowable current of the wiring strips in comparison with the conventional enclosures while maintaining the low power consumption, and stabilizes the output of the device in the enclosure. A photo-semiconductor module incorporating the enclosure is also offered. The ceramic terminal member is provided with a first wiring layer that comprises a plurality of wiring strips and that penetrates through the ceramic terminal member; two second wiring layers each of which comprises at least one wiring strip, one of which is connected to the first wiring layer at the outside of the enclosure, and the other of which is connected to the first wiring layer at the inside; and at least one third wiring layer that comprises at least one wiring strip and that connects the two second wiring layers.

Abstract: A semiconductor device having a semiconductor element and a plurality of segments formed by dividing a conductive plate. Some of the segments are electrically coupled with electrodes of said semiconductor element and constitute lead pad portions as mounting electrodes of the semiconductor device. Other segments among the plurality of divided segments constitute die pad portions on which the semiconductor element is mounted. The plurality of divided segments and the semiconductor element are sealed and supported together by a resin material portion. The resin material portion fills the space between the divided segments as the lead pad portions. Semiconductor devices having various package sizes can be fabricated by using standardized common parts.

Abstract: A resistor element has a ceramic body with a first outer electrode and a second outer electrode formed on its mutually opposite externally facing end surfaces and a plurality of mutually oppositely facing pairs of inner electrodes inside the ceramic body. Each of these pairs has a first inner electrode extending horizontally from the first outer electrode and a second inner electrode extending horizontally from the second outer electrode towards the first outer electrode and having a front end opposite and separated from the first inner electrode by a gap of a specified width, these plurality of pairs forming layers in a vertical direction. The gap of at least one of these plurality of pairs of inner electrodes is horizontally displaced from but overlapping with the gaps between the other pairs of inner electrodes. For producing such a resistor element, the distance of displacement is set according to a given target resistance value intended to be had by the resistor element.

Abstract: A semiconductor device including: a circuit board having a plurality of first electrodes thereon: a semiconductor chip having a plurality of second electrodes thereon: a bonding sheet sandwiched between said circuit boar and said semiconductor chip and having a plurality of apertures; and a solder bump disposed in each of apertures for connecting a corresponding one of the first electrodes and a corresponding one of the second electrodes. The semiconductor device can be manufactured without a conventional resin-applying step, thereby removing the cost for conducting the step. Also a short-circuit failure can be effectively prevented because the solder bumps are securely maintained in the apertures.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A method and apparatus for protecting a metal interconnect from corrosion due to contact with a low k dielectric material in a multilevel metallization and interconnect structure. To facilitate such protection, a barrier material, in the form of a sidewall spacer, is deposited between the dielectric material and the metal line.

Abstract: Titanium nitride layers a less than 30 nm thickness are formed by physical vapor deposition and used as barrier layers for tungsten deposition. The titanium nitride layers are annealed in the presence of nitrogen or a nitrogen compound.

Abstract: Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in interconnects and contacts. Early transition metals having relatively low surface energies are chosen to form stable crystalline compounds rich in the high surface-energy metal. Agglomeration control layers containing such alloy compounds facilitate adhesion between the high surface-energy metal and an underlying layer of the integrated circuit device, such as a diffusion barrier layer. These agglomeration control layers may be nitrided to improve robustness at higher temperatures.

Abstract: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

Abstract: A semiconductor device including a cylinder-type capacitor and a manufacturing method thereof are provided. The semiconductor device includes dielectric layer patterns formed on a semiconductor substrate. The dielectric layer patterns extend to the same height in a cell region and a peripheral circuit region of the semiconductor substrate and define a hole in the cell region. A lower electrode of a cylinder-type capacitor is formed to contact the bottom of the hole with a predetermined gap between the outer wall of the lower electrode and the sidewall of the hole. A dielectric layer is formed on the dielectric layer patterns and the lower electrode on the cell region. An upper electrode is formed on the dielectric layer. According to the semiconductor device and the manufacturing method thereof, a cylinder-type capacitor is formed in the cell region without generating a step difference between the cell region and the peripheral circuit region.

Abstract: A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulating films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A method of forming a copper oxide film comprises the step of forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of etching a copper film comprises the steps of forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method as recited in any one of claims 1 to 3, and removing the copper oxide film from the copper film using acid or alkali.

Abstract: A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted.

Abstract: A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Abstract: A structure having pores includes a first layer containing alumina, a second layer that includes at least one of Ti, Zr, Hf, Nb, Ta, Mo, W and Si, and a third layer with electrical conductivity, in this order, wherein the first and second layers have pores.

Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A-X-Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: Disclosed is a method for manufacturing a semiconductor device, which comprises the steps of forming a first insulating film made of a low dielectric constant material and containing carbon, subjecting the first insulating film to a surface treatment to reduce the carbon concentration of surface layer of the first insulating film, thus turning the surface layer into a low carbon concentration layer, forming a second insulating film on the low carbon concentration layer, forming a groove in the first and second insulating films for burying a metal therein, burying the metal in the groove formed in the first and second insulating films, and polishing a surface of the metal buried in the groove to thereby form a metal wiring.

Abstract: A multilayer semiconductor device includes at least one structure for transmitting electrical signals, and in particular, microwave signals. The device includes at least one electrically conductive enclosure that includes a bottom plate and a top plate in two different layers. Lateral walls connect the bottom and top plates. Electrically conductive connecting strips extend into the enclosure and are in an intermediate layer, and are electrically insulated from the enclosure. The enclosure has at least one passage through which extends electrical connections of the connecting strips, which are also electrically insulated from the enclosure.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract: A sealing dielectric layer is applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin metal diffusion barrier layer without creating pinholes in the metal diffusion barrier layer. The sealing dielectric layer is a CVD deposited film having the composition SixCy:Hz.

Abstract: Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise.

Abstract: A semiconductor package and method for manufacturing the same is disclosed. The semiconductor package comprises a semiconductor chip, a circuit board, an electrical connection means, an encapsulation material and a plurality of conductive balls. The semiconductor chip has a first surface and a second surface. A plurality of input and output pads are formed on one of the first and second surfaces. The circuit board comprises a thin film having a first surface and a second surface and being provided with a center hole in which the semiconductor chip is positioned, a plurality of circuit patterns being formed on the first surface of the thin film and including a plurality of bond fingers and ball lands, and a cover coat covering the circuit board except for the bond fingers and the ball lands. The electric connection means electrically connects the input and output pads of the semiconductor chip with the bond fingers of the circuit board.

Abstract: A semiconductor chip and an organic substrate are bonded together in an atmosphere having a reduced moisture content through Au bumps which have been subjected to a cleaning treatment therebetween. Using this bonding technique, a semiconductor chip and an organic substrate can be bonded together in a sufficiently high strength with use of Au bumps having a diameter of not larger than 300 &mgr;m, a height of not smaller than 50 &mgr;m, and a height/diameter ratio of not lower than 1/5, thus indicating a reduced strain.

Abstract: To decrease the weight and the thickness, and to increase the flexibility, of an electronics package, the package includes an integrated circuit (IC) mounted on a flexible tape substrate. In one embodiment, an IC is mounted on a flexible tape substrate using a ball grid array arrangement; however, other arrangements, including lead bonding, can be used. The flexible tape substrate can comprise conductive traces, vias, and patterns of lands on one or more layers. Methods of fabrication, as well as application of the flexible tape package to an electronic assembly, an electronic system, and a data processing system, are also described.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low-profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned-in and tested in a more efficient and cost-effective manner than prior known BGA or FBGA semiconductor packages. A high-density, low-profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: The resin-sealed semiconductor device includes a die pad portion, a semiconductor element mounted on the die pad portion and having electrodes, a plurality of lead portions arranged with their respective tips facing the die pad portion, thin metal wires for connecting the electrodes of the semiconductor element to the lead portions, and a sealing resin for sealing the die pad portion, the semiconductor element, the lead portions and connection regions of the thin metal wires except a bottom surface of the die pad portion and respective bottom surfaces and terminal ends of the lead portions. The terminal ends of the lead portions are approximately flush with a side surface of the sealing resin.

Abstract: A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.

Abstract: The present invention discloses a system for preventing the growth of marine organisms on objects which are continually submerged in water, such as a boat hull or piling. The present invention operates by having a source of air deliver air through a conduit to an underwater aeration device placed in proximity to the object which is desired to be free of the marine organisms. The present invention comprises an underwater aeration framework having a plurality of air vents therein which supply air bubbles so as to constantly keep the water in motion around the boat hull, piling or other underwater structure, thereby preventing the growth of marine flora and fauna.

Abstract: A method for manufacturing a packing made of a three-dimensional net-like structure which constitutes an internal structure of device which performs material transfer, heat exchange or mixing between gases, liquids or gas and liquid, the internal structure being divided in a plurality of chambers or channels connected to one another is provided. The three-dimensional net-like structure is made of a plurality of unit structures which are arranged continuously in vertical and horizontal directions of the three-dimensional net-like structure. Each of the unit structures is formed by converging and dispersion of three or four line elements. The method comprises a step of forming a converging section of the unit structure where the three or four line elements converge by binding the three or four line elements together.

Abstract: A method for manufacturing a packing made of a three-dimensional netlike structure which constitutes an internal structure of device which performs material transfer, heat exchange or mixing between gases, liquids or gas and liquid, the internal structure being divided in a plurality of chambers or channels connected to one another is provided. The three-dimensional net-like structure is made of a plurality of unit structures which are arranged continuously in vertical and horizontal directions of the three-dimensional net-like structure. Each of the unit structures is formed by converging and dispersion of three or four line elements. The method comprises a step of forming a converging section of the unit structure where the three or four line elements converge by binding the three or four line elements together.

Abstract: The invention comprises a water distribution mechanism for an evaporative air conditioner that alleviates splashing of water out of that mechanism. Further, the invention alleviates the problem of water running horizontally along a distribution edge of a water distribution mechanism to drip off at the lowest point. To compensate for the splashing problem, the invention comprises a structure that requires the water exiting the water distribution mechanism strike at least one surface of the water distribution mechanism on its way down. To compensate for the problem of water running horizontally because of sags and the like, the invention comprises a plurality of teeth along the bottom edge of the water distribution bonnet that therefore forces the water to drip rather than to move horizontally.

Abstract: An air diffuser (2) comprises a diffuser tube (5) immersed sidewardly in a tank (1), a flushing pipe (9) opening at its tip an outlet (11) at an upper position of the diffuser tube, and a flushing valve (12) disposed in the flushing pipe (9). The diffuser tube (5) is made up of a main pipe (6) communicated at its basal end to an air supply source (8) and communicated at its tip to the flushing pipe (9), and a plurality of branch pipes (7) being communicated to the main pipe (6) and opening at their tip as a blowhole (10) at a lower position of the main pipe (6). During air diffusion, air is supplied from the air supply source (8) with tile flushing valve (12) closed, and the air is diffused from the blowholes (10). During flushing, air is supplied from the air supply source (8) with the flushing valve (12) opened and an intra-tank mixed liquor is sucked from the openings of the diffuser tube (5), thereby flushing the inside of the diffuser tube (5) with the sucked intra-tank mixed liquor.

Abstract: A material for thermoforming comprises a plastic layer as well as a layer of reflecting pearls in an adhering transparent substance. The material is suitable for the manufacturing of a reflecting product by means by vacuum forming.

Abstract: A method for manufacturing an optical connector ferrule according to the present invention is a method for manufacturing an optical connector ferrule where a plurality of fiber holes are arranged between two guide pin holes, wherein melted material resin is injected from one resin injection port into a cavity of a forming mold where two forming pins for forming the guide pin holes and a plurality of forming pins for forming the fiber hole are arranged in parallel to one another. A forming mold according to the present invention is provided with a cavity where a plurality of forming pins can be arranged in parallel to one another, and one resin injection port through which melted material resin can be injected into the cavity.

Abstract: The invention relates to a method for obtaining artificial graphite powder for electrical engineering, manufacturing synthetic diamonds and in other fields of technology with especially high requirements for graphite purity. The novelty of the inventive method is the use of pyrolytic carbon material obtained by methane pyrolysis at a temperature of 2100-2400° C. Pyrolytic carbon obtained as a waste product of pyrolytic anisotropic material can be used as a carbon material. The method includes grinding carbon material and its graphitizing at a temperature of 2600° C.-2700° C. The inventive method simplifies the process of preparing artificial graphite powder and enhances the degree of graphitization, which improves the quality of the final product.

Abstract: A non-intrusive method of determining temperature and for controlling the Electroconsolidation process is described which is based on the change with temperature of the velocity of sound as it passes through a material. Ultrasonic transducers located outside of the die, but positioned to transmit and receive an ultrasonic signal, are used to determine an average temperature in the line of sight of the transmitted signal. A single-loop feedback system may be used to control the temperature based upon a comparison of the measured temperature to the desired temperature.

Abstract: A method of releasing pressure in a non-metallic injection mold has a pressure relief valve positioned in the molten resin flow path for handling excess resin pressure. The pressure relief valve responds to excess resin pressure in the cavity by providing an alternate resin flow path for the pressurized excess resin.