Abstract: A visible light source adapted to be mounted on the vehicle for generating visible light to be used to create warning signals which are viewed by observers remote from the vehicle. A dichroic element adapted to be mounted on the vehicle and adjacent to the visible light source transmits at least some of the visible light generated by the light source and reflects at least some of the visible light generated by the light source. The transmitted and reflected light provides warning light signals within different wavelength ranges when viewed by an observer remote from the vehicle.

Abstract: A lighting assembly for an interior rearview mirror assembly of a vehicle includes an illumination source, a reflective element and a lens. The illumination source is operable to radiate radiation including visible radiation and infrared radiation. The radiation from the illumination source impinges on the reflective element. The reflective element reflects reflected radiation toward the lens. The reflective element is adapted to at least partially transmit the infrared radiation so that reduced reflection of the infrared radiation occurs toward the lens. The lens may include an optical element which functions to substantially transmit the visible radiation through the optical element and the lens while at least partially reflecting the infrared radiation generally away from the lens.

Abstract: What is particularly worthy of illustration is that, the interlacing meshes of the upper circle and the lower circle are arranged in S-shaped curves, in both inner positions and outer positions. The purpose of the arrangement is that, the glass rods are inserted into the meshes, and slots are formed between the glass rods; and pass through the slots is the light, which is partly hidden and partly visible. Therefore, it creates a polychrome, phantom, project light source.

Abstract: A lighting device is disclosed which comprises an illuminating light source for illuminating an object, a first optical unit disposed on the side of the object of the illuminating light source and having an optical action section for diverging light or an optical action section for converging light, and a second optical unit disposed on the side of the object of the optical action section of the first optical unit and having an optical action section for exhibiting a characteristic opposite to a characteristic of the optical action section, wherein the optical action section of the second optical unit overlies the optical action section of the first optical unit in varying areas to change light distribution characteristic on the side of the object.

Abstract: A stand lamp assembly includes a stand frame unit, a main lamp unit, and an auxiliary lamp unit. The main and auxiliary lamp units are mounted on the stand frame unit. The auxiliary lamp unit includes a night lamp and a light sensor. The light sensor is connected to the night lamp, and controls activation of the night lamp in accordance with ambient light conditions.

Abstract: A method for restricting removal of a electrical lamp in a mounting bracket is provided. The mounting bracket including a first opening, a second opening and a mounting face. The method includes providing an electrical lamp including a lamp length and a plurality of lamp diameters and inserting the electrical lamp at least partly though the mounting bracket. The method further includes positioning the mounting bracket first opening adjacent a first surface such that the first surface is in close proximity to the first opening and securing the mounting face to a structure.

Abstract: A vehicle side mirror assembly including a lighted turn signal indicator. The side mirror assembly is configured to replace an existing side mirror assembly for mounting to known mirror scalps. The mirror glass is mounted to a rearward facing surface of a base plate of the mirror assembly by a piece of two-sided tape or heater panel. A printed circuit board is mounted to a forward facing surface of the base plate within a suitably shaped cavity. LEDs mounted to the circuit board are aligned with holes in the base plate. The circuit board is inserted into the cavity from an opposite side of the base plate from the mirror glass. A cover is sonically welded to the base plate to cover the cavity and hold the circuit board therein. The LEDs are illuminated in a sequential manner starting with an outermost pair of LEDs to an inner most LED.

Abstract: An infrared radiating lamp which dilutes the red light emitted from the front lens of the lamp by causing a peripheral portion of the lens to emit white light or causing a small amount of white light to pass through a generally central portion of the lens so that the lamp will not be mistakenly recognized as a tail lamp or a stop lamp. The lamp includes a lamp body, a lens attached to a front opening portion of the lamp body and which cooperates with the lamp body to define a lamp chamber, a reflector provided at an inner side of the lamp body, a light source provided forward of the reflector, and an infrared transmitting film that reflects a visible light component and transmits an infrared component. A region having no infrared transmitting film is provided at an outer periphery of the infrared transmitting film.

Abstract: Luminous intensity distribution patterns of a sub reflector and a main reflector are combined, and the combined pattern continuously changes based on a movement of the sub reflector. The main reflector and the sub reflector reflect the light from a light source to illuminate the road surface and the like in a target luminous intensity distribution pattern. As a result, it is possible to effectively utilize the light from the light source, as compared with the headlamp that makes only the main reflector reflect the light from the light source.

Abstract: The invention concerns an apparatus for illuminating a viewing field by means of two light sources. The beam paths of the two light sources are guided through a combining flexible light guide, a common flexible light guide, and a separating flexible light guide splitter. One of the two beam paths is directed to the microscope as principal illumination, and the other beam is directed to a handpiece. In addition, at least one of the two light sources can be configured as an interchangeable unit having two individual light sources.

Abstract: There is provided by this invention a dc power supply that utilizes capacitors in parallel with the diodes of the rectifier bridge in order to increase the full-power load impedance range of the power supply. In addition it has the capability to selectively couple the capacitors to the diodes over a predetermined frequency. This invention applies to both single phase and multiphase converters.

Abstract: To start a switching power supply in an energy saving manner, the method and device according to the invention transmits the energy that is collected by the Y-capacitors through a diode to a capacitor that is located on the secondary side. Once the voltage in the capacitor reaches a first predefinable minimum value, the voltage is applied to an impulse generator as an input voltage and the generator starts the switching power supply. Once the voltage in an additional capacitor on the secondary side reaches a second predefinable minimum value, the voltage in the capacitor is also applied as an input voltage to a control unit, preferably, a microprocessor, that controls the impulse generator.

Abstract: A power generation apparatus includes a permanent-magnet AC generator, a first converter for converting AC power into DC power, and a second converter for converting the DC power produced by the first converter into AC power. The first converter includes a unit for controlling active power and a unit for controlling reactive power and the second converter includes a unit for controlling a voltage of a DC system and reactive power or AC voltage of a power system.

Abstract: A power controller provides a distributed generation power networking system in which bidirectional power converters are used with a common DC bus for permitting compatibility between various energy components. Each power converter operates essentially as a customized bi-directional switching converter configured, under the control of the power controller, to provide an interface for a specific energy component to the DC bus. The power controller controls the way in which each energy component, at any moment, will sink or source power, and the manner in which the DC bus is regulated. In this way, various energy components can be used to supply, store and/or use power in an efficient manner. The various energy components include energy sources, loads, storage devices and combinations thereof.

Abstract: An electric power providing system comprising a converter control system and a DC power source. The converter control system includes an AC to DC converter electrically associatable with an outside power supply, and, a DC to AC converter electrically associated with the AC to DC converter, and, electrically associatable with a load. The DC power source is electrically associated with each of the AC to DC converter and the DC to AC converter. The DC power source is positioned between the converters. The converter control system includes a member that controls the distribution of power between an outside power supply, the DC power source and a load.

Abstract: A power generation apparatus includes a permanent-magnet AC generator, a first converter for converting AC power into DC power, and a second converter for converting the DC power produced by the first converter into AC power. The first converter includes a unit for controlling active power and a unit for controlling reactive power and the second converter includes a unit for controlling a voltage of a DC system and reactive power or AC voltage of a power system.

Abstract: Method and apparatus are disclosed for providing a constant voltage, high frequency sinusoidal output across a varying load, using either a single or multiple switch topology operating at constant frequency while maintaining high efficiency over the entire load range. This embodiment is especially suited to applications which require the sinusoidal voltage be held very close to a desired value in the presence of rapid changes in the conductance of the load, even in the sub-microsecond time domain as is common in computer applications and the like and in powering electronics equipment, especially a distributed system and especially a system wherein low voltage at high current is required.

Abstract: To permit a switched-capacitor-type stabilized power supply device to operate stably until the battery power falls considerably low, it needs to be provided with a voltage step-up circuit with a high voltage step-up factor. However, inconveniently, in a conventional switched-capacitor-type stabilized power supply device, increasing the voltage step-up factor of the voltage step-up circuit increases the difference between the voltage stepped-up by the voltage step-up circuit when the battery voltage is still high and the set output voltage, and thus lowers power conversion efficiency.

Abstract: A voltage source capable of coupling in parallel to at least one second voltage source, the second voltage source having an AC waveform to power at least one load. The voltage source includes a power supply and a controller. The controller is associated with the power supply. The controller includes an AC waveform generator which is capable of providing a waveform to an output, a sensor for sensing the AC waveform produced by the second voltage source and a member for phase shifting the AC waveform to synchronize same to the AC waveform of the second voltage source.

Abstract: A driving circuit of a DC motor includes a control circuit for providing a control signal, and a motor drive circuit commanded by the control circuit for providing respective command signals for the switches of an output power stage connected to the DC motor. The output power stage is connected to a power supply line and drives the windings of the DC motor. The driving circuit prevents generation of voltage surges having a significant magnitude on the power supply line because the driving circuit has logic circuits for preventing any substantial inversion in the direction of current flow in the supply lines when the DC motor operates as a current generator.

Abstract: A switching regulator provides load dependent output voltage regulation by sensing voltage drop across inherent DC resistance of the output inductor and secondary windings of power transformer with a first and second resistor and a capacitor and feeding back sensed voltage into an error amplifier for controlling the switching regulator. The regulator may be paralleled for more output current by connecting the outputs together and providing a common reference voltage to all the regulators.

Abstract: A frequency converter comprises a first mixer which frequency-converts an input signal with a first conversion gain in accordance with a local signal, a second mixer which frequency-converts the input signal with a second conversion gain lower than the first conversion gain in accordance with the local signal, and an adder which adds the output signals of the first and second mixers in opposite phase to each other in order to reduce distortion.

Abstract: A method and circuit for detecting multiple match conditions in a content addressable memory is disclosed. The circuit detects the multiple matches using a transistor array which is arranged as logical AND and OR gates. A current sensing detector provides multiple match detection when a current path is established through the transistor array when a multiple match exists.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A system for providing stability for a low power static random access memory (SRAM) cell (10) is provided that includes a wordline (14), a driver (34) and a mode selector (36). The wordline (14) is coupled to the SRAM cell (10). The wordline (14) is operable to select the SRAM cell (10) for read and write operations when activated and to de-select the SRAM cell (10) when de-activated. The driver (34) is coupled to the wordline. The driver (34) is operable to activate and de-activate the wordline (14). The mode selector (36) is coupled to the driver (34). The mode selector (36) is operable to provide a mode signal (44) to the driver (34) to place the wordline (14) into one of a plurality of modes.

Abstract: A static memory device that utilizes differential current bit line drivers to write information into the device's memory cells, and differential current sensing read amplifiers to read information from the cells. The drivers and amplifiers operate using limited differential current. The use of limited differential current, as opposed to voltages, reduces the power consumed by the device and increases the speed of read and write operations.

Abstract: A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

Abstract: A non-volatile memory device comprising a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has a plurality of memory cells. The sense circuitry is used to monitor the logic state of the memory cells. In addition, the memory device has an input connection to couple an external reference current to the sense circuitry to be used during the programming of the reference memory cell.

Abstract: Binary mode memory cells each storing data of a single bit per cell and multilevel mode memory cells each storing data of multi bits per cell are allocated with different address regions in a fixed manner and are formed in different regions. According to the fixed address allocation, the binary mode memory cells and the multilevel mode memory cells can be optimized individually and separately. In this way, the reliability of a nonvolatile semiconductor memory device is improved and the area occupied by the memory arrays is reduced.

Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

Abstract: This invention provides a circuit and a method for providing an override voltage to control gates through boosting of a selected word line for TWIN metal oxide, nitride semiconductor MONOS memory. The boosted voltages are required to program, erase and read the 2-bit MONOS memory cell in this invention. This invention relates to providing a means of using capacitive coupling between selected word lines and neighboring control gates to boost the voltage for the program, erase and write modes of MONOS memory. Capacitive coupling to boost the voltage on the control gates adjacent to the selected word lines is used instead of generating the required boosted voltage through the control gate and bit line decoders and drivers. This voltage boosting method saves address decoder silicon area, decoder circuit complexity, reduces address decode set-up time, and eliminates the need for extra voltage supplies for address decoders.

Abstract: A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

Abstract: In erasing operation, a main bit line discharge signal CPO is set at a voltage of Vss so as for a main bit line discharge transistor CP to put a main bit line BL in a floating state. A substrate signal is set at Vds to charge a local bit line LBL to Vds. A drain select gate signal DSG is set at Vleg (<(Vds+Vth)) which makes a half-conducting state between the main bit line BL and the local bit line LBL. Thereby, the main bit line BL is charged to Vmbl (=Vleg−Vth(ST)) which lowers potential differences between a drain and a source of the select transistor ST and between a drain and a source of the main bit line discharge transistor CP.

Abstract: A data output circuit for a memory device is disclosed. By decoding plural data signals and by operating output transistors coupled to different driving voltages and having a single output terminal, the interface with an outside circuit is performed through the single output terminal. The output terminal outputs output signals having voltage levels different from each other. Thus, the number of interface terminals, the instant consumption of current, the area of a pad, and the area of a chip are reduced.

Abstract: A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

Abstract: A method and apparatus for testing memory arrays where the addresses associated with such arrays exceeds the physical boundaries of the array. Addresses that are outside the physical boundary of the array are considered invalid addresses; while those residing within the physical boundaries are considered valid addresses. The method and apparatus tests the memory array by only loading data into the data out latch of the memory array when a valid address is received.

Abstract: A system for data transfer between different clock domains, and for efficiently obtaining the status of a memory device utilized during the process of data transfer. The different clock domains include a first clock domain controlled by a first frequency and a second clock domain controlled by a second frequency different from the first frequency. The system features a first counter circuitry operating at the first clock frequency which increments in response to a write control signal. The system further features first and second sync circuitries for translating write and read signals, and a second counter circuitry operating at the second clock frequency, which decrements in response to the read control signal. In addition, the first circuitry decrements in response to the read signal while the second circuitry increments in response to a write signal. In this manner, the first and second counter circuitries reflect the status of the memory device used for buffering data during the data transfer.

Abstract: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line.

Abstract: A method of transferring a block of data from a first to a second circular buffer of a computer system. The method comprises notifying the DMA controller of the source and destination addresses for the transfer, the sizes of the circular buffers, and the size of the data block to be transferred. At the DMA controller, respective base and rollover addresses of the circular buffers are identified. Data is read from the first circular buffer starting at the source address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached. Data is written to the second circular buffer starting at the destination address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached.

Abstract: The text format of input data is checked, and is converted into a system-manipulated format. It is further determined if the input data is in an HTML or e-mail format using tags, heading information, and the like. The converted data is divided into blocks in a simple manner such that elements in the blocks can be checked based on repetition of predetermined character patterns. Each block section is tagged with a tag indicating a block. The data divided into blocks is parsed based on tags, character patterns, etc., and is structured. A table in text is also parsed, and is segmented into cells. Finally, tree-structured data having a hierarchical structure is generated based on the sentence-structured data. A sentence-extraction template paired with the tree-structured data is used to extract sentences.

Abstract: A ferromagnetic thin-film based digital memory cell with a memory film of an anisotropic ferromagnetic material and with a source layer positioned on one side thereof so that a majority of conduction electrons passing therefrom have a selected spin orientation to be capable of reorienting the magnetization of the film. A disruption layer is positioned on the other side of the memory film so that conduction electrons spins passing therefrom are substantially random in orientation. The magnitude of currents needed to operate the cell can be reduced using coincident thermal pulses to raise the cell temperature.

Abstract: A semiconductor memory such as 256 KB-memory has a memory cell array divided into a plurality of memory blocks, and a defective memory block exists in the memory cell array. In this case, for example, to relive the 256 KB-memory as a 192 KB-memory not including the defective memory block of 64 KB, identification information identifying the defective memory block is stored in a relief condition storing unit, an address sent from an address bus is changed according to the identification information, and a changed address is input to a decoder of the memory cell array. For example, because a memory block of an address (0, 0) is not guaranteed, in cases where a physical address (0, 1) is assigned to the defective memory block, the address change is performed so as to change an address (0, 0) sent from the address bus to the address (0, 1) of the defective memory block.

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for coupl

Abstract: Leakage detection in a programming algorithm for a flash memory device. According to one embodiment of the present invention a method includes programming a first flash cell in an array of flash cells in a flash memory device, sequentially selecting flash cells connected to the first flash cell, testing each selected flash cell to determine if the selected flash cell is leaky, and applying a refresh pulse to the selected flash cell if the selected flash cell is leaky. According to another embodiment of the present invention a flash memory device includes an array of flash cells, a program circuit to apply a programming pulse to program a first flash cell in the array, and a control circuit including elements to sequentially select flash cells connected to the first flash cell, test each selected flash cell to determine if the selected flash cell is leaky, and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.

Abstract: Leakage detection in a programming algorithm for a flash memory device. According to one embodiment of the present invention a method includes programming a first flash cell in an array of flash cells in a flash memory device, sequentially selecting flash cells connected to the first flash cell, testing each selected flash cell to determine if the selected flash cell is leaky, and applying a refresh pulse to the selected flash cell if the selected flash cell is leaky. According to another embodiment of the present invention a flash memory device includes an array of flash cells, a program circuit to apply a programming pulse to program a first flash cell in the array, and a control circuit including elements to sequentially select flash cells connected to the first flash cell, test each selected flash cell to determine if the selected flash cell is leaky, and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.

Abstract: During a read operation, data read from memory cells onto bit lines are amplified simultaneously by sense amplifiers and outputted to the exterior of a memory. In this operation, a data control circuit outputs to the exterior all the data read from the memory cells onto the bit lines and amplified simultaneously by the sense amplifiers. During a write operation, data supplied from the exterior to the bit lines are amplified by the sense amplifiers and written into the memory cells. In this operation, the data control circuit writes into the memory cells all the data inputted from the exterior and amplified simultaneously by the sense amplifiers. Since all the data amplified simultaneously by the sense amplifiers are inputted/outputted from/to the exterior, the data transfer rate of the input/output data can be improved and the power consumption per unit amount of transferred data can be reduced.

Abstract: To prevent a resistive delay in a bitline disconnecting circuit, an NMOS latch composing a part of a CMOS latch is composed of four series NMOS transistors, two of which have respective gate electrodes cross-coupled directly to a pair of bitlines without the interposition of the bitline disconnecting circuit therebetween and the other two of which have respective gate electrodes cross-coupled to a pair of first-stage output nodes in a stage subsequent to the bitline disconnecting circuit.

Abstract: A memory system and a semiconductor memory device, which are capable of increasing memory bus efficiency and a refresh method of the semiconductor memory device are provided. A method for refreshing an open bank of a semiconductor memory device with a memory controller in a memory system including a plurality of semiconductor memory devices and the memory controller for controlling the plurality of semiconductor memory devices includes (a) applying a refresh command to each of the plurality of semiconductor memory device in order to the open bank; (b) precharging the open bank with each of the plurality of semiconductor memory devices if the refresh command is applied to the each of the plurality of semiconductor memory devices; and (c) refreshing the precharged bank with each of the plurality of semiconductor memory devices.