Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).

Abstract: Minute or infinitesimal amounts of fluid can be accurately delivered through microchannels formed in an elastic polymeric substrate. External (mechanical) force is applied on the substrate to progressively squeeze the microchannel along its length to push or pull the fluid through the microchannel. Fluids can be delivered at a constant rate and amount regardless of the kind of the fluid since fluid delivery is not affected by the physical properties of the fluid. The delivery rate of the fluid is determined in the ranges between femtoliters/sec and milliliters/sec by the size of the microchannel and the area of the substrate being pressed by the applied external (mechanical) force. Such techniques of fluid delivery can be applied to various fields including lab-on-a-chip technology, monitoring of chemical and biological processing, portable analyzing instruments, fine chemistry, clinical diagnosis and development of new medicines.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.

Abstract: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.

Abstract: An architecture to efficiently handle primary input and output signals for an embedded FPGA core in an ASIC is disclosed. Only the FPGA core is used without wire-bonding pads and pad ring found in conventional embedded FPGAs. The input and outputs of the embedded FPGA core can be made peripherally or at selected locations throughout the core to obtain high I/O-to-logic ratios and flexibility in I/O placement with high routability.

Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.

Abstract: A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. A gate is formed overlying the polycrystalline film. The polycrystalline film is doped to produce source and drain regions.

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract: A display device using a novel semiconductor device, which includes a pixel matrix, an image sensor, and a peripheral circuit for driving those, that is, which has both a camera function and a display function, and is made intelligent, is provided and a method of manufacturing the same is also provided. One pixel includes a semiconductor device for display and a semiconductor for light reception, that is, one pixel includes semiconductor devices (insulated gate-type field effect semiconductor device) for controlling both display and light reception, so that the display device having a picture reading function is made miniaturized and compact.

Abstract: A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in contact with the lower side of the gate electrode side walls, and upper side wall spacers that are composed of silicon nitride films and are in contact with the upper side of the gate electrodes side walls. As a result thereof, a distance is formed between the substrate and the interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurrence of poor contact.

Abstract: A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor.

Abstract: One-transistor memory cell arrangement and method for fabricating it

Abstract: Arrangement of trenches in a semiconductor substrate, in particular for trench capacitors

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A method of forming a metal-insulator-metal capacitor. A substrate is provided and then a first dielectric layer is formed over the substrate. The first dielectric layer is patterned to form a first opening for forming a desired lower electrode and a second opening for forming a desired conductive line. A first metallic layer conformal to the exposed surface of the first opening and completely filling the second opening is formed. A conformal capacitor dielectric layer is formed over the first metallic layer and then a second dielectric layer is formed over the capacitor dielectric layer. The second dielectric layer is patterned to form a third opening above the first opening and a fourth opening above the second opening. The third opening exposes a portion of the capacitor dielectric layer and the fourth opening exposes a portion of the first metallic layer. Finally, a second metallic layer that completely fills the third opening and the fourth opening is formed.

Abstract: An integrated circuit device with high Q MIM capacitor and its forming process are disclosed. The MIM capacitor dielectric layer is formed of a material which has relatively high dielectric constant and can be used as an anti-reflection coating (ARC). In the process of patterning MIM capacitor electrodes, the MIM capacitor dielectric layer can be directly used as an anti-reflection layer. Therefore, there is no need to form an anti-reflection layer on the metal layer, and the complexity and the cost of forming process can decrease.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: The formation of a barrier layer over a high k dielectric layer and deposition of a conducting layer over the barrier layer prevents intermigration between the species of the high k dielectric layer and the conducting layer and prevents oxygen scavenging of the high k dielectric layer. One example of a capacitor stack device provided includes a high k dielectric layer of Ta2O5, a barrier layer of TaON or TiON formed at least in part by a remote plasma process, and a top electrode of TiN. The processes may be conducted at about 300 to 700° C. and are thus useful for low thermal budget applications. Also provided are MIM capacitor constructions and methods in which an insulator layer is formed by remote plasma oxidation of a bottom electrode.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A structure of a flash memory is provided. The flash memory has a charge trapping layer, a gate and a source/drain region, wherein the charge trapping layer is formed by stacking in sequence a first oxide layer, a dielectric layer of high dielectric constant material and a second oxide layer. The gate is arranged on the charge trapping layer, and the source/drain region is arranged at the two lateral sides of the substrate.

Abstract: A semiconductor device having an isolation region formed in a semiconductor substrate and a capacitance device formed above that isolation region. The capacitance device has a first capacitor conductive layer disposed above the isolation region and a second capacitor conductive layer in the shape of a side wall formed along one side surface of the first capacitor conductive layer. The second capacitor conductive layer is disposed facing the first capacitor conductive layer, with a first capacitor insulating layer interposed.

Abstract: A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and control gates, are arranged in first and second directions. The memory cell array region has a plurality of sector regions divided in the second direction. Each of a plurality of control gate drivers is capable of setting a potential of first and second control gates in the corresponding sector region independently of other sector regions. A plurality of switching elements which select connection/disconnection are formed at connections between a plurality of main bit lines and a plurality of sub bit lines.

Abstract: An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a gate electrode layer constituting a sensing line. This leads to increases in opposite areas of a floating gate and a control gate of a sensing transistor, and a decrease in an area of the floating gate in the substrate.

Abstract: A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side of the semiconductor body. A drift zone adjoins the first connection zone and extends in a vertical direction of the semiconductor body as far as the second side of the semiconductor body. A body zone of a second conductivity type is disposed between the second connection zone and the first connection zone or the drift zone. A control electrode is insulated from the semiconductor body and disposed above the body zone such that the control electrode substantially does not overlap with the drift zone and the second connection zone in a lateral direction. A method for manufacturing a semiconductor component is also provided.

Abstract: Semiconductor device and method for fabricating the same, the device including a semiconductor substrate, a recessed channel region recessed below a surface of the semiconductor substrate, and a gate oxide film formed on the recessed channel region, a first and a second lightly doped impurity regions in surfaces of the substrate adjacent to, and on both sides of the recessed channel region respectively, and a first and a second highly doped impurity regions adjacent to the first and second lightly doped impurity regions, respectively, inverted sidewalls on the first and second lightly doped impurity regions each having a round in a side of the recessed channel region, and a gate electrode both on the inverted sidewalls and the recessed channel region, whereby securing a fabrication allowance and improving a device packing density.

Abstract: A semiconductor device includes a gate to control the semiconductor device, a drain coupled to the gate, a source to form a current path with the drain, which is formed in a well of a first type of material, a field oxide coupled to the gate, and a channel stop formed under the field oxide and formed of a second type of material.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to said first conductive type and incorporating the impurity contained in said impurity gas into the surface of said semiconductor substrate, thereby modifying the type and/or the intensity of the conductive type thereof. Provides devices having a channel length of 0.5 &mgr;m or less and impurity regions 0.1 &mgr;m or less in depth.

Abstract: A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

Abstract: Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.

Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting substantially the same function as the lightly doped drain regions, wherein the lightly activated high impurity concentration regions are bounded with high impurity concentration regions serving as source and drain regions. The boundaries are self-aligned to edges of a gate electrode. Side regions of the gate electrode overlap the lightly activated high impurity concentration regions.

Abstract: A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a resistive element (6). The density of crystal defects in the second regions (52, 62) is higher than that in first regions (51, 61). The density of crystal defects in a polycrystalline silicon film (70) for a resistive element (7) is higher near a silicide film (73). A polycrystalline silicon film (80) for a resistive element (8) is in contact with a substrate (2) with a silicide film in an opening of an isolation insulating film (3). The density of crystal defects in a substrate surface (2S) near the silicide film is higher than that in the vicinity. With such a structure, a current leak in an isolation region can be reduced.

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Abstract: An object of the invention is to provide a technique for improving the characteristics of a TFT and realizing an optimum structure of the TFT for the driving conditions of a pixel section and a driving circuit by a small number of photo masks. Therefore, a light emitting device has a semiconductor film, a first electrode and a first insulating film nipped between the semiconductor film and the first electrode. Further, the light emitting device has a second electrode and a second insulating film nipped between the semiconductor film and the second electrode. The first and second electrodes are overlapped with each other through a channel forming area arranged in the semiconductor film. In the case of a TFT in which a reduction in off-electric current is considered important in comparison with an increase in on-electric current, a constant voltage (common voltage) is applied to the first electrode at any time.

Abstract: A semiconductor transistor on a substrate, the transistor comprising activated source, drain and gate regions, and a channel region between the source and drain region, the channel underlying the gate region and wherein at least a portion of the gate region comprises a thermally non-degraded high dielectric constant material.

Abstract: Micromachine systems are provided. An embodiment of such a micromachine system includes a substrate that defines a trench. First and second microelectromechanical devices are arranged at least partially within the trench. Each of the microelectromechanical devices incorporates a first portion that is configured to move relative to the substrate. Methods also are provided.

Abstract: The leads of a light emitting device package are extended as flexible pins. These pins can be bent with respect to a motherboard so that the direction of the light emitted from the light emitting device can be adjusted. The package is tab-mounted to the motherboard for heat sinking or serving as a lead.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: A method of forming a semiconductor substrate having a plurality of epitaxial regions disposed at different lateral locations, includes assembling a plurality of epitaxial layers vertically adjacent to each other on a host substrate to form an epitaxial structure; etching a surface of the epitaxial structure to reveal epitaxial regions of the epitaxial layers at different lateral locations on the host substrate; and wafer bonding the etched surface of the epitaxial structure to a transfer substrate.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.

Abstract: A thermoelectric infrared detector comprising a substrate and two kinds of conducting pillars. The pillars longitudinally extend away from the substrate towards incident infrared radiation. The pillars have upper, hot ends remote from the substrate and lower ends at the substrate. Pairs of adjacent pillars of different kinds are electrically connected by a conducting junction at their upper ends, and thereby define thermocouples. The junctions of different pairs of pillars are exposed to the incident radiation.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

Abstract: A silicided polysilicon based fuse device that is programmable by optical and electrical energy in the polysilicon layer without damage to nearby structures, comprising: