Patents Issued in February 6, 2003
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Publication number: 20030025178Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.Type: ApplicationFiled: August 6, 2001Publication date: February 6, 2003Inventors: Gregory G. Romas, Rex W. Pirkle
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Publication number: 20030025179Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.Type: ApplicationFiled: July 22, 2002Publication date: February 6, 2003Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Byung-Kwon Han
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Publication number: 20030025180Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.Type: ApplicationFiled: August 1, 2001Publication date: February 6, 2003Applicant: International Business Machines CorporationInventors: David James Alcoe, Jeffrey Thomas Coffin, Michael Anthony Gaynes, Harvey Charles Hamel, Mario J. Interrante, Brenda Lee Peterson, Megan J. Shannon, William Edward Sablinski, Christopher Todd Spring, Randall Joseph Stutzman, Renee L. Weisman, Jeffrey Allen Zitz
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Publication number: 20030025181Abstract: A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.Type: ApplicationFiled: November 14, 2001Publication date: February 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mako Okamoto, Yasuhiko Taito, Fukashi Morishita, Akira Yamazaki, Nobuyuki Fujii
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Publication number: 20030025182Abstract: In accordance with a first aspect of the invention, a metal substrate is provided with a layer of tin or tin alloy that is coated under tensile stress to inhibit the growth of tin whiskers. The tensile stressed tin and tin alloy is preferably coated with a grain size larger than 1 micrometer. Advantageously the tin or tin alloy is coated on an underlayer chosen to maintain or generate the tensile stress state in the tin coating. The tensile stress inhibits whisker growth, and the resulting structure is particularly useful as a part of an electrical connector or lead frame. In a second aspect of the invention, the tensile stress of tin coatings is monitored to provide coatings of reduced tendency toward whisker growth.Type: ApplicationFiled: June 22, 2001Publication date: February 6, 2003Inventors: Joseph A. Abys, Chonglun Fan, Chen Xu, Yun Zhang
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Publication number: 20030025183Abstract: A semiconductor packaging technique provides for a semiconductor device with improved electrical and thermal performance. According to one embodiment of the invention, die edges are shaped before encapsulation to move the peripheral area of the die, which is more susceptible to stress and cracking, further inside the molding compound. This results in a device that can better withstand stress as well being more resistant to corrosion and other reliability problems caused by environmental conditions.Type: ApplicationFiled: July 31, 2002Publication date: February 6, 2003Applicant: Fairchild Semiconductor CorporationInventors: Neill Thornton, Dennis Lang
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Publication number: 20030025184Abstract: The invention provides a highly reliable, small sized stacked level semiconductor device with high density at low costs, and also methods for manufacturing the same. The semiconductor device can include a second semiconductor chip that is disposed on a surface of a first semiconductor chip. The semiconductor device can also include metal posts for taking out electrodes formed on a surface of the first semiconductor chip, metal posts for taking out electrodes formed on a surface of the second semiconductor chip, and a resin that seals the surface of the first semiconductor chip, the metal posts, the second semiconductor chip and the metal posts. Accordingly, the present invention can provide highly reliable, small sized stacked level semiconductor devices at low costs.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Seiko Epson CorporationInventor: Yukio Morozumi
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Publication number: 20030025185Abstract: An FBGA packaged device including a die adhered to a substrate with a small gap being formed between the die and substrate. An opening is formed through the substrate adjacent the center portion of the die. An encapsulating mold is formed around the die extending into the gap and also filling the channel. At least one barrier is disposed in the gap between the substrate and the die adjacent the channel to control the flow path of the encapsulating material as the mold is formed in the package.Type: ApplicationFiled: September 30, 2002Publication date: February 6, 2003Inventors: Lim T. Chye, Lee C. Kuan, Jeffrey Toh, Tim Teoh, Patrick Guay, Choong L. Wah
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Publication number: 20030025186Abstract: An electronic module (6) suitable for producing contactless cards (1) and/or contactless electronic labels, and comprising a carrier (10) for an electronic microcircuit (7) connectable to an antenna (2) to enable contactless operation of the module (6). The whole of the antenna (2) is arranged on the electronic module (6) and the turns lie in the plane of the carrier substrate (10). Said electronic module (6) is useful for producing contactless cards and electronic labels.Type: ApplicationFiled: September 25, 2002Publication date: February 6, 2003Applicant: Gem plusInventors: Michel Leduc, Philippe Martin, Richard Kalinowski
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Publication number: 20030025187Abstract: A protective device is described for subassemblies having a substrate and components disposed thereon and to be protected, for example semiconductor components. The protective device has at least one covering element for covering a subassembly, and at least one compression prevention element, which is disposed between the at least one covering element and the substrate and which is connected to the substrate and a surface of the covering element which faces the components and the substrate in such a way that a predefined spacing between covering element and the components to be protected can be maintained or is maintained.Type: ApplicationFiled: August 1, 2002Publication date: February 6, 2003Inventors: Volker Strutz, Uta Gebauer, Thorsten Meyer
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Publication number: 20030025188Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.Type: ApplicationFiled: October 4, 2002Publication date: February 6, 2003Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
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Publication number: 20030025189Abstract: A semiconductor package is provided that includes a flat leadframe having front and rear faces. The leadframe includes a central platform and elongate electrical connection leads distributed around this platform. Electrical connection wires connect the chip to the front face of the leads, and encapsulation means encapsulates the chip such that the rear face of the leadframe is visible. The electrical connection leads include an inner end part and an outer end part, the rear faces of the inner and outer end parts lie in the plane of the rear face of the leadframe, and the inner and outer end parts are connected by a branch whose rear face is set back with respect to the plane of the rear face of the leadframe so as to define a rear recess. The electrical connection wires are connected to the leads on the front face of their inner end part.Type: ApplicationFiled: May 31, 2002Publication date: February 6, 2003Applicant: STMICROELECTRONICS S.A.Inventor: Jean-Luc Diot
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Publication number: 20030025190Abstract: A tape ball grid array (TBGA) package having improved thermal reliability includes a semiconductor chip mounted on a tape circuit board having a base film, ball land pads, and board junction pads, wherein the semiconductor chip is attached to a first surface of the base film, the ball land pads are formed on an opposite, second surface of the base film, and the board junction pads are formed on either side of the base film. Each one of the board junction pads is electrically connected to a corresponding ball land pad using routings and/or via holes and to an associated chip pad by a bonding wire. A package body is formed by encapsulating the assembly, and external contact terminals, each one being attached to one of the ball land pads.Type: ApplicationFiled: July 2, 2002Publication date: February 6, 2003Inventors: Hyung Jik Byun, Jin Ho Kim
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Publication number: 20030025191Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.Type: ApplicationFiled: July 2, 2002Publication date: February 6, 2003Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
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Publication number: 20030025192Abstract: An electrically conductive article such as a sheet having holes therein is coated with a dielectric polymer using a multi-stage electrophoretic deposition process. A coating of uncured polymer is deposited electrophoretically and then cured. After the first polymer is cured, the part is subject to a further electrophoretic deposition process and further curing. Use of a second electrophoretic deposition step allows effective coating of parts having small holes without plugging the holes. The coated parts may be used as microelectronic connection components such as chip carriers used in packaging semiconductor chips.Type: ApplicationFiled: September 25, 2002Publication date: February 6, 2003Applicant: Tessera, Inc.Inventor: Belgacem Haba
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Publication number: 20030025193Abstract: Provided is a method of manufacturing a semiconductor laser device capable of reducing time required for manufacture and preventing deterioration in performance due to heating, and a mounting plate and a supporting plate which are used in the method of manufacturing a semiconductor laser device. A semiconductor laser device is formed by stacking a laser chip, a sub-mount and a heat sink and adhering them to each other. The laser chip has a structure such that a p-side electrode and an n-side electrode are formed on the same surface of the crystalline substrate. The sub-mount has a structure such that a front face solder film and a back face solder film are formed on front and back surfaces of a supporting body, respectively. When the laser chip, the sub-mount and the heat sink are stacked, the front face solder film is positioned between the laser chip and the sub-mount and the back face solder film is positioned between the sub-mount and the heat sink.Type: ApplicationFiled: September 30, 2002Publication date: February 6, 2003Inventor: Masafumi Ozawa
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Publication number: 20030025194Abstract: A protective device is provided for subassemblies having a substrate and a component disposed thereon and needing to be protected. The component typically is a semiconductor component. The protective device includes a covering element, a spacer, and a guide. The covering element covers a subassembly. The spacer is disposed between the covering element and the substrate for maintaining a predefined spacing between the covering element and the component to be protected in the area of the spacer. The guide is used for fixing a free end of the spacer to the covering element and/or to the substrate in a predefined X and/or Y position.Type: ApplicationFiled: August 1, 2002Publication date: February 6, 2003Inventors: Uta Gebauer, Volker Strutz
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Publication number: 20030025195Abstract: The present invention is a semiconductor apparatus having at least a part of a semiconductor device conjugated to a metal material for heat sink via an electric insulating material, wherein said electric insulating material is a bismuth glass layer.Type: ApplicationFiled: March 18, 2002Publication date: February 6, 2003Applicant: HITACHI, LTD.Inventors: Takayoshi Nakamura, Ryuichi Saito, Akihiro Tamba, Takashi Naitou, Hiroki Yamamoto, Takashi Namekawa
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Publication number: 20030025196Abstract: The present invention is a semiconductor apparatus having at least a part of a semiconductor device conjugated to a metal material for heat sink via an electric insulating material, wherein said electric insulating material is a bismuth glass layer.Type: ApplicationFiled: July 30, 2002Publication date: February 6, 2003Applicant: HITACHI, LTD.Inventors: Takayoshi Nakamura, Ryuichi Saito, Akihiro Tamba, Takashi Naitou, Hiroki Yamamoto, Takashi Namekawa
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Publication number: 20030025197Abstract: A first electronic device, a second electronic device which generates less heat than the first electric device, and an electrode are connected by a heat leveling plate formed of an electrically conductive material having high thermal conductivity. A heat radiation plate is provided below an insulated substrate to which the first and second electronic devices are mounted. The second electronic device is cooled by a heat radiation path which extends through the insulated substrate and the heat radiation plate and a heat radiation path which extends through the second electronic device and the electrode to the heat radiation plate. The first and the second electronic device have substantially the same temperature due to heat radiation through the heat leveling plate. As a result, cooling effect of the electronic devices can be enhanced.Type: ApplicationFiled: October 3, 2002Publication date: February 6, 2003Inventors: Makoto Imai, Naoki Ogawa, Yuji Yagi, Takashi Kojima, Yasushi Yamada
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Publication number: 20030025198Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Inventors: Gregory M. Chrysler, Abhay A. Watwe, Sairam Agraharam, Kramadhati V. Ravi, C. Michael Garner
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Publication number: 20030025199Abstract: A super low profile package with stacked dies comprises a substrate, a heat spreader, a first die, a second die, a molding compound, and a number of solder balls. The substrate has a cavity, a top surface and a bottom surface opposite to the top surface. The heat spreader is connected to the bottom surface of the substrate, and a portion of the heat spreader opposite to the cavity serves as a die pad. The first die seated in the cavity is attached to the die pad while the second die seated in the cavity is attached to the first die, and both dies are wire-bonded to the substrate for electrical connection. The molding compound fills the cavity and encapsulates the first die, the second die, the heat spreader, and part of the bottom surface of the substrate. Numerous solder balls are attached to the bottom surface of the substrate. The benefits resulting from the package of the invention include a reduction of profile, a simple manufacturing process, and a low prime cost.Type: ApplicationFiled: December 27, 2001Publication date: February 6, 2003Inventors: Chi-Chuan Wu, Tzong-Dar Her
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Publication number: 20030025200Abstract: A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.Type: ApplicationFiled: June 24, 2002Publication date: February 6, 2003Inventors: Nobuhito Katsumura, Yoshiteru Katsumura, Hidemi Sato, Norihiro Uchida, Fumiyuki Kanai
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Publication number: 20030025201Abstract: An integrated circuit chip in which enlarged lands are provided at four corners of the bottom surface of the integrated circuit chip, and a large amount of cream solder adheres to the enlarged lands, so that the four corners of the integrated circuit chip are firmly soldered to a mother board, as a result of which, even if an external force is applied when, for example, the integrated circuit chip and the mother board are subjected to shock or are twisted, the relative position between them does not easily change. In addition, even if a portion between the integrated circuit chip and the mother board is not reinforced by injecting an insulating adhesive therebetween, it is possible to provide a highly reliable integrated circuit chip, to increase working efficiency during the mounting process of the IC chip, and to reduce the possibility of solder connection portions becoming damaged due to changes in environmental temperature.Type: ApplicationFiled: July 9, 2002Publication date: February 6, 2003Inventor: Hiroshi Harada
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Publication number: 20030025202Abstract: An external electrode in a semiconductor device includes, from the bottom of a wafer, a wiring pad, first and second barrier metal layers, a solder-wetting film and a solder ball. The first barrier metal layer has a tensile internal stress and a granular crystalline structure, whereas the second barrier metal layer has a compressive internal stress and a pillar crystalline structure. The two-layer structure of the barrier metal film has an excellent barrier function against Sn diffusion from the solder ball and reduces the internal stress of the barrier metal film.Type: ApplicationFiled: July 17, 2002Publication date: February 6, 2003Applicant: NEC CorporationInventors: Kaoru Mikagi, Akira Furuya, Keisuke Hatano
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Publication number: 20030025203Abstract: The present invention relates to an improved method of forming and structure for under bump metallurgy (“UBM”) pads for a flip chip which reduces the number of metal layers and requires the use of only a single passivation layer to form, thus eliminating a masking step required in typical prior art processes. The method also includes repatterning bond pad locations.Type: ApplicationFiled: September 23, 2002Publication date: February 6, 2003Inventors: Salman Akram, Alan G. Wood
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Publication number: 20030025204Abstract: In a ball grid array type semiconductor device including an interposer substrate having first and second surfaces, a semiconductor chip mounted on the first surface of the interposer substrate, and solder balls formed on the second surface of the interposer substrate, a plurality of through holes are formed within the interposer substrate, and each of the solder balls clogs one of the through holes of the interposer substrate.Type: ApplicationFiled: May 23, 2000Publication date: February 6, 2003Inventor: Hiroshi Sakai
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Publication number: 20030025205Abstract: Cell terminals in an integrated circuit is interconnected by using multiple layers of conductors that are routed both orthogonally and non-orthogonally to each other. Non-orthogonally routed conductors have slopes that are ratios of non-zero integers which approximate ceratin predetermined angles. The integers in the ratios are chosen from integers generated by sequence equations. The conductors are routed by following grid lines in a grid system comprising both orthogonal grid lines and non-orthogonal grid lines having slopes generated by the sequence equations. Ratios of integers are used to approximate certain angles so that the conductors would intersect the cell terminals located on the fundamental grid intersection points. The conductors in different metal layers form different angles with other conductors in other metal layers based on the slopes of the conductors.Type: ApplicationFiled: May 17, 2001Publication date: February 6, 2003Inventor: John Shively
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Publication number: 20030025206Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Inventors: Ammar Derraa, Sujit Sharan, Paul Castrovillo
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Publication number: 20030025207Abstract: The portion of a lower-layer wiring contacting with a metal film in a via hole is a copper silicide layer. Moreover, a laminated structure of a titanium-nitride-silicide layer and a titanium nitride film or the laminated structure of a metal film, titanium-nitride-silicide layer, and titanium nitride film is formed between an insulating film and a wiring copper film embedded in a concave portion formed in the insulating film.Type: ApplicationFiled: July 31, 2002Publication date: February 6, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Takeshi Harada
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Publication number: 20030025208Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.Type: ApplicationFiled: March 1, 2002Publication date: February 6, 2003Applicant: Fujitsu LimitedInventors: Kozo Makiyama, Naoya Ikechi, Takahiro Tan
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Publication number: 20030025209Abstract: A plurality of metal interconnections are formed on a semiconductor substrate. The semiconductor substrate is held on a sample stage in a reactor chamber of a plasma processing apparatus and a material gas containing C5F8, C3F6, or C4F6 as a main component is introduced into the reactor chamber, so that a first fluorine-containing organic film having cavities at positions between the metal interconnections is deposited between the metal interconnections and on the top surfaces of the metal interconnections.Type: ApplicationFiled: September 27, 2002Publication date: February 6, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuhiro Jiwari, Shinichi Imai
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Publication number: 20030025210Abstract: A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.Type: ApplicationFiled: September 26, 2002Publication date: February 6, 2003Inventors: Calvin K. Li, N. Johan Knall, Michael A. Vyvoda, James M. Cleeves, Vivek Subramanian
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Publication number: 20030025211Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.Type: ApplicationFiled: October 3, 2002Publication date: February 6, 2003Inventors: Ted Bruce, John A. Forthun
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Publication number: 20030025212Abstract: In one embodiment of the present invention, a highly reflective dielectric stack is formed on the mesa wall of a flip-chip LED. The layers of the dielectric stack are selected to maximize reflection of light incident at angles ranging from −10 to 30 degrees, relative to the substrate. The dielectric stack is comprised of alternating low refractive index and high refractive index layers. In some embodiments, the LED is a III-nitride device with a p-contact containing silver, the dielectric stack layer adjacent to the mesa wall has a low refractive index compared to GaN, and the low refractive index layers are Al2O3.Type: ApplicationFiled: May 9, 2001Publication date: February 6, 2003Inventors: Jerome Chandra Bhat, Daniel Alexander Steigerwald
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Publication number: 20030025213Abstract: Device for attaching a semiconductor chip to a chip carrier In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22, 24) arranged on a surface of the semiconductor chip (10) and contact areas (26, 28) on the chip carrier (12) by means of an anisotropically conducting film (16) or an anisotropically conducting paste (16), a pressure die (18) is used for the application of the pressure to the chip (10) with an adjustable pressing force against the chip carrier (12). A counter-pressure support (14) accepts the chip carrier (12) with the semiconductor chip (10) arranged on it with the interposition of the anisotropically conducting film (16) or the anisotropically conducting paste (16). An elastic body (20) is arranged either between the pressure die (14) and the semiconductor chip (10) or between the chip carrier (12) and the counter-pressure support (14).Type: ApplicationFiled: September 27, 2002Publication date: February 6, 2003Inventors: Hermann Schmid, Wolfgang Ramin, Nusret Yilmaz, Heinrich Brenninger
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Publication number: 20030025214Abstract: Sealing resin comprising a resin component and filler mixed in the resin component, the filler having grain size distribution with a plurality of grain size peaks. The complex internal structure can be filled with the sealing resin including the filler particles with the plurality of the filler distribution peaks.Type: ApplicationFiled: August 1, 2002Publication date: February 6, 2003Inventor: Tsumoru Takado
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Publication number: 20030025215Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Applicant: ChipPAC, Inc.Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
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Publication number: 20030025216Abstract: In a phase shift mask blank comprising a transparent substrate and a phase shift film thereon, after the phase shift film is formed on the substrate, it is surface treated with ozone water having an ozone concentration of at least 1 ppm. The resulting phase shift film is of quality in that it experiences minimized changes of phase difference and transmittance upon immersion in chemical liquid during subsequent mask cleaning step or the like.Type: ApplicationFiled: August 6, 2002Publication date: February 6, 2003Inventors: Yukio Inazuki, Masayuki Nakatsu, Tsuneo Numanami, Atsushi Tajika, Hideo Kaneko, Satoshi Okazaki
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Publication number: 20030025217Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.Type: ApplicationFiled: September 24, 2002Publication date: February 6, 2003Inventor: Jun-eui Song
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Publication number: 20030025218Abstract: A choke valve device in a carburetor including an opening spring for biasing a choke valve in a fully opening direction, a negative pressure operating chamber provided in a carburetor body to communicate with an intake passage at a location downstream from the choke valve, a locking piston which has a pressure-receiving face facing the negative pressure operating chamber and which is adapted to be advanced and retracted between a locked position L and a unlocked position U, a locking spring for biasing the locking piston toward the locked position L, and a locking recess which is provided in a choke lever secured to a valve stem so that the locking recess engages with the locking piston advanced to the locked position L when the choke lever is moved to a fully closed position C of the choke valve.Type: ApplicationFiled: July 25, 2002Publication date: February 6, 2003Applicant: Honda Giken Kogyo Kabushiki KaishaInventor: Takashi Suzuki
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Publication number: 20030025219Abstract: Water vapor is introduced into an inlet air stream (16) of an engine (12), for example, by a pervaporation process through a non-porous hydrophilic membrane (18). A water reservoir (20), which can contain contaminated water, provides a vapor pressure gradient across the hydrophilic membrane (18) into the inlet air stream (16), while the rate of delivery of the water vapor to a cylinder (38-40) is self-regulated by the rate of flow of air across the membrane. The hydrophilic membrane (18) therefore also filters the water from the water reservoir (20) to an extent that pure water vapor is provided to the air inlet stream (16). Delivery of water vapor can nevertheless be controlled using a hood (26) that slides over the hydrophilic membrane to limit its exposed surface area.Type: ApplicationFiled: September 24, 2002Publication date: February 6, 2003Inventors: Mark Christopher Tonkin, Mark Andrew Young, Mark Elden Schuchardt
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Publication number: 20030025220Abstract: A method of facilitating replacement of a supply of air freshener every time a supply of soap is replaced, including the steps of providing a supply of air freshener, providing a supply of soap and joining the supply of soap and the supply of air freshener. Another aspect of the invention is a method of packaging a supply unit including providing a supply of soap and a supply of air freshener and connecting the supply of soap and the supply of air freshener in a manner such that when the supply of soap is removed from a dispenser, the supply of air freshener is removed from the dispenser as well. Another aspect is a supply unit for the dual dispenser including a receptacle, a supply of soap within the receptacle, and a supply of air freshener connected to or secured within the receptacle.Type: ApplicationFiled: September 24, 2002Publication date: February 6, 2003Inventors: Douglas S. Brown, David F. Scherger, George C. Heilman, Robert B. Brown
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Publication number: 20030025221Abstract: A diffuser for use in a pressurized feed system. The diffuser introduces a carbonic acid solution into water to be treated. The carbonic acid solution within the diffuser is maintained at an elevated pressure. As the carbonic acid solution passes to the exterior of the diffuser, the pressure drop causes an effective mixing of the carbonic acid solution and the water. The carbonic acid solution mixes with the water and the pH of the water is reduced.Type: ApplicationFiled: October 11, 2002Publication date: February 6, 2003Inventor: Tommy J. Shane
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Publication number: 20030025222Abstract: The invention relates to a process for the manufacture of a molding comprising the steps ofType: ApplicationFiled: March 6, 2002Publication date: February 6, 2003Inventors: Harald Bothe, Achim Muller, Bernhard Seiferling
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Publication number: 20030025223Abstract: The object of this invention is to provide a mold releasing method for a diffraction optical element, which enables stable mass production of a diffraction optical element free from deformation or damage due to mold release. In order to achieve this object, a mold releasing method for a diffraction optical element, of releasing from a mold a diffraction optical element formed by using the mold and having a convex lens function, includes the steps of pressing a central portion of the diffraction optical element toward the mold, and pushing a periphery of the diffraction optical element in a direction to separate from the mold, so that mold release progresses from the periphery toward the central portion of the diffraction optical element. The method also includes the step of adjusting the balance with a plurality of hydraulic cylinders without pressing the central portion, so that mold release progresses toward the center.Type: ApplicationFiled: July 2, 2002Publication date: February 6, 2003Applicant: Canon Kabushiki KaishaInventor: Masaaki Nakabayashi
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Publication number: 20030025224Abstract: The present invention provides a method of forming a lenticular sheet for use in forming a substantially ghost-free lenticular image. In a preferred embodiment, the method according to the invention includes providing a means for forming a lenticular sheet and forming the lenticular sheet out of a polymeric material using the means such that the lenticular sheet has an actual thickness (da) that is within about ±15% of an optimal thickness (do) as determined according to the formula: do=(ns−1)r/s(n−1), wherein n is the refractive index of the polymeric material, s is the number of interlaced scenes in the lenticular image, and r is the radius of the lenticles formed using the means.Type: ApplicationFiled: June 13, 2001Publication date: February 6, 2003Inventor: Anna Catherine Andrews
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Publication number: 20030025225Abstract: A molding die having satisfactory releasability, a sol-gel composition produced using the molding die, and a process for producing a sol-gel composition. The molding die which is to be pressed against a sol-gel material for producing a sol-gel composition has a release film, e.g., a thin gold (Au) film, formed on the molding surface of the molding die through a buffer layer made of metals and/or inorganic oxides.Type: ApplicationFiled: April 24, 2000Publication date: February 6, 2003Inventors: Katsuhide Shimmo, Kenichi Nakama, Isao Muraguchi
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Publication number: 20030025226Abstract: Method comprises:Type: ApplicationFiled: April 30, 2001Publication date: February 6, 2003Inventors: Hao Wen Chiu, Hsinjin Edwin Yang
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Publication number: 20030025227Abstract: A relief master is formed by assembly of previously molded, machined, or otherwise fabricated relief structures. The relief structures may be quite small and include a relief geometry, i.e., a topology of interest, and a positioning feature. The relief structures are mounted on a rigid (e.g., metal) substrate that includes a plurality of positioning features complementary to the positioning features in the relief structures. The relief master is assembled through selective application and positioning of the small-scale relief structures, and can then be used as a pattern for diverse surface replication processes, including the fabrication of durable metal mold faces for casting, embossing, compression molding, and injection molding of complex patterned surfaces.Type: ApplicationFiled: July 30, 2002Publication date: February 6, 2003Applicant: Zograph, LLCInventor: Stephen Daniell