Patents Issued in February 6, 2003
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Publication number: 20030026128Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventors: Oron Michael, Ilan Sever
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Publication number: 20030026129Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identifies the addressed column of memory cells as being defective.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Applicant: STMicroelectronics, Inc.Inventors: Stella Matarrese, Luca Giovanni Fasoli
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Publication number: 20030026130Abstract: A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventor: Luca Giovanni Fasoli
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Publication number: 20030026131Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventors: Stella Matarrese, Luca Giovanni Fasoli
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Publication number: 20030026132Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventors: Chun Chen, Kirk D. Prall
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Publication number: 20030026133Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventors: Oron Michael, Ilan Sever
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Publication number: 20030026134Abstract: A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventor: Tyler A. Lowrey
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Publication number: 20030026135Abstract: A data-shifting scheme is implemented where a group of arrays may be selected from a larger set of arrays. The arrays are connected to output-buffers and input-buffers such that data from the selected arrays may be read or written without changing addresses. The arrays are selected by programming the control signals controlling the output-buffers and input-buffers. The control signals may be programmed by several methods, for example, by blowing fuses or storing data in registers. The fuses do not have to be on pitch with the arrays. DRAMs, SRAMs, register arrays, and PLAs are examples of arrays that may be used with this invention. This invention is particularly useful for adding redundancy to an integrated circuit.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Inventors: J. Michael Hill, Donald R. Weiss, Jonathan E. Lachman
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Publication number: 20030026136Abstract: A semiconductor memory device is provided which can apply a redundancy circuit replacement program to cells by a DS testing in a parallel testing state. That is, in this semiconductor memory device, when the redundancy circuit replacement is effected on an electrically programmable nonvolatile memory device, an internal circuit is so provided as to detect a defect chip retrievable on a DS tester while being in a parallel testing state as well as address information contained in the defect chip and, by doing so, it is possible to achieve the redundancy circuit replacement.Type: ApplicationFiled: July 19, 2002Publication date: February 6, 2003Applicant: Kabushiki Kaisha ToshibaInventor: Hiroshi Maejima
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Publication number: 20030026137Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.Type: ApplicationFiled: August 6, 2001Publication date: February 6, 2003Inventors: Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
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Publication number: 20030026138Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.Type: ApplicationFiled: May 24, 2002Publication date: February 6, 2003Applicant: Samsung Electronics, Co., Ltd.Inventors: Chan-Yong Lee, Jung-Bae Lee
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Publication number: 20030026139Abstract: A semiconductor module includes a plurality of semiconductor memory devices, a registered buffer, a PLL circuit and a test mode entry circuit. The test mode entry circuit receives a signal MRS, a bank address signal and an address signal from the registered buffer, directly and externally receives a signal formed of a high voltage level higher than the voltage level in a normal operating range, generates a deactivating signal for deactivating the PLL circuit and a test mode shift signal formed of the high voltage level, applying the deactivating signal to the PLL circuit, and applying the test mode shift signal to the plurality of semiconductor memory devices. Consequently, the plurality of semiconductor memory devices included in the module can be shifted to the test mode in the modular state.Type: ApplicationFiled: April 12, 2002Publication date: February 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shunsuke Endou, Takayuki Miyamoto, Jun Nakai
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Publication number: 20030026140Abstract: A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.Type: ApplicationFiled: July 12, 2002Publication date: February 6, 2003Inventor: Greg A. Blodgett
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Publication number: 20030026141Abstract: A memory circuit includes a plurality of memory cells, an input/output area for addressing or writing onto the plurality of memory cells by means of electrical signals, and an optical-electrical converter for converting optical signals into the electrical signals, the plurality of memory cells and the input/output area being integrated on a chip, and the optical-electrical converter being mechanically connected to the chip or being integrated into the chip.Type: ApplicationFiled: July 31, 2002Publication date: February 6, 2003Inventors: Eric Cordes, Georg-Erhard Eggers, Christian Stocken
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Publication number: 20030026142Abstract: In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j+1 to MCij+1 and one word line of substitution information storing memory cells MCRA0 to MCRAj+1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS0 to CSj so as to selectively connect the columns other than a defective column to an input/output line.Type: ApplicationFiled: August 5, 2002Publication date: February 6, 2003Applicant: NEC CORPORATIONInventor: Junichi Yamada
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Publication number: 20030026143Abstract: A method for automatically assembling a data store 5 implementation from an abstract data model and automatically assembling data-sets indicating which parts of the data store 5 are required for each purpose (including data entry and reporting) and automatically generating data store 5 specific code for each such purpose optimized to minimize server loading and network traffic.Type: ApplicationFiled: August 5, 2002Publication date: February 6, 2003Inventor: Declan M. Brennan
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Publication number: 20030026144Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages.Type: ApplicationFiled: September 26, 2002Publication date: February 6, 2003Inventor: Yeong-Taek Lee
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Publication number: 20030026145Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages.Type: ApplicationFiled: September 26, 2002Publication date: February 6, 2003Inventor: Yeong-Taek Lee
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Publication number: 20030026146Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.Type: ApplicationFiled: October 1, 2002Publication date: February 6, 2003Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
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Publication number: 20030026147Abstract: A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.Type: ApplicationFiled: February 13, 2002Publication date: February 6, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Kyeong-Seon Shin, Sang-Seok Kang, Hyen-Wook Ju, Jeong-Ho Bang, Ho-Jeong Choi
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Publication number: 20030026148Abstract: In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.Type: ApplicationFiled: September 30, 2002Publication date: February 6, 2003Inventors: Lawrence T. Clark, Jay B. Miller
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Publication number: 20030026149Abstract: A dynamic random access memory includes first and second address generators, subarrays, an address decode path and a precharge activation path, wherein the precharge activation path and the address decode path are matched. The first address generator identifies a word and a column address. The second address generator identifies a subarray address. The subarrays include a number of cells for storing data. The address decode is configured to transmit address and other information while the precharge activation path is configured to transmit a precharge activation signal. In a preferred embodiment, an event during an active phase process, such as a sense amplifier set signal initiation, initiates the precharge phase process.Type: ApplicationFiled: August 1, 2001Publication date: February 6, 2003Applicant: International Business Machines CorporationInventors: George M. Braceras, Harold Pilo
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Publication number: 20030026150Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.Type: ApplicationFiled: September 24, 2002Publication date: February 6, 2003Applicant: STMicroelectronics S.r.I.Inventor: Danilo Rimondi
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Publication number: 20030026151Abstract: Latches for amplifying data on bit lines are activated in response to the activation of first activating signals. Amplifying transistors to be operated in read operations and switching transistors to be operated in write operations receive the activation of second activating signals at their sources and are activated per sense amplifier array. Since the numbers of amplifying transistors and switching transistors to be operated decrease, power consumption during operation period is reduced. Besides, since the wiring lengths of second activating signal lines can be made small compared to conventional art, driving capacity of second sense amplifier control circuits can be reduced. As a result, power consumption of the sense amplifiers can be reduced significantly in read operations. By having smaller loads in the second activating signal lines, transmission time of the second activating signals can be shortened, and thus read operation time and write operation time can be reduced.Type: ApplicationFiled: March 1, 2002Publication date: February 6, 2003Applicant: FUJITSU LIMITEDInventor: Naoharu Shinozaki
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Publication number: 20030026152Abstract: A plurality of sense amplifiers amplify parallel read data from memory cells, respectively. At least one of read amplifiers for amplifying the amplified read data respectively has a higher drivability than those of the rest of the read amplifiers. A connection switching circuit connects the sense amplifiers to a predetermined read amplifier according to an address. Switching the read data to one another before the amplification by the read amplifiers allows read data to be first outputted in burst read operation to be amplified by the read amplifier whose drivability is always high. In the burst read operation, a data output circuit first outputs read data corresponding to the read amplifier whose drivability is high. This enables reductions in read operation time and power consumption, even in a semiconductor memory in which the output orders of read data are changeable according to addresses or operation modes.Type: ApplicationFiled: March 25, 2002Publication date: February 6, 2003Applicant: FUJITSU LIMITEDInventor: Naoharu Shinozaki
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Publication number: 20030026153Abstract: A DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry is disclosed. The body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i.e., during an access operation, but the threshold voltage Vt of the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage Vt will increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are separated.Type: ApplicationFiled: September 30, 2002Publication date: February 6, 2003Inventor: Greg A. Blodgett
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Publication number: 20030026154Abstract: A reference voltage generating circuit of a non-volatile ferroelectric memory device includes a temperature compensating control circuit that increases and outputs a level of a signal to a reference capacitor node according to an increase in temperature when a reference control signal is at a high level, a plurality of ferroelectric capacitors connected in parallel, each of first electrodes of the plurality of ferroelectric capacitors are commonly connected to a ground voltage terminal and each of second electrodes of the plurality of ferroelectric capacitors are commonly connected to the reference capacitor node, and a plurality of switching blocks controlled by a reference wordline signal, each having drain terminals commonly connected to the reference capacitor node, source terminals connected to a corresponding bitline.Type: ApplicationFiled: July 30, 2002Publication date: February 6, 2003Applicant: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Hun Woo Kye, Duck Ju Kim, Je Hoon Park
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Publication number: 20030026155Abstract: In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.Type: ApplicationFiled: June 25, 2002Publication date: February 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Tadato Yamagata
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Publication number: 20030026156Abstract: A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.Type: ApplicationFiled: October 9, 2002Publication date: February 6, 2003Applicant: Hitachi, Ltd.Inventors: Takao Watanabe, Hiroyuki Mizuno, Satoru Akiyama
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Publication number: 20030026157Abstract: A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic.Type: ApplicationFiled: July 30, 2001Publication date: February 6, 2003Inventors: N. Johan Knall, Igor Kouznetsov, Michael A. Vyvoda, James Cleeves
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Publication number: 20030026158Abstract: A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.Type: ApplicationFiled: December 20, 2001Publication date: February 6, 2003Applicant: Matrix Semiconductor, Inc.Inventors: N. Johan Knall, James M. Cleeves, Igor G. Kouznetsov, Michael A. Vyvoda
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Publication number: 20030026159Abstract: Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ “enable” latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.Type: ApplicationFiled: July 31, 2002Publication date: February 6, 2003Applicant: Infineon Technologies North America Corp.Inventors: Gerd Frankowsky, Barbara Vasquez
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Publication number: 20030026160Abstract: A semiconductor integrated circuit device comprises an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.Type: ApplicationFiled: October 8, 2002Publication date: February 6, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Tadayuki Taura, Hidetoshi Saito
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Publication number: 20030026161Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.Type: ApplicationFiled: March 27, 2002Publication date: February 6, 2003Applicant: FUJITSU LIMITEDInventors: Shusaku Yamaguchi, Toshiya Uchida, Yoshimasa Yagishita, Yoshihide Bando, Masahiro Yada, Masaki Okuda, Hiroyuki Kobayashi, Kota Hara, Shinya Fujioka, Waichiro Fujieda
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Publication number: 20030026162Abstract: In a memory system having a memory controller 20 and at least one DRAM 30, the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM 30, and generates an internal reception clock signal for a DQ signal on the basis of the continuous and alternate inversion signal and a base clock signal. Then, the memory controller 20 counts the number of the receiving internal clocks from the moment an OUT1 command is issued to the DRAM 30 until a high-level data signal is received as the DQ data signal from the DRAM 30, and retains the count result as the number of delay clocks. Thus, the memory controller 20 can receive read data (DQ signal) on the basis of the internal reception clock signal when time equivalent to the number of the delay clocks passes after the read command is issued.Type: ApplicationFiled: August 1, 2002Publication date: February 6, 2003Inventor: Yoshinori Matsui
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Publication number: 20030026163Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S•N•F.Type: ApplicationFiled: October 1, 2002Publication date: February 6, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Kenji Tsuchida, Hitoshi Kuyama
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Publication number: 20030026164Abstract: The Convenience Nectar Mixing and Storage Device consists of a container that is divided proportionately to allow for the precise measuring of the recommended sugar to water ratios used for nectar type bird and butterfly feeders. The device is adapted for supporting a removable divider that separates the container into proportionate volumes, 4 to 1, 6 to 1, and 9 to 1 that correspond to the commonly recommended sugar to water ratios for hummingbird, oriole, and butterfly nectar feeders. The device allows for the water and sugar compartments to be filled to the same “line of sight” level to facilitate the making of precise nectar sugar to water ratios. Once the sugar and water compartments are filled to the same level, the divider is removed to allow for mixing. In the preferred embodiment of the Convenience Nectar Mixing and Storage Devices, the container divider can be used as a stirring implement and lid to cover the container during storage.Type: ApplicationFiled: July 24, 2002Publication date: February 6, 2003Inventor: Arnold Gregory Klein
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Publication number: 20030026165Abstract: An apparatus for mixing and diluting a concentrated liquid lubricant and a dilution material to form a diluted lubricant solution and more particularly a mass balance proportioner for weighing and mixing a concentrated lubricant and a dilution material to form a diluted lubricant having a predetermined dilution ratio based upon weight of concentrated lubricant to weight of dilution material.Type: ApplicationFiled: August 4, 2001Publication date: February 6, 2003Applicant: Dylon Industries Inc.Inventors: James W. Himmelright, Joseph D. Rose
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Publication number: 20030026166Abstract: An acoustic system and method for monitoring a hydrocarbon reservoir. Wellbore tube wave energy may be created by natural or ambient sources or tube waves may be excited intentionally. Wellbore tube wave energy is converted to seismic body wave energy at minor borehole obstructions or irregularities. Each obstruction or discontinuity position along the borehole has an associated unique waveform source coda that may be measured for processing the body waves radiated into the earth formation surrounding the well bore. A plurality of sensors detects the radiated seismic energy after the seismic body wave energy has transited intervening earth formations. The system may be employed for permanent monitoring of mineral resources and resource management. Measurements of reservoir characteristics may be acquired at many different times over the productive life of a reservoir.Type: ApplicationFiled: August 6, 2002Publication date: February 6, 2003Applicant: Baker Hughes IncorporatedInventor: Peter S. Aronstam
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Publication number: 20030026167Abstract: A system is presented for detecting downhole generated telemetry pressure pulses in a well. The system employs high sensitivity dynamic pressure sensors such as hydrophones for detecting the pulses in either the surface drilling fluid supply line or in the fluid return annulus. The high sensitivity allows detection of smaller surface pulses than standard transducers. In one embodiment, an annular pulser is used to generate pulses directly in the annulus.Type: ApplicationFiled: July 23, 2002Publication date: February 6, 2003Applicant: Baker Hughes IncorporatedInventors: Detlef Hahn, Volker Peters, Cedric Rouatbi
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Publication number: 20030026168Abstract: A seismic data acquisition system includes a connector housing and a mating electrical circuitry module. A single interface couples electrical circuitry housed in the electrical circuitry module to one or more signal data carriers that are consolidated at a single location in the connector housing. Preferably, the connector housing and electrical circuitry module each have a substantially contaminant-free interior regardless of whether these two parts are mated. An alternate connector housing has two plug casings, each of which are provided with a plug. A complementary alternate electrical circuitry module includes two receptacles complementary to the plugs and an interior space for holding the electrical circuitry. A locking pin disposed within the plug casing selectively engages the electrical circuitry module.Type: ApplicationFiled: July 16, 2002Publication date: February 6, 2003Applicant: Input/Output, Inc.Inventors: Lawrence P. Behn, John Chester, Leo Dekkers, John Downey, Keith Elder, Jerry Iseli
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Publication number: 20030026169Abstract: The invention describes a method and apparatus for effectively communicating data along the acoustic channel of a subterranean well. The method comprises optimally driving an acoustic transmitter with an adaptive transmitter controller. A data signal is transmitted along the acoustic channel and detected as a distorted signal along the acoustic channel. The distorted signal is input to the adaptive transmitter controller which, based on the detected signal, modifies later transmissions to counteract the distorting effects of the transmitter and acoustic channel. The adaptive transmitter controller preferably comprises a neural network. Another receiver may be employed, at a point further from the transmitter, to receive the optimized signals.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventor: Roger L. Schultz
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Publication number: 20030026170Abstract: There is disclosed herein a limb-mounted device that is controlled by one or more inputs disposed within reach of the fingers of a user on the same hand that is associated with the limb. The inputs may be disposed upon a retractable or removable surface so that they have an operative position, in which they are within reach of the fingers, and an inoperative position, in which they are stowed outside reach of the fingers, but in a manner otherwise convenient to the user.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Inventor: Jong H. Yang
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Publication number: 20030026171Abstract: An electrophorectic display is used in a watch, allowing for a dynamic range of new shapes and environments of use. The present invention addresses many of the shortcomings of the prior art watch technology. Specifically, a watch that embodies the present invention is uses addressable reflective display technology such as electronic ink or gyricons. This allows a watch display that features some flexibility. Further, the display can be shaped into a variety of interesting and novel designs that cannot be accomplished using prior art displays. The flexibility of the display also allows for the novel placement of the watch display. For example, the display can be placed onto a shoe, allowing a runner to see the time without having to move his arm into a viewing position. The watch display could also be placed into a wallet, or on a purse or belt. Any flexible garment or accessory could now incorporate a watch.Type: ApplicationFiled: August 1, 2001Publication date: February 6, 2003Inventors: Donald R. Brewer, Chan Chin Pang John, Jeffrey Keith Bruneau
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Publication number: 20030026172Abstract: An apparatus and method for keeping time in a multi-player game is disclosed. The method involves presetting the time remaining for each player, and continuously decrementing a player's timer while the internal clock is associated with that player. A means is provided to end one player's turn and simultaneously begin the next player's turn; thereby changing the association of the internal clock. The list of players is kept ordered as a ring, so that when the last player's turn ends, the first player's turn begins.Type: ApplicationFiled: August 6, 2001Publication date: February 6, 2003Inventor: Charles David Eagle
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Publication number: 20030026173Abstract: A method of reading out data from a domain expansion data storage such as a MAMMOS magneto-optic disk (1) which includes a data storage layer in which data is stored in the form of magnetic marks, and an expansion layer capable of copying and expanding domains from the storage layer, the system applying a first radiation beam (7), having a first spot size on the disk, in order to initiate copying of a domain from the storage layer to the expansion layer, and applying a second radiation beam (9), having a second spot size larger than the first spot size on the disk, in order to read out data from the expansion layer.Type: ApplicationFiled: July 30, 2002Publication date: February 6, 2003Inventor: Coen Adrianus Verschuren
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Publication number: 20030026174Abstract: A magnetic head includes a dielectric member, a coil and a heat conductor. The dielectric member has an obverse surface held in facing relation to a data storage disk. The coil generates a required magnetic field. The coil is provided in the dielectric member or in the obverse surface of the dielectric member. The heat conductor absorbs heat generated by the coil. The heat conductor has a heat conductivity which is higher than that of the dielectric member. The heat conductor has a surface which is at least partially irregular.Type: ApplicationFiled: February 14, 2002Publication date: February 6, 2003Applicant: FUJITSU LIMITEDInventors: Hiroyasu Yoshikawa, Goro Kawasaki, Tsuyoshi Matsumoto, Tohru Fujimaki
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Publication number: 20030026175Abstract: An optical disk device for writing data onto an optical disk having an undulating track comprises an optical pickup for illuminating laser light of a writing power and laser light of a replaying power onto an optical disk and for converting return light from the optical disk into an electrical signal, a filter for extracting a wobble component contained in the return light signal when the laser of a writing power is illuminated, a processor for detecting the direction of track deviation based on the phase of the wobble component, and an actuator for driving the optical pickup in the width direction of the track based on the direction of the track deviation in order to control the tracking. Because the phase of the wobble component differs for a case when a light spot is deviated radially inward and for a case when a light spot is deviated radially outward, the direction of the track deviation can be detected based on the phase of the wobble component and the tracking can be controlled during data writing.Type: ApplicationFiled: July 31, 2002Publication date: February 6, 2003Applicant: TEAC CorporationInventors: Yoshiyuki Otsuka, Mitsumasa Kubo
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Publication number: 20030026176Abstract: An image-recording device for generating image spots (210) by n individually controllable light sources (12), which each have a distance si, i being=1 . . . n, to an object line (14), in a projection line (16) of the object line (14) on a printing form (28), which moves with a velocity component v normally to the direction defined by the projection line (16) and tangentially to the surface of the printing form. The image-recording device is distinguished by the triggering device (216) having an assigned time-delay device (222), which delays the tripping instant of the triggering device for each light source (12) as a function of the particular distance si. The image-recording device may advantageously by used in direct imaging print units or printing-form exposure units.Type: ApplicationFiled: May 15, 2002Publication date: February 6, 2003Applicant: Heidelberger Druckmaschinen AGInventors: Uwe Albrecht, Bernard Beier, Uwe Ernst, Peter Goos, Andreas Rupprecht, Bernd Vosseler
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Publication number: 20030026177Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.Type: ApplicationFiled: May 14, 2002Publication date: February 6, 2003Inventors: Wen-Yi Wu, Jin-Chuan Hsu, Bruce Hsu