Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A pinned photodiode is operated without a transfer gate. This is done by forming a pinned photodiode which has a selective connection to the substrate. When the connection is turned on, the photodiode is pinned to the substrate, and kept at a specified potential. When the connection is off, the photodiode is disconnected from the substrate and hence floats. In this way, the area above the photoreceptor can be used both for a reception area and for a charge transfer area.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. A semiconductor structure formed in accordance with this method includes a monocrystalline silicon substrate, a metal oxide semiconductor portion formed in the monocrystalline silicon substrate, and a compound semiconductor portion formed in the layer of monocrystalline compound semiconductor material.

Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies, and capacitor structures.

Abstract: A structure of a non-volatile memory including a substrate with a vertical ladder channel profile (VLCP), a stacked gate structure on the substrate, and a source/drain region in the substrate beside the stacked gate structure. The vertical ladder channel profile is a profile of the dopant concentration in a first doped region directly underneath the surface of the substrate and in a second doped directly underlying the first doped region, wherein the dopant concentration in the second doped region is larger than that in the first doped region.

Abstract: A method for producing a self-aligned split-gate EEPROM memory cell is provided. The memory cell has a cell size smaller than the traditional spilt-gate structure without sacrificing program disturb immunity. Moreover, the problem current of the memory cell is much lower than the stack-gate structure. The method includes steps of: providing a silicone substrate, forming a select gate on the silicone substrate, growing a tunnel oxide layer on exposed surfaces of the silicon substrate, forming a floating gate self-aligned to one side of the select gate, performing an ion implantation to form a source region and a drain region on the silicone substrate, and forming a control gate over the floating gate and the select gate, wherein the control gate, the floating gate and the select gate are insulated from one another.

Abstract: The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Abstract: The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract: A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: According to the semiconductor thin-film and semiconductor device manufacturing method of the present invention, an insulating film having a through-hole between two layers of silicon film is provided, the silicon film is partially melted by irradiating a laser thereon, and a substantially monocrystalline film is continuously formed extending via the through-hole from at least part of the layer of silicon film below the insulating film that continues to the through-hole, to at least part of the layer of silicon film above the insulating film. It is therefore sufficient to form a through-hole with a larger diameter than that of a hole formed by the conventional method, because the diameter of the through-hole in the insulating film may be the same size or slightly smaller than the size of a single crystal grain that comprises the polycrystal formed in the silicon film below the insulating film. Costly precision exposure devices and etching devices are therefore unnecessary.

Abstract: A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.

Abstract: A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: A semiconductor device in accordance with the present invention is equipped with a gate electrode 10 formed on a BOX layer 2, a gate oxide film 11 formed on the gate electrode, a body region 12a composed of epitaxial Si formed on the gate oxide film, diffusion layers 18 and 19 for source/drain regions formed on both sides of the body region, and a body terminal connected to the body region for applying a specified potential to the body region. As a result, the substrate floating effect is suppressed even in a transistor having a short gate length and a long gate width.

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array region in which a plurality of memory cells are arranged, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates. In reading out data from one of the first and second nonvolatile memory elements of the memory cell, a control voltage of a control-gate-line selection switching element connected to a sub control gate line to which an override voltage is applied, is greater than that of a control-gate-line selection switching element connected to a sub control gate line to which a read voltage is applied.

Abstract: A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film.

Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Abstract: A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.

Abstract: A method for sensing mechanical quantities such as force, stress, strain, pressure and acceleration is disclosed. This technology is based on a change in the electrochemically generated voltage (electromotive force) with application of force, stress, strain, pressure or acceleration. The change in the voltage is due to a change in the internal resistance of the electrochemical cell with a change in the relative position or orientation of the electrodes (anode and cathode) in the cell. The signal to be detected (e.g. force, stress, strain, pressure or acceleration) is applied to one of the electrodes to cause a change in the relative position or orientation between the electrodes. Various materials, solid, semisolid, gel, paste or liquid can be utilized as the electrolyte. The electrolyte must be an ion conductor. The examples of solid electrolytes include specific polymer conductors, polymer composites, ion conducting glasses and ceramics.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A micromachined capacitive electrical component such as a condenser microphone with a support structure and a rigid plate with an electrically conductive plate electrode secured to the support structure at discrete locations. A diaphragm of a substantially non-conductive material is secured to the support structure along its periphery at a predetermined distance from the substantially rigid plate, whereby the substantially rigid plate and the diaphragm define an air gap. The diaphragm is movable in response to sound pressure and carries an electrically conductive diaphragm electrode. The support structure and the diaphragm electrode are electrically interconnected so as to have substantially the same electrical potential. A layer of a substantially non-conductive material is disposed between the substantially rigid plate and the support structure at least at the discrete locations.

Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.77Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. A composite integrated circuit having a tunable laser is provided. The laser may be mode-locked. Injection-locking may be used to pass optical properties to a slave laser.

Abstract: A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate 11, and pads 13 stacked thereon via an insulation film 12. A particular pad 13a is connected to a signal wiring 17a formed in a bus line region 17, and a capacitor-forming conductor 14 behaving as an impedance adjusting conductor is formed to surround the pad 13a. A source line conductor 15 is made in a space between the pad 13a and the capacitor-forming conductor 14 to encircle the capacitor-forming conductor 14. Therefore, the pad capacitance can be increased by using the space around the pad 13a, other signal wirings 17b and any others formed in the bus line region 17 are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Abstract: There is described a method for controlling the sensitivity profile of a photodetector (1; 1a to 1d) comprising at least one well (10; 10a to 10d) of a first conductivity type (e.g. N) formed in a semiconductor substrate (20) of a second conductivity type (e.g. P), this method comprising the steps of determining a desired sensitivity profile for the photodetector, forming at least one diffusion region (15; 15a to 15d) of the first conductivity type in a determined region of the well and/or forming at least one diffusion region (25) of the second conductivity type in the semiconductor substrate adjacent to the well, and connecting said at least one diffusion region of the first or second conductivity type to a positive or negative potential of a reverse-bias voltage applied across said well and said semiconductor substrate.

Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction.

Abstract: A driver circuit substrate is prepared and a mirror substrate is so provided as to be placed on the driver circuit substrate. Nine mirror elements are lad out on the mirror substrate in a 3×3 matrix form. The mirror elements are prepared by a microelectromechanical system (MEMS). An insulating substrate is provided on the driver circuit substrate and a driver circuit which drives a light reflecting mirror element is provided on the insulating substrate. The driver circuit substrate is connected to the mirror substrate via a resin layer of a thermosetting adhesive or the like.

Abstract: A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: The present invention is to provide a kind of multilayer microstructure macrocapacitor, wherein on one side of an electrode substrate after it forms slots with an appropriate aspect ratio, sequentially forms a high dielectric layer and a conducting material layer to give a basic composition unit, laminates the conducting material layers of two groups of basic composition unit to form a monolayer microstructure macrocapacitor, and stacking laminates the plural groups of the monolayer microstructure macrocapacitor to obtain a multilayer microstructure macrocapacitor; on two sides of an electrode substrate it forms a basic composition unit of a microstructure macrocapacitor through the process described above, and laminates the plural groups of the monolayer microstructure macrocapacitor to obtain a multilayer microstructure macrocapacitor.

Abstract: Method and structure effective for reducing quiescent current drain using a semiconductor structure including a monocrystalline silicon substrate and a plurality of capacitors formed with a monocrystalline perovskite oxide material comprised of a high-k dielectric material, and a monocrystalline compound semiconductor layer including a plurality of logic elements having respective output gates, wherein the logic elements are coupled via their respective output gates to different ones of the capacitors, such that the logic elements use the oxide film as a capacitive storage element.

Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.

Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicone oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: A composite ceramic board comprising an insulating board of insulating layers of alumina ceramics and dielectric layers of ceramics having a dielectric constant smaller than at of said insulating layers which are fired as a unitary structure, and metallized wirings of a low-resistance conductor such as of Au, Ag, Cu or Pt formed on the surfaces and inside thereof, and a method of producing the same. The composite ceramic board not only has a large strength and a high thermal conductivity but also exhibits excellent high-frequency chararteristics and is suited for use as a high-frequency wiring board. The invention further provides an optical/electronic-mounted circuit substrate using the above board, and a mounted board having the circuit substrate of the invention connected to an electronic circuit formed on a mother board.