Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a CMOS latch.

Abstract: A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to an input electrode of a TFT (101), a non-inverting output signal is outputted from an output electrode of the TFT (101) and an inverting output signal is outputted from output electrodes of TFTs (102 and 103). Two line outputs of non-inversion and inversion are obtained. Thus, when a buffer located in a subsequent stage is operated, a period for which a direct current path is produced between a high potential and a low potential of a power source can be shortened, thereby contributing to reduction in a consumption current.

Abstract: The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be output from the output driver device, an input terminal for an input signal to be input into the output driver device, and a control device that is signal-connected to the output device and the input terminal and is designed to transform the input signal into two mutually different control signals and to output the control signals via control signal outputs to the output device, where the output device configured to generate the output signal in a manner dependent on the control signals.

Abstract: To improve a control circuit for at least one inductive load, comprising a first load branch, which lies between a first voltage terminal and a second voltage terminal and comprises an electronic switch and the inductive load connected in series, the electronic switch lying between a first terminal of the inductive load and the first voltage terminal, and a second terminal of the inductive load being in connection with the second voltage terminal, a freewheeling diode, via which a freewheeling current of the inductive load flows when the electronic switch is open, in such a way that smallest possible fluctuations of the supply current and smallest possible voltage peaks occur at the voltage terminals, it is proposed that there is provided a freewheeling branch which has, as a series connection, a capacitance connected to the first voltage terminal and an inductance connected to the second terminal of the inductive load, and also a freewheeling diode lying between a center tap between the capacitance and the i

Abstract: The output (&thgr;2) of a digital adder (13) before being held by a first data holding circuit (14), a first reference value (D1) and a second reference value (D2) are compared, respectively, by a first data comparator (15) and a second data comparator (16), to thereby change one cycle of the output control of the pulse train fout from four cycles (T1-T4) to two cycles (T1-T2) of the reference clock. Further, by comparing the output (&thgr;1) of the first data holding circuit (14) and the first reference value (D1) by a third data comparator (19), the latch timing of the overflow signal is changed from T4 to T1.

Abstract: A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.

Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

Abstract: The present invention relates to a differential charge pump, in particular for use in a tuning system including a phase-locked loop, for generating currents, comprising a first input (IN+) and an inverse second input (IN−), in particular for receiving differential signals from a phase comparator, first current source means (Q1) for generating a first current (kIo) in accordance with the signal inputted into said first input (IN+), second current source means (Q2) for generating an inverse second current (kIo) in accordance with the signal inputted into said second input (IN−); and a first output (OUT+) and a second output (OUT−) for outputting said first and second currents, respectively.

Abstract: A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions.

Abstract: A significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, a phase detector circuit comprises: a first compare block coupled to receive a first clock signal and a second clock signal, and configured to generate a first output signal representing a lead or lag condition; a delay cell having an input and an output, the input coupled to receive the second clock signal; a second compare block coupled to receive the first clock signal and the output of the delay cell, and configured to generate a second output signal representing a lead or lag condition; and a logic block coupled to receive the first output signal and the second output signal, and configured to generate a phase detect output signal indicating a lock condition or an out-of-phase condition.

Abstract: An apparatus for reducing a magnitude of a rate of current change of an integrated circuit is provided. The method uses a counter stage controlled by a control stage to sequentially disable a plurality of transistors that are used to source current from a power supply. By sequentially disabling the plurality of transistors, a reduction of an amount of current occurs gradually, effectively reducing the magnitude of the rate of current change.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: Each of a plurality of clock generation units has a clock driver which generates a clock signal in accordance with a reference clock, and a supplying unit which supplies the reference clock to the clock driver. The supplying unit supplies the clock driver, in a case where another clock generation unit is already attached to a clock signal generation device at a time the clock generation unit to which the supplying unit belongs is attached to the clock signal generation device, with a clock signal generated by the clock driver of the another clock generation unit as the reference clock during a predetermined time. The clock driver makes a clock signal to be generated follow the supplied reference clock.

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

Abstract: Digital CMOS integrated circuit (120) comprising an analog signal processing circuitry with a series of two or more field-effect transistors (FETs). The FETs have a maximum allowed supply voltage value (Vmax). The digital CMOS integrated circuit (120) further comprises a local charge pump (135) for generating an elevated supply voltage (Vsupplydiff) larger than the maximum allowed supply voltage value (Vmax). The local charge pump (135) is arranged such that this elevated supply voltage (Vsupplydiff) is applied to the series of two or more of the field-effect transistors (FETs).

Abstract: For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second operational current, which is smaller than the first operational current, a first power source regulator for stepping down a predefined output power supply voltage from an input power supply voltage and having a current supply ability corresponding to the first operational current of the internal circuit and a second power source gulator having a current supply ability corresponding to the second operational current are combined in order to, under the control of a power supply control unit, operate the first step-down type regulator in response to a first control signal instructing the first operation mode in the internal circuit and to operate the second step-down type regulator in response to a second control signal instructing the second operation mode.

Abstract: A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage shifting a data value to the right and at least one other multiplexor stage shifting to the right. Left and right shifts may thus be obtained by using a single set of multiplexor stages. As a result, time delays and area consumed may be reduced when the upper/lower end of a desired shift value range does not equal 2Q−1, wherein Q equals an integer.

Abstract: An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

Abstract: A charge pump is disclosed with a circuit to prevent pass device latch-up. The charge pump includes at least one charge storage device and a pre-charge circuit to charge the at least one charge storage device to a charge level to provide a predetermined output voltage from the charge pump. A pass device is coupled between the charge storage device and an output of the charge pump, and a circuit is coupled to the pass device to prevent a latch-up condition.

Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

Abstract: A voltage generation circuit comprises a capacitor, an n-channel MOS transistor, a p-channel MOS transistor and the like, while the n-channel transistor has a source terminal connected to a node and a drain terminal employed as an output terminal for a negative voltage, the p-channel MOS transistor has a source terminal connected to the aforementioned node and a drain terminal employed as a ground terminal, gate terminals of the n-channel MOS transistor and the p-channel MOS transistor are connected in common, and clock signals inverted in phase to each other are applied to the common node and a first terminal of the capacitor.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: In one aspect, a method for a sleep mode in a dynamic circuit includes driving a dynamic node to an operating voltage state during a precharge interval by precharge timing circuitry coupled to the dynamic node and a voltage source responsive to a precharge signal. The dynamic node is selectively pulled to a low voltage state during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The dynamic node voltage is inverted by output circuitry coupled to the dynamic node and to an output node. The output node is isolated from ground during a sleep interval responsive to a sleep signal by sleep circuitry coupled to the output circuitry.

Abstract: This invention seeks to provide an active filter circuit capable of reducing power consumption without limiting dynamic range, for example. A switch section and a capacitance element are disposed between an active filter section and a charge pump section. ON/OFF switching (short/open) of the switch section is controlled by a cut-off frequency judging section according to a status of adjusting cut-off frequency of the active filter section. When the switch section is under the OFF status, the capacitance element maintains a voltage to be supplied to a gate terminal and each circuit operation of a frequency adjusting section is stopped, thus reducing power consumption.

Abstract: An improved method and design for adjusting clock skew in a wire trace comprising a corrugated pattern wire trace bracketed by a pair of parallel conducting wire frames with wire extensions projecting between the corrugations of the wire trace. The wire frames are connected to a voltage supply. The transmission properties of the wire trace, and thus the degree of clock skew associated with the wire trace, are affected by the number of wire extensions protruding between the corrugations, their degree of penetration, as well as other factors inherent in the design. The present design can achieve the same degree of clock skew with a smaller surface area covered and with fewer resistive losses than with prior art designs.

Abstract: An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

Abstract: An apparatus and method for operating an adaptive circuit includes injecting a set of orthogonal tracer signals into the circuit. The tracers signals are extracted after modification by at least a portion of the circuit and are examined by respective controllers to modify operation of the circuit. In one embodiment, the invention is incorporated into a feed forward amplifier where a set of orthogonal tracer signals are injected into the amplifier. A detector controller detects the orthogonal tracer signals, as modified by portions of the amplifier, and applies each tracer signal to a respective controller. Each controller examines its respective signal and modifies its output to control a portion of the amplifier accordingly. The controllers apply their outputs to the respective portions of the amplifier at substantially the same time, leading to quick convergence of the operating point of the amplifier to an optimal or near-optimal configuration.

Abstract: A system and method for improving the input return loss in RF amplifiers is disclosed. One embodiment of the present invention amplifies only one of the two output quadrature signals of 3 dB coupler in an amplifier module while substantially maintaining a constant impedance at the input to the 3 dB coupler. This removes one of the design constraints for designing the input network for an amplifier module thereby allowing for more flexible amplifier designs and ease of cascading amplifier modules. One embodiment of the present invention improves the input return loss of an RF amplifier pallet in a cascaded-stage power amplifier circuit for a television transmitter including a 3 dB coupler by replacing one of the two amplifiers connected to the output of the 3 dB coupler with an electrical circuit of substantially equivalent impedance to the input impedance of the non-replaced amplifier.

Abstract: A system of connecting errors in the control loop using multiple additional loops. A first loop carries out control in a desired way, and the additional loops are provided for the purpose of determining a specified error value. That specified error value may be, for example, a quiescent current. The specified error value is then used to correct for errors in the first loop.

Abstract: An RF wideband amplifier system is provided that includes an M way splitter for receiving an RF input signal and splitting same into M RF signals for respective application to M power amplifier modules PAM-1 to PAM-M that amplify the M signals and apply the amplified M signals to an M way combiner that applies an amplified RF signal to a load. A main controller provides an automatic level control reference signal, representative of the desired output power level of each of the power amplifier modules.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: The variable power supply to an amplifier in an electrical circuit is dynamically controlled through the use of a lookup table responsive to one or more operating conditions of the electrical circuit. The lookup table is indexed by one or more of the operating conditions and the amount of amplification to be applied to an input signal to the amplifier is determined. One embodiment of the invention comprises a television transmitter circuit including a power amplifier circuit capable of amplifying a variable frequency COFDM or 8VSB input signal where the amount of amplification applied to the input signal is dynamically controlled through the use of a lookup table as a function of the frequency of the input signal.

Abstract: A low-noise amplifier for radio frequency signals uses the magnitude of the input signal to adjust the output current of a current source if the input signal magnitude exceeds a predetermined value. The current source provides operating current to the low-noise amplifier. Compensation for gain reduction due to large input signal magnitude is therefore achieved by increasing the gain of the low noise amplifier in such situations by increased operating current. As a result, power consumption savings and better linearization are achieved, especially for such low-noise amplifiers used in mobile receivers.

Abstract: A variable gain amplifier is provided with a first differential amplifier circuit and a second differential amplifier circuit each formed with transistors. A common signal is inputted to each of the differential amplifier circuits, and output signals of the differential amplifier circuits are added together for output via resistances. When a voltage of a variable voltage source is increased, a bias current of the first differential amplifier circuit having a high gain is increased, and therefore the gain of the first differential amplifier circuit is raised, resulting in an increase in overall gain. When the voltage of the variable voltage source is decreased, a bias current of the second differential amplifier circuit having a low gain is increased and therefore the gain of the second differential amplifier circuit is raised, so that the second differential amplifier circuit has greater effect and thus provides an amplifier circuit with a high saturation input level.

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

Abstract: A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers. Inverting output ports of each of the first group of amplifiers are coupled to a module inverting output terminal, and non-inverting output ports are coupled to a module non-inverting output terminal. A divider network is provided and is coupled to the input ports of the first group of amplifiers. A second group of amplifiers is also provided. Each amplifier of the second group corresponds to one of the amplifiers in the first group, has an inverting input port coupled to the second module inverting input terminal and to output ports of the divider network, and a non-inverting input port coupled to the second non-inverting input terminal.

Abstract: A multichannel parallel IC amplifier includes a plurality of amplifier circuits formed on an IC substrate. Each amplifier circuit is coupled to respective inputs via a pair of capacitors. The capacitors are configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels, leading to cancellation of crosstalk signals.

Abstract: To provide an amplifier in which an amount of variation in output impedance between high- and low-gain modes is small and gain control can be accomplished accurately. A radio frequency signal inputted through an input terminal (1) is provided to a base of a transistor (102) and outputted to its collector. In a high-gain mode, a switch (110) is turned off to place a transistor (104) in an off sate. All radio frequency signals are inputted into an emitter of a transistor (103), outputted to its collector and then to an output terminal (2). In a low-gain mode, the switch (110) is turned on to place the transistor (104) in an on state so that a base voltage of the same value as that of the transistor (103) is applied to it. A current ratio between the transistor (103) and the base-grounded transistor (104) is determined by a size ratio between them. Therefore, a current can be accurately adjusted by adjusting the size ratio between them and outputted to the output terminal (2).

Abstract: A phase-locked loop fractional-N frequency synthesizer, particularly of a sigma delta type, has a voltage controlled oscillator, a fractional-N frequency divider, a phase comparator, a charge pump, and a loop filter. The loop filter has a capacitive element for receiving a charge pump current from the charge pump. A filtered charge pump current controls the voltage controlled oscillator. The charge pump is operable in three current modes, a pre-charging/pre-discharging mode, a speed up mode, and a normal, locked mode. In the pre-charging/pre-discharging mode the charge pump is decoupled from the phase comparator so that the phase locked loop is open, and in the speed up and normal modes the charge pump is coupled to the phase comparator so that the phase locked-loop is closed.

Abstract: The present invention relates to a charge pump, in particular for use in a tuning system including a phase-locked oop, for generating currents, comprising current amplifier means, wherein that said current amplifier means comprises a translinear circuit (Q13, Q11, Q9, Q1; Q14, Q12, Q10, Q2).

Abstract: An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.

Abstract: The present invention relates to a ring oscillator stage, comprising delay means (32) having an input and an output, and further comprising adjustable negative resistor means (−RTUNE) coupled to the output of said delay means (32).

Abstract: The present invention relates to a differential ring oscillator stage, comprising differential delay means (Q1, Q2) having a first input (IN+) and an inverse second input (IN−) and a first output and an inverse second output, a first output buffer means (34a) having its input connected to the first output of said delay means (Q1, Q2), and a second output buffer means (34b) having its input connected to the second output of said delay means (Q1, Q2), and further comprising a first controllable current source means (M6) which is connected to the output (OUT+) of said first output buffer means (34a) and controlled in accordance with the signal from said second output of said delay means (Q1, Q2), and a second controllable current source means (M5) which is connected to the output (OUT−) of said second output buffer means (34b) and controlled in accordance with the signal from said first output of said delay means (Q1, Q2), said controllable current source means (M5, M6) supplying currents t

Abstract: A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.

Abstract: An oscillation circuit is provided with a positive feedback oscillation loop constructed by an amplifier, a SAW resonator with a prescribed resonance frequency, a phase-shifting circuit which outputs the phase of an input signal as an output signal with a prescribed shift and a tank circuit composed of an inductance element and a capacitive element, and an NTC thermistor with negative temperature characteristics is connected in parallel to the tank circuit. Moreover, a capacitive element with a capacity-temperature characteristic for correcting the quadratic frequency-temperature characteristic of the SAW resonator is used in the oscillation circuit as the oscillation element of the tank circuit.

Abstract: A pulse width modulation integrated circuit (PWM IC) chip available as an 8-pin DIP or a 14-pin SOP package is characterized by simplified circuit complexity, high package density, more voltage regulation functions and more pin functions. The PWM IC of the present invention uses several internal control circuit to create and define the pin functions thereof and is capable of controlling the switch of the internal power control circuit therein, modulating the operation frequency of the PWM IC, accomplishing the voltage feedback operation of the power supply, sensing the external current and increasing the pulse width of the output pulse signal tardily as the PWM IC starts up. More specifically, because the PWM IC of the present invention employs internal current sources to create and define the pin functions thereof, the PWM IC can be equipped with less pin numbers, simpler circuit complexity and higher package density.

Abstract: In one aspect, the invention relates to a waveguide structure for differential transmission lines. The waveguide structure includes a first ground structure, a first signal line, a second ground structure, a second signal line, a third ground structure. The first signal line is typically positioned adjacent and substantially parallel to the first ground structure. The second ground structure has a first separation distance from the first ground structure and is typically positioned adjacent and substantially parallel to the first signal line. The first signal line is typically positioned between both the first and second ground structures. The second signal line typically has a second separation distance from the first signal line and is positioned adjacent and substantially parallel to the second ground structure. The second ground structure is typically positioned between both the first and second signal lines.