Abstract: A semiconductor device comprises: a semiconductor element; an external terminal used for an external connection; an interposer having the semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface thereof opposite to the first surface so as to electrically connect the semiconductor element and the external terminal; a resin sealing the semiconductor element on the first surface; and an interconnecting portion formed within the resin, the interconnecting portion having a first connecting part electrically connected to the external terminal and having a second connecting part exposed on an outer surface of the resin.

Abstract: Field-Effect Transistor Based on Embedded Cluster Structures and Process for Its Production In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball.

Abstract: An interconnect module and a method of manufacturing the same is described comprising: a substrate, an interconnect section formed on the substrate, and a variable passive device section formed on the substrate located laterally adjacent to the interconnect section. The interconnect section has at least two metal interconnect layers separated by a dielectric layer and the variable passive device has at least one moveable element. The moveable element is formed from a metal layer which is formed from the same material and at the same time as one of the two interconnect layers. The moveable element is formed on the dielectric layer and is released by local removal of the dielectric layer. Additional interconnect layers and intermediate dielectric layers may be added.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate and then patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the exposed surface of the device region. A conductive layer is formed on the gate dielectric layer and then patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Abstract: An electromagnetic stator comprises a printed circuit board. The stator also comprises at least one conductive coil formed on the printed circuit board for generating an electromagnetic field.

Abstract: Coil structures and isolators using them. A coil(s) is (are) used as a magnetic field-generating element(s) paired with another coil(s) or other magnetic field-receiving element(s). The coil(s) is(are) formed in or on a substrate which does not include some or all of the driver (i.e., input) or receiver (i.e., output) circuits. The coil(s) and magnetic field-receiving element(s) thus can be manufactured separately from the driver and/or receiver circuitry, using different processes, instead of subjecting the chip areas containing both input and output circuits to post processing to form the coil(s). Isolators can be assembled using such coils with a resultant lower cost. Isolators also can be assembled using transformers made from such coils wherein the transformers can be driven on either of their windings in order to provide bi-directional isolation with a single transformer.

Abstract: The invention relates to a transponder provided with an integrated circuit, an antenna, and a first capacitor provided with a dielectric and a first and a second capacitor electrode, which transponder comprises a stack of layers, i.e.

Abstract: An on-die termination resistor includes three transistors and a resistor. The resistor keeps at least one of the transistors from entering the saturation region and therefore improves the I-V characteristics of the termination resistor.

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract: This invention relates to an insulated gate bipolar transistor, a semiconductor device using such a transistor and manufacturing methods of these, and in particular, its object is to eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current.

Abstract: A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g.

Abstract: A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g.

Abstract: A crystalline silicon layer is epitaxially grown on a substrate having a porous silicon layer on the surface. In making epitaxial growth by liquid-phase epitaxy, a silicon material is previously dissolved in a melt at a high temperature and then the silicon substrate to be subjected to epitaxy is immersed in the melt. Then, its temperature is gradually lowered, whereby the silicon precipitated from the melt is epitaxially grown on the silicon substrate. In this epitaxy, a substrate having the principal plane of (111)-plane is used as the silicon substrate.

Abstract: A semiconductor structure and a method of determining an overlay error produced during formation of the semiconductor structure are disclosed. The semiconductor structure comprises a first two-dimensional periodic pattern and a second two-dimensional periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second two-dimensional periodic patterns indicates the magnitude and direction of an overlay error caused during the formation of the first and second two-dimensional periodic patterns. The semiconductor allows one to independently determine the overlay errors in linearly independent directions by directing a light beam of known optical properties onto the first and second two-dimensional periodic patterns and by analyzing the diffracted beam by comparison with reference data.

Abstract: Semiconductor devices and methods are disclosed which address resistance shift reliability problems. At least one conductive level is included which has first vias formed in an organic material. The first vias include first contacts formed therein having a first layout dimension. An organic dielectric layer is formed on the at least one conductive level including second vias. The second vias include second contacts formed therein having a second layout dimension greater than the first layout dimension. An inorganic dielectric layer is formed on the organic dielectric layer. The employing this structure resistance shift reliability is prevented.

Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.

Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract: A semiconductor chip is arranged on the main surface of an island portion as a substrate with a seal member interposed. Between the main surface of island portion and semiconductor chip, there exists a space kept airtight by seal member. Semiconductor chip is fixed on island portion by making negative the atmospheric pressure in this space relative to the atmospheric pressure outside a semiconductor package. A semiconductor device in which a semiconductor chip can be fixed on a lead frame without using a die bonding material, and a method of manufacturing the same are thus obtained.

Abstract: A routing element for use with a multi-chip module. The routing element includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a multi-chip module substrate. The conductive traces may be carried upon a single surface of the routing element substrate, internally by the routing element substrate, or include externally and internally carried portions. The routing element also includes a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multi-chip module. Multi-chip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Abstract: The objective of this invention is to provide a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a type of semiconductor device that makes use of said substrate for carrying a semiconductor chip. Constitution: The conductor pattern on insulating substrate 102 contains lands 130 that are respectively connected to electrode pads 120 of semiconductor chip 100 via conductor wires 110. Each land 130 of conductor pattern 110 as capillary tool contact portion 202 where the capillary tool makes contact during bonding, and wire contact portion 204 that allows contact of conductor wire 110. The portion of wire contact portion 204 on the side toward capillary tool contact portion 202 becomes constricted portion 200. Lands 130 are positioned such that constricted portion 200 and capillary tool contact portion 202 of adjacent lands 130 are arranged facing each other.

Abstract: The present invention provides a new IC packaging and its manufacturing methods. This technology simultaneously combines Flip Chip (FC), Ball Grid Array (BGA), and Chip on Chip (COC) packages to form a vertically stacked IC such that multiple semiconductor chips can be integrated into a single, small factor IC product. Each semiconductor chip as well as the substrate of the final IC product can be manufactured, tested, and assembled separately under its own optimal manufacturing conditions, thereby increasing yield, lowering manufacturing cost, and shortening processing time. Another advantage of this new technology is that the length of the interconnects between the semiconductor chips as well as between each semiconductor chip and the substrate is shorter than those of known IC packages. The reduction of the length of the rerouting lines enhances electrical performance because inductance of the signal path is greatly reduced.

Abstract: There is disclosed a TAB style BGA type semiconductor device. This semiconductor device comprises a semiconductor chip on which an integrated circuit is formed, and a polyimide tape which has a conductive pattern and which is allowed to adhere to the semiconductor chip. The conductive pattern includes a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to the outside electrode, and an electrically floating island-like portion in addition to a wiring portion for connecting the bonding portion and the pad portion.

Abstract: A stack chip module includes a substrate having a predetermined-size groove on one side and a circuit pattern, one end of the circuit pattern being adjacent to the groove; a first semiconductor chip adhered in the groove of the substrate by adhesive and having a plurality of center pads and a plurality of edge pads, electrically connected to each other, on the upper part thereof; a plurality of gold wires for electrically connecting the circuit pattern of the substrate and the edge pads of the first semiconductor chip, respectively; a second semiconductor chip having a plurality of center pads corresponding to those of the first semiconductor chip, the formative side being opposite to that of the first semiconductor chip; and a plurality of bumps interposed between the center pads of the first semiconductor chip and the center pads of the second semiconductor chip for joining and electrically connecting them.

Abstract: An electronic component has at least a first semiconductor chip module, a second semiconductor chip module, and a substrate to accommodate the semiconductor chip modules. In this case, active chip surfaces of the two semiconductor chip modules each have a central contact area, which are disposed to face each other. The individual solder contact areas formed on the central contact areas and corresponding with one another are opposite and aligned with one another and are electrically conductively connected.

Abstract: An electronic component is formed with at least two semiconductor chips disposed on a carrier substrate. Active chip surfaces of the semiconductor chips comprise central contact surfaces, respectively, on which opposing solder contact surfaces are formed. These are conductively connected to an intermediate carrier which is disposed between the semiconductor chips and which produces rewirings from the chips to the carrier substrate.

Abstract: In order to keep the mounting outlay for shielding measures as low as possible, a semiconductor device having a semiconductor component in a housing element is proposed. At least one capacitive element having a first electrode, a second electrode and a dielectric is provided in an integrated manner in the housing element or in the region thereof. The electrode regions of the capacitive element are electrically contact-connected to terminal regions of the semiconductor component, in such a way that high-frequency interference signals between terminal regions can be suppressed.

Abstract: A pad grid array semiconductor package (28) provides interconnect pads (30) of equal pad area and matrixed locations, placing an interconnect pad in a fixed location relative to an adjacent interconnect pad. Die pad (48) and interconnect pads (30) are formed from an etched, or otherwise formed, conductive lead frame. Die pad (48) is in full contact with semiconductor die (50), providing pad grid array interconnect pads (30) in electrically conductive contact to semiconductor die (50). Interconnect pad (58) is removed in an alternate configuration to provide spacial orientation of pad grid array package (56).

Abstract: It is intended to provide a configuration of a semiconductor package used for manufacturing a small high-quality semiconductor package with a flat lead and to provide a method of manufacturing a lead frame. The semiconductor package with a flat lead is formed to have a lead frame with its lead portion made thinner than its foot portion.

Abstract: A substrate assembly including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact with the lead elements of an IC device. The substrate assembly also comprises a layer of resilient conductive material formed on a surface of the substrate, the spring-biased electrical contacts being formed in the resilient conductive material layer in situ on the substrate. Each spring-biased electrical contact includes a surface or surfaces configured to bias against and electrically contact an IC device lead element. The present invention also encompasses methods of fabricating substrate assemblies according to the invention, including heat treating the substrate assembly after formation to achieve desired spring characteristics.

Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.

Abstract: In a semiconductor device which is assembled by making use of a lead frame 1 with a heat radiation plate 3 in which the lead frame 1 and the heat radiation plate 3 made of copper or copper alloy are joined by an adhesive layer 2 formed on a surface of the heat radiation plate 3 and at least a part of the inner leads 1a of the lead frame 1 is applied of a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of inconveniences such as leakage and shorting due to ion migration can be prevented.

Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.

Abstract: A multichip module that utilizes an angled interconnect to electrically interconnect chips in the module that are positioned at an angle relative to each other. The multichip module may comprise a first and second chips that are positioned in an orthogonal manner. The first and second chips are electrically interconnected via an interconnect structure comprising a first conductive pillar that extends from an outer surface of the first chip. A distal end of the first pillar is electrically connected to an outer surface of the second chip via a solder ball or another conductive pillar that is interposed between the distal end of the first conductive pillar and the second chip.

Abstract: The present invention provides a method and apparatus which facilitates wafer level burn-in testing of semiconductor dies. Sacrificial busses on the wafer supply voltage to respective on die Vcc and Vss sacrificial voltage pads during burn-in testing. The Vcc sacrificial pad on each die is connected to a secondary Vcc pad through an on-die sacrificial metal bus. An on-die fuse is interposed between the secondary Vcc pad and a normal Vcc die bonding pad. The fuse will blow when a die draws excessive current isolating a defective die from other dies on the wafer which are connected to the sacrificial busses. The Vss sacrificial pad is connected to a normal Vss die bonding pad through a sacrificial metal bus. After burn-in testing, the structures are removed. During this removal, the on-die sacrificial metal busses protect the secondary Vcc pad and Vss bonding pad. The secondary Vcc pad, Vcc bonding pad and Vss bonding pad can then be exposed for additional die testing.

Abstract: An electronic module having a semiconductor element and filters provided on a base substrate. The filters have an impedance conversion function and are directly connected to the semiconductor element without the aid of a matching circuit. Since no matching circuit is required between the semiconductor element and the filters, the electronic module can be made smaller and signal transmission loss can be suppressed.

Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A direct attachment technique is described for silicon packages housing high frequency devices. A silicon package may be shaped as either a plug or a socket or the package may have both the plug and socket capability, thus enabling the package to be directly attached to other packages The plug is trapezoidal in cross section while the socket has a dovetail-joint-like aperture. The plug is inserted into the socket thereby directly attaching one package to another. The two packages are locked together when the slanted edges of the plug are fitted to the slanted edges of the socket.

Abstract: The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.

Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.

Abstract: The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.

Abstract: A multilayer interconnection structure that offers a fast semiconductor operation is realized by employing copper wiring, electro migration of which is prevented from occurring by providing a via plug that includes a layer of a high melting-point metal, such as tungsten.

Abstract: A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10, and an interlayer dielectric layer 20 that covers the wiring layers 12. The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10, and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22, and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.

Abstract: A method for producing cavities, which are patterned in submicrometer dimensions, in a cavity layer of a semiconductor device, is described. In the method, a process liquid is frozen in the trenches in a process layer which has been patterned by ribs and trenches, then the process liquid is covered with a covering layer and is then expelled from the cavities resulting from the covering of the trenches.

Abstract: The present invention relates to a semiconductor device in which a barrier insulating film is formed to cover a copper film or a wiring consisting mainly of the copper film. In structure, the barrier insulating film 34a comprises a double-layered structure or more that is provided with at least a first barrier insulating film 34aa containing silicon, oxygen, nitrogen and hydrogen or silicon, oxygen, nitrogen, hydrogen and carbon, and a second barrier insulating film 34ab containing silicon, oxygen and hydrogen or silicon, oxygen, hydrogen and carbon.