Abstract: This invention describes a refrigerating oil composition for natural substance-based refrigerants which comprises (A) a synthetic oil component comprising a polyether compound having a pour point of −10° C. or lower and (B) a mineral oil component comprising sulfur components, wherein the ratio of amounts by weight of component (A) to component (B) is in the range of 25:75 to 99:1 and the amount of the sulfur components derived from component (B) in the composition is in the range of 5 to 1,000 ppm. The refrigerating oil composition has excellent miscibility with natural substance-based refrigerants and, in particular, with ammonia-based refrigerants, exhibits an improved lubricity and used for industrial refrigerators using natural substance-based refrigerants such as ammonia, propane, butane and carbon dioxide.

Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.

Abstract: A high voltage capable, insulating and resinous composition is disclosed. An epoxy-anhydride resin is prereacted with an antioxidant oligomer selected from the group consisting of organophosphorus compounds, sterically-hindered alkylated phenolics, alkyl and aryl thio-esters, alkyl and aryl thio-phosphites, thiazoles, lactones, hydroxylamines, and maleimides.

Abstract: The invention relates to an electrically conductive powder coating composition having anti-static properties comprising metallic fibres. Further, the coating composition shows effective EMF shielding. Very good results are found when the metallic fibres have an L/D ratio in the range between 5 and 75, wherein L is the length of the fibre and D is the diameter of the fibre. In a preferred embodiment stainless steel fibres are incorporated in the powder coating composition.

Abstract: A conductive polymer is disclosed which is suitable for use in applications which require corrosion resistance including resistance to corrosion when subjected to acidic flow at temperature ranging from −40 to 140 degrees Fahrenheit and which can be molded such as by compression and/or injection molding techniques, into highly intricate and thin specimens without significant post machining. and which exhibit consistent conductivity, sufficient strength and flexibility, and appropriate surface characteristics. In particular the invention involves molding resin composition, which have high loadings of conductive fillers. Further the compositions may include rheological modifiers such as Group II oxides and hydroxides; carbodiamides; aziridines; polyisocyanates; polytetrafluorethylene (PTFE); perfluoropolyether (PFPE), and polyethylene. In an additional embodiment of the invention, an anti-shrink additive is added to improve the characteristics of the molded fuel cell plate.

Abstract: A composite substance for forming a conductive paste, comprises a solvent and metal or metal compound particles. The solvent is compatible with an organic component included in the conductive paste, and the metal or metal compound particles are dried metal or metal compound particles having the second solvent adhering to the surface thereof. The conductive paste comprises an organic vehicle, a solvent, and the composite substance which is mixed with the organic vehicle and the solvent. The method for manufacturing the composite substance comprises the steps of washing metal or metal compound particles with water, adding a solvent that is compatible with an organic component included in the conductive paste, thereby replacing water components, and drying the metal or metal compound particles having the solvent adhering to the surface thereof.

Abstract: A ferrite core is provided. This ferrite core has high saturation flux density Bs at a high temperature of 100° C. or higher, and in particular, at around 150° C., and has excellent magnetic stability at a high temperature, experiencing reduced deterioration of magnetic properties, and in particular, reduced core loss at such high temperature (even by trading off some improvement in the level of the loss).

Abstract: Conjugated copolymers of dithienothiophene with vinylene or acetylene are suitable for use as semiconductors or charge transport materials in optical, electrooptical or electronic devices including field effect transistors, electroluminescent, photovoltaic and sensor devices.

Abstract: A coating liquid for forming an organic layer of an organic LED display which layer includes a light-emitting layer or a light-emitting layer and a charge-transporting layer, the liquid comprising: an organic material or a precursor thereof required for forming the organic layer, and at least one low volatile liquid solvent having a vapor pressure of 10 mmHg or less at 20° C. and a boiling point lower than a denaturing temperature of the organic material or lower than a converting temperature of the precursor.

Abstract: An electrochromic medium for use in an electrochromic device comprising: at least one solvent; a cathodic electroactive material; an anodic electroactive material; wherein at least one of the cathodic and anodic electroactive materials is electrochromic; and a self-healing cross-linked polymer gel.

Abstract: A roofer's hammer having multiple pry features of varying configurations as well as a striking face on a head portion. One feature is formed on the handle end, another comprises a special claw on the head portion, and a pry tooth projects to one side of the claw.

Abstract: An improved brace preferably for use with a post or other vertical or substantially vertical member. The brace is generally constructed of a first and second member which are connected, with the opposite or free end of each member being connected to, joined with, attached to, or retaining at least a portion of the post or other substantially vertical structure or member. The brace can be used without penetrating the substrate and is adjustable to different angles, heights, and forces.

Abstract: The subject of the disclosed technique is as follows: a structure in a ridge type semiconductor optical device having both high operation speed and high reliability together is attained.

Abstract: A semiconductor optical component is disclosed which includes a semiconductor material confinement layer containing acceptor dopants such that the doping is p-type doping. The confinement layer is deposited on another semiconductor layer and defines a plane parallel to the other semiconductor layer. Furthermore, the p-type doping concentration of the confinement layer has at least one gradient significantly different from zero in one direction in the plane. A method of fabricating the component is also disclosed.

Abstract: A quantum well structure is provided that includes two or more quantum well layers coupled by at least one barrier layer such that at least one of a piezo-electric field and a pyro-electric field is produced. The quantum well structure is sufficiently doped to cause a Fermi energy to be located between ground states and excited states of the coupled quantum well layers. The quantum well structure can be incorporated into a layered semiconductor to form optical devices such as a laser or optical amplifier.

Abstract: A modulation doped multiple quantum well structure having a steep Zn profile of several nm by the balance between an increase in a Zn concentration and a decrease in Zn diffusion by using metal organic vapor phase epitaxy using Zn, in which an InGaAlAs quaternary alloy is used and the Zn concentration and the range for crystal composition are defined to equal to or less than the critical concentration at which Zn diffuses abruptly in each of InGaAlAs compositions.

Abstract: A power transistor includes an n+ Si substrate, which has a surface intended for deposition, which is cleaned by wet chemical cleaning and further cleaned by vacuum heated cleaning, an n− Si buffer layer, which is deposited on the Si substrate as a deposition by CVD to cover impurities remaining on the surface intended for deposition, a p SiGe base layer, which is deposited as a deposition on the Si buffer layer by CVD, an n Si emitter layer on the SiGe base layer, a base electrode, an emitter electrode, and a collector electrode.

Abstract: The present invention comprises a junction between an unconventional superconductor, an intermediate material, and a conventional superconducting material. In some embodiments, the unconventional superconductor has an orthorhombic crystal structure and the supercurrent in the resulting junction flows in the c-axis direction of the orthorhombic crystal. In other embodiments, the supercurrent flows parallel to a direction in the a-b plane. Interface junctions according to embodiments of the present invention may be used in superconducting low inductance qubits (SLIQs) and in permanent readout superconducting qubits (PRSQs), can form the basis of quantum registers, and can permit parity keys or other devices made from conventional superconducting material to be attached to qubits made from unconventional superconducting material or vice versa.

Abstract: A thin film transistor array substrate includes an insulating substrate, and gate lines formed on the substrate, storage electrode lines and storage electrodes are also formed on the substrate. Data lines cross over the gate lines and the storage electrode lines. The data lines are electrically insulated from the gate lines and the storage electrode lines. Thin film transistors are connected to the data lines and the gate lines, and pixel electrodes are connected to the thin film transistors. Bridges are formed at the same plane as the pixel electrodes while interconnecting the storage electrode lines and the storage electrodes placed at both sides of the gate lines. The storage electrode lines and the storage electrodes have protrusions or grooves placed close to the bridges to indicate the locations of laser illumination.

Abstract: The present invention provides a method and apparatus which facilitates wafer level burn-in testing of semiconductor dies. Sacrificial busses on the wafer supply voltage to respective on die Vcc and Vss sacrificial voltage pads during burn-in testing. The Vcc sacrificial pad on each die is connected to a secondary Vcc pad through an on-die sacrificial metal bus. An on-die fuse is interposed between the secondary Vcc pad and a normal Vcc die bonding pad. The fuse will blow when a die draws excessive current isolating a defective die from other dies on the wafer which are connected to the sacrificial busses. The Vss sacrificial pad is connected to a normal Vss die bonding pad through a sacrificial metal bus. After burn-in testing, the structures are removed. During this removal, the on-die sacrificial metal busses protect the secondary Vcc pad and Vss bonding pad. The secondary Vcc pad, Vcc bonding pad and Vss bonding pad can then be exposed for additional die testing.

Abstract: Inexpensive, unannealed glass is used as a substrate. The surface of a polycrystalline silicon film doped with boron (B) or phosphorus (P) is oxidized with ozone at a processing temperature of 500° C. or below to form a silicon oxide film of 4 to 20 nm thick on the surface of polycrystalline silicon. On account of this treatment, the level density at the interface between the gate-insulating layer and the channel layer can be made lower, and a thin-film transistor having less variations of characteristics can be formed on the unannealed glass substrate.

Abstract: A semiconductor integrated circuit device includes a plurality of internal circuits, an internal power supply potential generating circuit for converting a level of an external power supply potential to supply an internal power supply potential at a level according to a level set signal, a control portion for successively applying said plurality of level set signals to each internal potential generating circuit for successively producing a plurality of internal potentials at different levels in a test operation, and a measuring circuit for making a comparison between each internal potential and a reference potential, and holding information representing results of the comparison.

Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

Abstract: Controlling, guiding, manipulating, and circuiting light and performing surface-enhanced spectroscopy in a medium comprising plasmonic nanomaterials via the excitation of plasmon modes in the materials. The plasmonic nanomaterials are based on metal films with or without arrays of nanoholes and/or on metal nanowires and/or spheroids. Also devices and methods employing such plasmonic nanomaterials.

Abstract: A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

Abstract: A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor substrate. Each cell includes a storage element for storing a quantity of charge indicative of the state of the memory cell and a valve element that inhibits the quantity of charge from changing during quiescent periods. The storage elements are disposed adjacent a plurality of storage regions of the substrate and the valve elements are disposed adjacent a plurality of valve regions of the substrate. A plurality of dopant atoms are selectively implanted into the array portion so as to increase a threshold voltage which is required to develop a conducting channel through the valve region. The dopant atoms are disposed mainly throughout the valve regions of the substrate and are substantially absent from the storage regions.

Abstract: An image sensor includes an array of pixels formed in a semiconductor substrate. The pixels are grouped as a center portion of pixels and an outer portion of pixels. A first set of micro-lenses is formed over each of the pixels in the center portion of pixels. A second set of micro-lenses is formed over each of the pixels in the outer portion of pixels. The second set of micro-lenses differ from said first set of micro-lenses. In one embodiment, the second set of micro-lenses are taller than the first set of micro-lenses.

Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

Abstract: At least a lower cladding layer, an active layer for generating laser light, a first upper cladding layer, an etching stopper layer and a second upper cladding layer are stacked on a substrate. An impurity for restraining laser light absorption is diffused into the second upper cladding layer along a region where a light-emitting end surface is to be formed, under a condition that allows the etching stopper layer to maintain a function of stopping etching for the second upper cladding layer (First annealing process). Etching is performed until the etching stopper layer is reached such that the second upper cladding layer is left in a ridge shape. The impurity in the second upper cladding layer is re-diffused into the active layer to thereby cause local intermixing of the active layer in a portion extending along the light-emitting end surface and located just under the ridge (Second annealing process).

Abstract: A solid-state light source includes a semiconductor light source for emitting light and an optical system having a fiber optic element. The fiber optic element has an input for receiving emitted light from the semiconductor light source. The fiber optic element also has an output for emitting light received from the solid-state light source. The semiconductor light source and the fiber optic element in aggregate form an illumination path.

Abstract: This invention discloses the basic chip architecture and packing configuration required to build an all silicon opto-coupler in which a forward biased silicon PN junction diode is used as the LED. Construction of the LED and the detector are disclosed as well as the package chip configuration. Methods for isolating circuit structures from the LED are also disclosed so that CMOS and bipolar circuits can freely added to the transmitting chip as well as the receiving chip. Bi-directional data transmission and multi-channel operation is also shown.

Abstract: A semiconductor optical device includes, on a semiconductor substrate, a mesa-stripe-like multilayer structure constituted by at least an n-cladding layer, an active region formed from an active layer or a photoabsorption layer, and a p-cladding layer, and a buried layer in which two sides of the multilayer structured are buried using a semi-insulating semiconductor crystal. The buried layer includes a diffusion enhancement layer which is adjacent to the mesa-stripe-like multilayer structure and enhances diffusion of a p-impurity, and a diffusion suppression layer which is adjacent to the diffusion enhancement layer and suppresses diffusion of a p-impurity. A method of manufacturing a semiconductor optical device is also disclosed.

Abstract: A method of forming a partially etched nitride-based compound semiconductor crystal layer includes the following steps. A non-crystal layer of a nitride-based compound semiconductor is formed. At least a part of the non-crystal layer is then etched to form a partially etched non-crystal layer before the partially etched non-crystal layer is crystallized to form a partially etched nitride-based compound semiconductor crystal layer.

Abstract: The invention relates to a thermoelectric element comprising at least one n-type layer (1) and at least one p-type layer (2) of one or more doped semiconductors, whereby the n-type layer(s) (2) are arranged to form at least one pn-type junction (3). At least one n-type layer (1) and at least one p-type (2) are contacted in an electrically selective manner, and a temperature gradient (T1, T2) is applied or tapped parallel (x-direction) to the boundary layer (3) between at least one n-type layer (1) and p-type layer (2). At least one pn-type junction is formed essentially along the entire, preferably longest, extension of the n-type layer(s) (1) and of the p-type layer(s) (2) and thus essentially along the entire boundary layer (3) thereof.

Abstract: A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.

Abstract: The invention relates to an arrangement for improving the ESD protection in an integrated circuit. In order to achieve an effective use of chip area, it is proposed to connect a passive component between the bonding pad and an integrated circuit, said passive component being arranged over an electrically non-conductive layer and under the bonding pad. In the event of damage to the bonding pad when bonding or testing, only the passive component, at most, is short-circuited, but the functionality of the output driver stage and of the integrated circuit remains unaffected.

Abstract: One or more deep-array implants under the photosensitive region of a semiconductor substrate are conducted to improve optical cross-talk between pixel cells. According to an embodiment of the present invention, one or more deep-array implants of a first conductivity type are used to dope predefined regions of a well of a second conductivity type. This way, first conductivity type dopants from the one or more deep-array implants counterdope second conductivity type dopants from the predefined regions of the well. The dosage and energy of each deep-array implant may be optimized so that the collection of signal carriers by the photosensitive region and the photoresponse for different wavelengths are maximized.

Abstract: The present invention provides methods and apparatus for creating insulating layers in Group III-V compound semiconductor structures having aluminum oxide with a substantially stoichiometric compositions. Such insulating layers find applications in a variety of semiconductor devices. For example, in one aspect, the invention provides vertical insulating layers separating two devices, such as photodiodes, formed on a semiconductor substrate from one another. In another aspect, the invention can provide such insulating layers as buried horizontal insulating layers of semiconductor devices.

Abstract: A heterojunction field effect transistor has a high forward withstand voltage between a gate and a source, and includes a channel layer, a carrier supply layer, a first Schottky contact layer preferably made of AlGaAs, a second Schottky contact layer which preferably made of AlGaAs having an Al component ratio that is lower than that of the first Schottky contact layer, and a contact layer, which are disposed in that order on a semiconductor substrate. A groove is formed by removing a portion of the contact layer. A gate electrode extending from a region on a portion of the surface of the second Schottky contact layer to the surface or the inside of the first Schottky contact layer is formed in the groove. Accordingly, the Schottky barrier height is increased, and a high forward withstand voltage between the gate and the source is achieved. In addition, since the distance between the gate electrode and the channel layer is decreased, a high mutual conductance is achieved.

Abstract: A transistor having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The collector layer formed from InGaAs, and the collector layer being doped n-type. The emitter layer formed from InP, and the emitter layer being doped n-type. The base layer formed of indium gallium arsenide (InGaAs), the base layer being tensile mismatched, and doped p-type. A lattice mismatch between the substrate and the base material is greater than 0.2%. In an x-ray rocking curve of the heterojunction bipolar transistor, a peak corresponding to the base layer is separated from a peak corresponding to the substrate layer by at least 250 arcseconds. In one embodiment this results from the percentage of indium in the base layer is less than 51.5%, that is the lattice constant of the base layer is substantially smaller than a lattice constant of the substrate throughout an entire base region.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench(27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.

Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.

Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.

Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Abstract: A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

Abstract: An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.

Abstract: A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

Abstract: The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an electrode. Another embodiment relates to a system that includes the vertical transistor or the vertical storage cell.

Abstract: A compensation circuit and method for compensating for the threshold shift in an irradiated MOSFET. The method determines the gate threshold voltage to body voltage relationship to vary the body voltage with radiation. The compensation circuit (10) has at least one MOSFET (Q2) having the same channel type as the MOSFET being compensated (Q1). The at least one matching MOSFET (Q2) is connected to the gate of the MOSFET (Q1) being compensated. At least one MOSFET (Q3, Q4) having a channel type that is different from the channel type of the MOSFET (Q1) being compensated is connected to the gate of the matching MOSFET (Q2). The result is that the compensation circuit (10) controls a negative shift in the body voltage of the MOSFET (Q1) being compensated resulting in a higher threshold voltage.