Abstract: Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two sides, and two ends; and a conductive inhibitor strip that adjoins a portion of one of the two sides of the p-type strip and a portion of one of the two sides of the n-type strip so as to inhibit cross-diffusion between the p-type strip and the n-type strip while electrical connection between n-type and p-type polycrystalline silicon is maintained.

Abstract: A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.

Abstract: Structure and methods for the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions are provided. These PMOS devices minimize tunneling leakage currents in DRAM capacitors, cells and devices, as well as conserve power supply currents to minimize power dissipation. A memory cell is provided which utilizes p-type semiconductor or metal gates or capacitor plates with work functions larger than those of n-type doped polysilicon (4.1 eV) or the commonly used aluminum metal in MOS technology (4.1 eV). The memory cell includes a PMOS transistor. The PMOS transistor includes a first source/drain region and a second source/drain region separated by a channel region. The first and the second source/drain region include source/drain regions having a large work function. The PMOS transistor has a gate opposing the channel region and separated therefrom by a gate insulator. The gate includes a gate having a large work function.

Abstract: A field-effect transistor is formed with a gate stack, which is patterned by a hard mask and contains a first part of a gate electrode and a second part of the gate electrode that is disposed on the first part. The second part of the gate electrode, which is disposed between the patterned hard mask and the first part of the gate electrode, is laterally recessed, so that the second part of the gate electrode, in a contact hole which is subsequently formed, is at a greater distance from a contact plug with which the contact hole is filled, in order to avoid short circuits.

Abstract: A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.

Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.

Abstract: A semiconductor memory device of the present invention includes: a semiconductor substrate; a memory cell capacitor for storing data, including a first electrode provided above the semiconductor substrate, a capacitance insulating film formed on the first electrode, and a second electrode provided on the capacitance insulating film; a step reducing film covering an upper surface and a side surface of the memory cell capacitor; and an overlying hydrogen barrier film covering the step reducing film.

Abstract: A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored the replacement information; and an input/output port for outputting information PI actually stored in the first LT fuse group and information CI actually stored in the second LT fuse group to an external memory tester. The first and second LT fuse groups are fabricated according to the same conditions, and the laser input to the respective group is set to be under the same conditions.

Abstract: A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Abstract: This semiconductor apparatus includes a semiconductor element having a structure which becomes conductive by movement of the carrier in the vertical direction of a semiconductor substrate. Further, this semiconductor apparatus includes a joint substrate joined to the semiconductor substrate in order to give mechanical strength to the semiconductor element.

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

Abstract: A non-volatile semiconductor memory device includes a p-type Si substrate, an n-type well formed in the Si substrate, a control gate of a p-type buried diffusion region formed in the n-type well, an active region formed in the Si substrate in the vicinity of the n-type well and covered by a tunneling insulation film, and a floating gate electrode formed on the Si substrate so as to achieve a capacitance coupling with the p-type buried diffusion region, wherein the floating gate electrode extends on the active region over the tunneling insulation film, and the active region including a pair of n-type diffusion regions are formed at both sides of the floating gate electrode as source and drain regions, the n-type diffusion region forming the source region having an n−-type diffusion region at the side facing the n-type diffusion region forming said drain region.

Abstract: Disclosed is a fabrication method for a non-volatile semiconductor memory device that comprises a pattern forming step in which by using a first mask layer and a second mask layer formed in a common lithography step as masks, a pattern is formed from a second layer, a third layer, a fourth layer, a sixth layer and a protection layer in a laminated substrate having, in a memory cell area, a sequential lamination of a first layer for forming a first insulating layer, the second layer for forming a floating gate, the third layer for forming an intergate insulating layer, the fourth layer for forming a control gate and a first mask layer, and having, in a logic area, a sequential lamination of a fifth layer for forming a second insulating layer, the sixth layer for forming a logic gate, the protection layer for protecting the sixth layer at the time of forming the control gate and a second mask layer.

Abstract: The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element.

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.

Abstract: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

Abstract: In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

Abstract: The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n− silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n− silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n− silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n− silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n− silicon substrate (1).

Abstract: A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain voltage and a positive gate voltage are applied. A current that can be controlled with the gate voltage flows in the inversion channels.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate electrode layer with a gate insulating layer interposed therebetween. The semiconductor layer is formed so that its width W1 is smaller than its height H1. As a result, a thin film transistor and manufacturing method thereof can be obtained in which contact between a source/drain region of the thin film transistor and an upper or lower conductive layer can be made stably.

Abstract: A voltage applying section (32) is connected to a silicon substrate (1). Emission of radiation to a semiconductor device causes a large number of holes to accumulate within a BOX layer (2) in the vicinity of the interface with respect to a silicon layer (3). The amount of accumulation of holes increases with a lapse of time. A voltage applying section (32) applies a negative voltage which decreases with the lapse of time to the silicon substrate (1) in order to cancel out a positive electric field resulting from the accumulated holes. The voltage applying section (32) includes a time counter (30) for detecting the lapse of time and a voltage generating section (31) connected to the silicon substrate (1) for generating a negative voltage (V1) which decreases in proportion to the lapse of time based on the result of detection (time T) carried out by the time counter (30). Consequently, a semiconductor device capable of suppressing occurrence of total dose effects is obtained.

Abstract: The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers.

Abstract: The present invention concerns a method of forming multi-layers such as base-coat and active layers for TFTs. In accordance with the preferred embodiment of the present invention, a first layer is formed on a transparent substrate using a physical vapor deposition. And a second layer is sequentially formed using a physical vapor deposition on the first layer without breaking vacuum.

Abstract: A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.

Abstract: MOS transistor comprising:

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.

Abstract: A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity &rgr; (&OHgr;cm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract: Formation of sidewalls on a gate structure in layers having a differential etch rate for certain etchants allows metallization and salicide formation annealing of a gate electrode and source/drain regions prior to shallow impurity implantation and impurity activation annealing at the location of a removable portion of a sidewall spacer establishing a gap between source/drain regions and remaining sidewalls of a gate structure. Therefore, diffusion of impurities to a greater depth and impurity deactivation during salacide formation annealing is avoided in a high performance semiconductor device such as a field effect transistor of extremely small dimensions.

Abstract: A semiconductor device having a metal suicide layer and a method of manufacturing the same are provided. A spacer material layer is formed on a semiconductor substrate on which a gate and a source and drain region having a low impurity concentration are formed. Only the spacer material layer, which is formed in a region in which a silicide layer is to be formed, is etched. A source and drain region having a high impurity concentration is formed in the exposed semiconductor substrate, and a silicide layer is formed on the source and drain region having a high impurity concentration. Since an extra silicide blocking layer (SBL) is not formed, a photomask process of patterning a SBL is not performed. That is, one photolithographic process is reduced in comparison with a conventional process of selectively forming a silicide layer. Thus, a process of manufacturing a semiconductor device can be simplified, thereby reducing process costs and reducing the danger of misalignment occurring during a photomask process.

Abstract: A semiconductor memory device assembled in a flip chip package includes a memory cell array divided into subarrays arranged in matrix form, and a peripheral circuit area and a pad area formed in middle sections of the subarray matrix. The pad area includes pads arranged at the same pitches as those of the subarrays, and a signal connecting the peripheral circuit area and each of the subarrays is linearly formed so as to pass between the pads. The variations of delay time of signals supplied to the subarrays are avoided and the transmission time of signals is kept constant, thereby achieving a high-speed operation.

Abstract: Disclosed herein is a peripheral LSI containing a number of microprocessor peripheral IPs. Even when the peripheral IPs are integrated, this peripheral LSI can prevent the package price from rising, the power consumption from increasing, and the software designers from being perplexed. A switch of the programmable peripheral LSI is provided for electrically disabling peripheral IPs. As a result, the peripheral IPs are disabled while they are not used.

Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

Abstract: In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: A memory cell which allows information to be written or erased electrically. The memory cell includes a gate insulation film including three layers, i.e., a first insulation layer, an electric charge accumulating layer and a second insulation layer and a gate electrode formed on the gate insulation film. The electric charge accumulating layer is composed of a silicon nitride film or silicon oxynitride film. The first and second insulation layers are composed of a silicon oxide film or silicon oxynitride film containing more oxygen composition than the electric charge accumulating layer. The thickness of the second insulation layer is more than 5 nm. The gate electrode is formed of a p-type semiconductor containing p-type impurity.

Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

Abstract: A micromechanical switch comprises a substrate, at least one pair of support members fixed to the substrate, at least one pair of beam members placed in proximity and parallel to each other above the substrate, and connected to one of the support members, respectively, each of the beam members having a moving portion which is movable with a gap with respect to the substrate, and a contact portion provided on the moving portion, and a driving electrode placed on the substrate between the pair of beam members to attract the moving portions of the beam members in a direction parallel to the substrate with electrostatic force so that the contact portions of the beam members which are opposed to each other are short-circuited.

Abstract: A magnetoresistive device (11) having a lateral structure and provided with a non-magnetic spacer layer (3) of organic semiconductor material allows the presence of an additional electrode (19). With this electrode (19), a switch-function is integrated into the device (11). Preferably, electrically conductive layers (13,23) are present for the protection of the ferromagnetic layers (1,2). The magnetoresistive device (11) is suitable for integration into an array so as to act as an MRAM device.

Abstract: Similar patterns of spacer ribs (7, 8) are applied on the two substrates (3, 4) of a display. Small misalignments are corrected by the shape and positioning of the patterns when the two substrates are pressed together, for example, in a reel-to-reel process.