Patents Issued in March 20, 2003
  • Publication number: 20030052335
    Abstract: A capacitor stack (12) in a layer structure of an integrated component has the same layer sequence as an adjacent interconnect (13), with the exception of a dielectric interlayer (5). This significantly facilitates the fabrication of vias (16).
    Type: Application
    Filed: October 15, 2002
    Publication date: March 20, 2003
    Inventors: Rudolf Lachner, Michael Schrenk, Markus Schwerd
  • Publication number: 20030052336
    Abstract: An electro-optical device having high operation performance and high reliability, and electronic equipment which include the electro-optical device, are provided. A TFT structure that is strong against hot carrier injection is realized by placing an LDD region which overlaps a gate electrode in an n-channel TFT forming a driver circuit. Furthermore, a TFT structure having a low off current value is realized by placing LDD regions which do not overlap a gate electrode in a pixel TFT forming a pixel section. In addition, the electro-optical device has a memory section on the same insulator, the memory section having a memory transistor and storing data.
    Type: Application
    Filed: October 4, 2002
    Publication date: March 20, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidehito Kitakado, Takeshi Fukunaga
  • Publication number: 20030052337
    Abstract: In a thin film transistor provided with a metallic layer with a light-shading property and a Si layer formed on an insulating layer, a dent for locally thinning the insulating layer is formed on a portion corresponding to a drain region. When the Si layer is recrystallized by means of a laser light irradiation, the dent serves as a crystalline nucleus formation region in order to recrystallize a particular portion earlier than other portions. Recrystallization of melted Si starts from a periphery of a bottom surface of the dent, hence a Si layer formed of a single crystal or uniformed crystal grains which serves as an active region of the TFT can be obtained.
    Type: Application
    Filed: October 16, 2002
    Publication date: March 20, 2003
    Inventor: Hiroshi Tanabe
  • Publication number: 20030052338
    Abstract: Semiconductor devices that utilize a silicon-containing dielectric layer are disclosed. In one embodiment, a silicon-containing material is deposited on a substrate. The deposited material is processed with a reactive agent to react with silicon atoms of the deposited material to form the dielectric layer. The silicon-containing dielectric layer provides for improved or smaller semiconductor devices by reducing leakage and increasing the dielectric constant.
    Type: Application
    Filed: October 18, 2002
    Publication date: March 20, 2003
    Inventors: Don Carl Powell, Garry Anthony Mercaldi
  • Publication number: 20030052339
    Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.
    Type: Application
    Filed: October 28, 2002
    Publication date: March 20, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigeru Harada, Yoshifumi Takata, Junko Izumitani
  • Publication number: 20030052340
    Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.
    Type: Application
    Filed: November 1, 2002
    Publication date: March 20, 2003
    Inventor: Mark Tuttle
  • Publication number: 20030052341
    Abstract: A semiconductor integrated circuit device comprises vertical power supply wiring 12 divided into first and second narrow-width vertical power supply wirings 12a and 12b, vertical ground wiring 14 disposed in parallel with vertical power supply wiring 12 and divided into first and second narrow-width vertical ground wirings 14a and 14b, auxiliary vertical power supply wiring 22 connecting first narrow-width vertical power supply wiring 12a and second narrow-width vertical power supply wiring 12b, and auxiliary vertical ground wiring 24 connecting first narrow-width vertical ground wiring 14a and second narrow-width vertical ground wiring 14b.
    Type: Application
    Filed: August 6, 2002
    Publication date: March 20, 2003
    Inventor: Takenobu Iwao
  • Publication number: 20030052342
    Abstract: The present invention relates generally to a method for forming a pattern and a semiconductor device, and in particular, to a method for forming a pattern for the formation of quantum dots or wires with (1)˜(50) nm dimension using the atomic array of a crystalline material and to the manufacture of functional devices that have such a structure.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 20, 2003
    Inventor: Ki-Bum Kim
  • Publication number: 20030052343
    Abstract: A semiconductor chip includes a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each being operable to produce a respective output clock signal from an associated input clock signal in accordance with an error signal, the outputs of a subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the clock buffers adjust the respective output clock signals in accordance with the respective error signals.
    Type: Application
    Filed: October 22, 2002
    Publication date: March 20, 2003
    Applicant: Sony Computer Entertainment America Inc.
    Inventor: Hidetaka Magoshi
  • Publication number: 20030052344
    Abstract: An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Inventors: Kurt Hoffmann, Oskar Kowarik
  • Publication number: 20030052345
    Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 20, 2003
    Applicant: Elpida Memory, Inc.
    Inventors: Satoshi Isa, Seiji Funaba
  • Publication number: 20030052346
    Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for inspecting of bumps and other three dimensional (3D) features on wafers and other semiconductor substrates. The sensor eliminates out of focus light using a confocal principal to improve depth response.
    Type: Application
    Filed: February 11, 2002
    Publication date: March 20, 2003
    Inventors: Cory Watkins, David Vaughnn
  • Publication number: 20030052347
    Abstract: As the silicon-on-insulator field effect transistor (SOI FET) CMOS technology continues migrating towards thinner SOI thicknesses to reduce the parasitic capacitance and improve the short channel effects, it is known that the body resistance of body contacted MOSFETs increases correspondingly. The problem is compounded for strong halo and weak wells device designs for T-shaped or L-shaped BC-MOSFETs. The invention provides a structure and a method that includes an additional well level implant for n-type and p-type devices in selected parts of the extended gate region. A new mask increases the channel doping at the extended gate region to prevent that region from fully depleting and increasing the carrier concentration for lower resistance. Since the physical gate dimensions are usually narrower than the mask dimensions, the mask is slightly offset from the extended gate edge to avoid excessive encroachment into the intrinsic device channel region.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 20, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ka Hing Fung
  • Publication number: 20030052348
    Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.
    Type: Application
    Filed: October 11, 2002
    Publication date: March 20, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takeshi Takagi, Akira Inoue
  • Publication number: 20030052349
    Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Inventors: Hae-Seung Lee, Keith Glen Fife
  • Publication number: 20030052350
    Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.
    Type: Application
    Filed: May 17, 2000
    Publication date: March 20, 2003
    Inventor: Keiichi Ohno
  • Publication number: 20030052351
    Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.
    Type: Application
    Filed: September 17, 2001
    Publication date: March 20, 2003
    Inventors: Daniel Xu, Chien Chiang
  • Publication number: 20030052352
    Abstract: A semiconductor device has a semiconductor substrate and a resistor group and/or a signal interconnection layer on a region in this semiconductor substrate. A shielding layer provided above and/or below the region where the resistor group and/or the signal interconnection layer has been provided.
    Type: Application
    Filed: February 20, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinya Soeda
  • Publication number: 20030052353
    Abstract: A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.
    Type: Application
    Filed: February 27, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tsuyoshi Fujiwara, Takeshi Saikawa, Ryouichi Furukawa, Masato Kunitomo
  • Publication number: 20030052354
    Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.
    Type: Application
    Filed: October 24, 2002
    Publication date: March 20, 2003
    Inventor: Charles H. Dennison
  • Publication number: 20030052355
    Abstract: The transmitter or receiver comprises several transducers made opposite an aperture in a package.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Inventors: Herve Jaouen, Thomas Skotnicki, Malgorzata Jurczak
  • Publication number: 20030052356
    Abstract: The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.
    Type: Application
    Filed: October 11, 2002
    Publication date: March 20, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Haining Yang, Gurtej S. Sandhu
  • Publication number: 20030052357
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦y≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNB1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2(TayNb1−y)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≳40, and preferably about 100.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 20, 2003
    Applicant: Symetrix Corporation
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20030052358
    Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 20, 2003
    Applicant: Micron Technology Inc.
    Inventor: Ronald A. Weimer
  • Publication number: 20030052359
    Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
    Type: Application
    Filed: December 7, 2001
    Publication date: March 20, 2003
    Inventors: Sung Hun Shin, Jae Doo Eom
  • Publication number: 20030052360
    Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.
    Type: Application
    Filed: August 20, 2002
    Publication date: March 20, 2003
    Inventors: Daniel C. Guterman, Gheorghe Samachisa, Yupin Kawing Fong, Eliyahou Harari
  • Publication number: 20030052361
    Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.
    Type: Application
    Filed: October 29, 2002
    Publication date: March 20, 2003
    Inventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch
  • Publication number: 20030052362
    Abstract: A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same are disclosed, the semiconductor device including a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insulating layer formed in the trenches and beneath a surface of the substrate to have a recess, a polysilicon layer formed on the insulating layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.
    Type: Application
    Filed: October 31, 2002
    Publication date: March 20, 2003
    Applicant: Hyundai Electronics Industries Co., Ltd.
    Inventors: Eun Jeong Park, Sung Chul Lee
  • Publication number: 20030052363
    Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.
    Type: Application
    Filed: October 15, 2002
    Publication date: March 20, 2003
    Inventor: Yoshihiro Kumazaki
  • Publication number: 20030052364
    Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 20, 2003
    Applicant: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, James M. Leas, William H-L Ma, Paul A. Rabidoux
  • Publication number: 20030052365
    Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
  • Publication number: 20030052366
    Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
    Type: Application
    Filed: October 30, 2002
    Publication date: March 20, 2003
    Inventors: Yoshifumi Okabe, Masami Yamaoka, Akira Kuroyanagi
  • Publication number: 20030052367
    Abstract: A number of different arrangements of island structures are utilized for improved ESD protection. The MOSFET structure provides islands that are selectively positioned among a group of ESD protection devices for protecting the power-bus, input pins, output pins and I/O pins to achieve ESD improvement in a manner which improves overall ESD protection strength while reducing the complexity of IC simulation and modeling.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 20, 2003
    Inventor: Shi-Tron Lin
  • Publication number: 20030052368
    Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Applicant: Yamaha Corporation
    Inventors: Nobuaki Tsuji, Terumitsu Maeno
  • Publication number: 20030052369
    Abstract: Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding output pull up transistor, and further comparison circuits are provided, corresponding to a plurality of pull down transistors, each for comparing the voltage of the output node and each respective reference voltage different in voltage level from other, and each for adjusting an amount of a drive current of a corresponding pull down transistor in accordance with a result of comparison. The reference voltages each are set to a voltage level between a power supply voltage and a ground voltage. Without a dedicated power supply pin terminal, a signal of a small amplitude having the amplitude limited stably and precisely can be output at high speed.
    Type: Application
    Filed: August 15, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takeshi Kajimoto
  • Publication number: 20030052370
    Abstract: A semiconductor laser driving circuit drives a plurality of semiconductor laser devices having different objective operating voltages, and has a power source for generating power voltages for the semiconductor laser devices, a power voltage changeover means for changeover from one of the power voltages to another, a current amplification section for supplying a driving current to the semiconductor laser device with the power voltage so that the semiconductor laser device comes to have its respective objective operating voltage.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 20, 2003
    Inventor: Mitsuo Ishii
  • Publication number: 20030052371
    Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.
    Type: Application
    Filed: October 4, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Publication number: 20030052372
    Abstract: A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yoshikazu Ibara, Atsuhiro Nishida
  • Publication number: 20030052373
    Abstract: The present invention relates to a field effect transistor formed on a semiconductor thin film formed on an insulating substrate, and to an integrated circuit thereof. Provided is a structure such that a maximum allowable voltage in an output voltage is improved and a bipolar transistor is attained. A field effect transistor according to the present invention employs a structure in which a body contact region is interposed between source regions in order to realize a higher maximum allowable voltage with a smaller area. In order to realize the bipolar transistor with an increased channel width without external wirings for fixing a body potential, a structure of a transistor is also formed in which a drain/source region, a first gate electrode, a portion where a body contact region is arranged with a second region having a first conductivity type, a second gate electrode, and a source/drain region are arranged.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 20, 2003
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Hiroaki Takasu, Jun Osanai
  • Publication number: 20030052374
    Abstract: Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which a dielectric constant is higher than that of the first dielectric layer, stacked on the first dielectric layer. Also disclosed are methods for fabricating the semiconductor device.
    Type: Application
    Filed: September 12, 2002
    Publication date: March 20, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Jong-Hyuk Oh
  • Publication number: 20030052375
    Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 20, 2003
    Inventor: Hiroki Koga
  • Publication number: 20030052376
    Abstract: Disclosed is a semiconductor device with high-k dielectric layer. The semiconductor device has a dielectric layer including a first dielectric layer containing aluminum and a second dielectric layer containing lithium in the first dielectric layer.
    Type: Application
    Filed: September 12, 2002
    Publication date: March 20, 2003
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kee-Jeung Lee, Su-Jin Chae
  • Publication number: 20030052377
    Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 20, 2003
    Applicant: Micron Technology Inc.
    Inventor: Ronald A. Weimer
  • Publication number: 20030052378
    Abstract: A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and a gate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.
    Type: Application
    Filed: April 12, 2001
    Publication date: March 20, 2003
    Inventors: Tadahiro Ohmi, Hiroyuki Shimada
  • Publication number: 20030052379
    Abstract: A module for optical communications includes a light receiving element which converts the light signal to an electric signal and an insulating substrate including first and second surfaces opposite to each other. An output section is provided on the first surface and extracts the electric signal as reverse and non-reverse signals. First and second connection terminals are connected to the output section and output the reverse and non-reverse signals. First and second wiring patterns are provided on the first surface. The first and second wiring patterns are electrically connected to one of the first and second wiring patterns and the other one thereof. The first and second wiring patterns have first and second ends, respectively. The first and second ends are provided in order in a direction intersecting with a line connecting the first and second connection terminals.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 20, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Sadao Tanikoshi, Masato Yoshida
  • Publication number: 20030052380
    Abstract: A layout of a carrier in an optical component having the carrier and an optical device is described. The layout comprises a pair of terminals, a resistor connected to a first terminal, a wire bond connected in series with the resistor for connecting the resistor to an optical device, and a first ground patch connected to a second terminal and for connecting to an optical device for providing a common ground on a first surface on a substrate on which the carrier is based, whereby the pair of terminals, the resistor, the wire bond and an optical device form an optical signal transmission system in the optical component.
    Type: Application
    Filed: November 20, 2001
    Publication date: March 20, 2003
    Inventors: Mui Seng Yeo, Yong Kee Yeo, Mahadevan K. Iyer, Eitaro Ishimura, Gou Sakaino
  • Publication number: 20030052381
    Abstract: Disclosed is a solid state image sensing device. The solid state image sensing device comprises a semiconductor chip for image sensing which has at least one of photoelectric conversion element line; and a package into which the semiconductor chip is received. The package is composed of an insulating package body which has the semiconductor chip mounted on a flat inner bottom surface of a concave portion; a transparent cover glass to be fixed on an upper surface of an outer frame of the concave portion for sealing the concave portion; and a lead frame which is brought out to the outside of the package body. The solid state image sensing device has a reference plane for attaching onto an image input apparatus is arranged on the package. The reference plane for attaching is made parallel to the inner bottom surface of the concave portion on which the semiconductor chip is mounted.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 20, 2003
    Inventors: Jun Andoh, Tatsuya Tsuyuki
  • Publication number: 20030052382
    Abstract: Systems and methods are described for compositions, apparatus and/or electronic devices. A composition, includes a composition layer defining a first surface and a second surface, the composition layer including a collection layer that is located closer to the first surface than to the second surface. An apparatus, includes a semiconductor absorber layer defining a first surface and a second surface; and an electrode layer coupled to the first surface of the semiconductor absorber layer, wherein the semiconductor absorber layer includes a collection layer that is located closer to the first surface than to the second surface.
    Type: Application
    Filed: September 20, 2001
    Publication date: March 20, 2003
    Inventor: Billy J. Stanbery
  • Publication number: 20030052383
    Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.
    Type: Application
    Filed: August 2, 2002
    Publication date: March 20, 2003
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Michio Nemoto, Tatsuya Naito, Masahito Otsuki, Mitsuaki Kirisawa
  • Publication number: 20030052384
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Application
    Filed: May 9, 2002
    Publication date: March 20, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji