Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A first insulation layer 33 is embedded between adjacent ones of the fuses 20. A second insulation layer 39 is formed on the first insulation layer 33. The first insulation layer 33 and the second insulation layer 39 are formed such that their interface 42 is generally at the same level as the top surface of the fuses 20. As a result, the fuses may be reliably fused without generating cracks in the interface 42 at the time of fusing the fuses.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: A bipolar transistor is provided in which the product of base-collector capacitance and collector resistance can be reduced through a layout optimization, which leads to an improvement of the critical transistor parameters. The bipolar transistor has an emitter formed from a plurality of emitter elements, a plurality of base contacts and a plurality of collector contacts, these elements being provided in a specific arrangement with respect to one another for the formation of the transistor layout. The invention provides for the emitter to have at least one closed emitter configuration, the at least one emitter configuration bounding at least one emitter inner space, which can in turn be divided into a plurality of partial spaces. At least one of the base contacts is arranged in the emitter inner space, while at least one other base contact and the collector contacts are arranged outside the emitter configuration.

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and discrete deposits of gas absorbing or contaminant removing material on the base by a variety of techniques and a layer for temporary protection of the contaminant removing material on top of the contaminant removing material. Passages are created in the layer which expose the contaminant removing material to atmosphere. The device may be used as a covering for the microdevice as well.

Abstract: A semiconductor device comprises a package; one or a plurality of chips sealed in the package; and leads having inner parts electrically connected to the chip or the chips in the package, and outer parts extending outside the package. The package has an upper elevated part having a top surface, and terraced surfaces formed at a level below a level of the top surface. The leads are provided with joining parts to which leads included in another semiconductor device to be put on top of the package are to be bonded, respectively, on the terraced surface. The joining parts of the leads have a width greater than a width of other parts of the leads.

Abstract: A semiconductor device comprises a semiconductor chip. The semiconductor chip has an internal active region, an external active region, and a plurality of electrodes for electrically connecting the internal active region and the external active region to outside thereof, respectively. The semiconductor device also comprises a boarding portion that carries the semiconductor chip, a plurality of external electrode terminals for electrical connection to an external device, a plurality of connecting wires each connecting the electrode of the semiconductor chip and the external electrode terminal; and a mold resin that seals the semiconductor chip, the boarding portion and the connecting wires. The electrodes are disposed around the internal active region, and the external active region is disposed outside the electrodes.

Abstract: A semiconductor device includes a semiconductor die having patterned circuitry, a plurality of terminals coupled to the die, and an indication providing signal noise information of at least one of the terminals.

Abstract: A semiconductor device includes a housing, which is formed of a polyamide-series thermoplastic resin, and semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The package has a modified face that is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the packages in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance.

Abstract: A method for rewiring contact pads in the wafer-level package is inventively provided. In order to be able to make the terminals of the characterization pads available for testing in a wafer-level package without these terminals being available later to the end user, the invention provides that the rewiring line is led via the scribe line of the wafer.

Abstract: A semiconductor memory card is disclosed which achieves augmentation in design property, promotion of understanding and augmentation in identification facility of the type thereof. A memory card housing is entirely or partially transparent or translucent so that a circuit board, a memory chip and so forth in the inside thereof can be visually observed from the outside therethrough. Or, the card housing is partially opaque or is colored at the transparent or translucent portion thereof. Or else, the card housings of different types of memory cards are formed as different ones of transparent, translucent and opaque housings from each other.

Abstract: First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode is electrically connected only to the second electrode disposed on the back at position corresponding to the (N−1)-th chip select electrode, and the plurality of chip select electrodes are sporadically disposed in the first electrodes.

Abstract: A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively. The wiring layer and the protective film are formed so as to establish a relationship of t1<t2. An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65×10−6/°C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.

Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.

Abstract: A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally from a single edge of the lead frame. The lead fingers of each layer may extend in substantially the same direction. The electrically conductive buses of the two or more lead frame layers are at least partially superimposed with respect to one another. An insulator element is disposed between at least portions of the superimposed regions of the buses. One of the buses is connectable to a power supply source (VCC), while the other is connectable to a power supply ground (VSS). Thus, the mutually superimposed regions of the buses form a decoupling capacitor. Lead fingers of one of the layers may be arranged in groups which flank the remainder of the lead fingers so that they are not interleaved therewith.

Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package.

Abstract: A semiconductor device of a surface-mounting type having a mount surface to be joined with a mounting substrate includes a lead frame (4), semiconductor chip (2), and a resin (12) covering said the semiconductor chip. A mounting surface of an electrode terminal extracted from the semiconductor chip via the lead frame and surfaces of electrodes (20A, 20B) formed in the semiconductor chip are exposed to the mount surface to be substantially flush with the plane of the mount surface.

Abstract: Semiconductor-based devices, and methods for making the devices, involve a first device that includes a buried channel layer, a dielectric layer, and a compositionally graded spacer layer. The spacer layer includes a first material and a second material, and is located between the buried channel layer and the dielectric layer. A second device includes a buried channel layer, a relaxed surface layer, and a spacer layer located between the buried channel layer and the relaxed surface layer. The spacer layer has a composition that is different from a composition of the relaxed layer. The spacer layer and the relaxed surface layer each have bandgap offsets relative to the buried channel layer to reduce a parasitic channel conduction. A substrate for fabrication of devices, and methods for making the substrate, involves a substrate that includes a first layer, such as a silicon wafer, a substantially uniform second layer, and a graded-composition third layer.

Abstract: Electronic component, in particular a chip, which can be electrically bonded by means of a plurality of contacts provided on the component to mating contacts provided on a carrier, each contact (9) having a raised elastic base (3) of a conductive material which is connected to a lead (7) on the component side, and to which there is applied on the upper side a metallic cap-like contact covering (6), only partially covering the base (3).

Abstract: A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.

Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.

Abstract: A semiconductor wafer has: first semiconductor chips including a side of the semiconductor wafer; second semiconductor chips formed in an area surrounded by the first semiconductor chips, each of the second semiconductor chips having an integrated circuit and pads electrically connected to the integrated circuit; first bumps formed over each of the first semiconductor chips, at least part of each of the first bumps being formed in a columnar shape; and second bumps formed over the pads, respectively, at least part of each of the second bumps being formed in a columnar shape.

Abstract: A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10, and an interlayer dielectric layer 20 that covers the wiring layers 12. The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10, and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22, and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.

Abstract: A semiconductor device includes a substrate; a metal layer formed on the substrate; an insulating layer, which is formed on the metal layer and is provided with a via-hole through it; and a bonding pad formed above the via-hole. The bonding pad comprises an inner portion arranged in the via-hole and an outer portion arranged above the via-hole. The boding pad is made of a conductive resin having a shock absorbing characteristic.

Abstract: A semiconductor device includes a SAW device chip. The SAW device chip is provided on a passive element chip in which a passive element circuit including a transmission line is formed on a semi-insulating compound substrate having one surface set to have a ground potential electrode. In the semiconductor device, even when the width of the transmission line is increased, a high characteristic impedance can be maintained by increasing the thickness of the substrate. This can reduce the resistance of the transmission line and can facilitate matching with the SAW device.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: A solder bump structure and a method for forming the same are disclosed. Over a contact pad a first and a second metal film are deposited, wherein the second metal film is patterned prior to the deposition of a solder bump material such that an opening isolates an inner region of the second metal film from an outer region of the second metal film. The solder material deposited on the inner region and, at least partially, in the opening serves as an etch stop for a subsequent removal of the outer region.

Abstract: A thick film circuit connection epoxy is provided for protecting connections of dissimilar metals in a thick film substrate from the effects of oxidation. In the fabrication of hybrid integrated circuits, aluminum leads on the integrated circuit die are connected to gold conductors on the thick film substrate by means of an ultrasonic weld. The present invention comprises disposing a silver-filled thermoplastic epoxy around the weld between the aluminum wire and the gold conductor. Physical and electrical integrity of the connection between the aluminum wire and the gold conductor is thus maintained, even if the weld fails due to oxidation at elevated operating temperatures.

Abstract: To minimize the area of a chip-size package provided with balls, an equilateral triangle defined by pitches between balls is used as a basic shape, and a chip is formed into a shape in which the equilateral triangles are arranged side by side.

Abstract: The resin sealing apparatus includes a mold that has a main cavity into which a portion of a semiconductor device to be sealed with a resin is disposed. Furthermore, an external-shape regulating member is detachably accommodated in the main cavity of the mold to form a new cavity inside the main cavity.

Abstract: In the manufacture of a semiconductor device by adopting a block molding method wherein a semiconductor chip is fixed onto a wiring substrate through an adhesive, the occurrence of a defect caused by flowing-out of the adhesive is to be prevented. The semiconductor device according to the present invention comprises a wiring substrate, the wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film, a semiconductor chip fixed through an adhesive onto the insulating film formed on the main surface of the wiring substrate, conductive wires for connecting the electrodes on the main surface of the wiring substrate and electrodes on the semiconductor chip with each other, and a seal member, i.e.

Abstract: Described is a semiconductor device comprising a plurality of inner leads each made of copper or an alloy thereof; a heat sink made of copper or an alloy thereof, bonded to one end of each of a plurality of inner leads via an insulating adhesive layer and having a semiconductor element mounted on the heat sink via a metal wire; a plurality of metal wires each electrically connecting the semiconductor element and each of the plurality of inner leads; an encapsulating resin encapsulating the semiconductor element and the plurality of metal wires; and a plurality of outer leads protruded outside of the encapsulating resin and bent in the gullwing form. The encapsulating resin has been added with an additive forming a compound with an ionic impurity so that water at the peeling portion becomes near neutral, which prevents reaction and easy elution of copper, thereby preventing Cu migration.

Abstract: A mark configuration is provided for the orientation and/or determination of the relative position of a substrate and/or of layers on the substrate during a lithographic exposure, in particular for the case of a wafer during the fabrication of DRAMs. At least one part of a mark is disposed above a patterned background for the purpose of increasing a difference in contrast between the mark and the substrate. A wafer can also be manufactured with such a mark configuration. A method for fabricating the mark configuration is also described. An efficient and simple orientation of layers and/or of the substrate is thus made possible.

Abstract: A carburetor arrangement for an internal combustion engine including a two-stroke engine in a portable handheld work apparatus includes an intake channel section (2) which is formed in the carburetor housing (34). A throttle flap (3) is arranged in the intake channel section and is rotatably held by a throttle flap shaft (4). Fuel-conducting channels open into the intake channel section (2) in the region of the throttle flap. A choke flap (5) is mounted upstream of the throttle flap (3) in the intake channel section (2). The choke flap (5) is held by a choke shaft (6) so as to be rotatable. The throttle flap (3) is displaced in a closing direction from an opening position into a closed position and in an opening direction from the closed position into the open position. The same applies to the choke flap (5). The choke flap (5) and the throttle flap (3) are mechanically coupled. The choke shaft (6) is actuable by an operator-controlled element.

Abstract: A method for casting an ophthalmic lens having a toric surface includes the step of providing a casting cell that includes a conventional front mold, a novel gasket, and a novel toric back mold. An annular carrier ring is integrally formed with or attached to the toric back mold. The gasket has a first annular flat step against which the front mold squarely abuts and a second annular flat step against which the annular carrier ring squarely abuts. The gasket includes no toric annular seat against which the front surface of a toric back mold abuts. This eliminates the need for a lens maker to maintain a large inventory of toric back molds and gaskets. The square seating enhances the sealing capability of the mold, reduces leaks, and produces lenses having fewer bubbles and flash on the edge of the lens.

Abstract: A method for coating hydrogel and silicone hydrogel articles, and articles made by the method, are provided in which the coating is first applied to the molding surface in which an article-forming material will be cured to form the article. The method permits the thickness and uniformity of the coating to be more easily controlled than in known coating methods.

Abstract: An adjustable mold includes a distortable boundary, a flexible membrane, and a pressurizer, and method of use thereof. Pressure is applied to the flexible membrane, which causes the membrane to distort over the boundary. The shape of the boundary and the distortion of the flexible membrane control the optical characteristics of a lens resulting from the application and curing of a molding composition placed on the flexible membrane or to cast other items having variable shapes determined in part by the flexible membrane. In addition, a mold edge is used to allow casting in predetermined shapes, reducing need for grinding or edging. Visual and emission device calibration features used in conjunction with calibration reference images allow uniform selective distortion of the flexible membrane.

Abstract: The invention refers to a method of controlling the porosity of porous spherical particles produced from a polysaccharide dissolved in a solvent, in which it can be gelled. The polysaccharide solution is finely divided by mechanical means into spherical droplets which are allowed to pass through a humid atmosphere and transferred to a capturing medium while controlling the temperature and humidity of humid atmosphere.

Abstract: The invention relates to a retaining device (26), in particular on an extruder (2), for several die plates (27) which can be arranged immediately one after the other in the extrusion direction (6) to form an extrusion die (28) with an inlet region (29) and an outlet region (30). At least two tension elements (37) are provided spaced at a distance apart from one another perpendicular to the extrusion direction (6), which can co-operate with the die plates (27) respectively in the region of opposing first side ends (34) which they span. At least one holding element (40) projects, in an end region (39) of the tension element (37) which may be directed towards the outlet region (30), into the cross-sectional surface bounded by the side ends (34) of the die plates (27) disposed one after the other and engages round these side ends (34).

Abstract: To provide a method for producing a ceramic porous material which has a high strength, though it has a high porosity, and which is excellent in permeability without dust generation. In a ceramic porous material having a three-dimensional mesh-like skeleton structure with a large number of substantially spherical adjacent cells communicating with each other via communication holes, the crystal particle size at the rim of each communication hole in the skeleton structure is provided substantially equal to the crystal particle size in the other parts.

Abstract: A process for making a fluid processing module is provided wherein a plurality of filtration elements is alternated with a fluid porous layer to form a stack. The filtration elements comprise a membrane sheet having a thermoplastic element bonded to a portion of an edge of the membrane. An opening is provided either through the membrane or through the thermoplastic element. A portion of the thermoplastic element extends into the opening and can be sealed to an adjacent positioned thermoplastic element to seal the porous sheet positioned between adjacently positioned membranes from fluid communication with the opening. Sealing can be effected by extending a heating element through the opening of the stack to effect simultaneous sealing of a plurality of thermoplastic elements.

Abstract: Methods are taught for manufacturing a press molded article (1) that comprises a profiled substrate layer (10) and a foamed layer (20). A substrate material (12) may be press molded with a foamable material (22) under pressure in order to join or attach the foamable material to the substrate material. In addition, a profile may be imparted to the substrate material during the press molding step, thereby forming the profiled substrate layer. After the press molding step has been completed, the foamable material is foamed and expanded, to thereby form the foamed layer. A skin material (32) optionally may be applied to the foamable layer before the press molding step. Optionally, embossed patterns may be imparted to the skin material during the press molding step, thereby forming an embossed skin layer (30) that is attached to the foamed layer.

Abstract: Thermoplastic elastomeric compositions and processes for preparing the compositions comprising a blend of polypropylene, styrene-ethylene butylene-styrene copolymer, ethylene-propylene-diene monomer elastomer, linear low density polyethylene, peroxide crosslinking agent and a crosslinking coagent. The peroxide crosslinking agent and crosslinking coagent provide a crosslinking system. The compositions improve melt strength and increase resistance to flow and tear. The composition may further comprise mineral oil, antioxidant, colorant, a processing aid and stabilizer and mixtures thereof. The processes for preparing thermoplastic elastomeric compositions are particularly useful in microcellular injection molding to form articles with improved surface characteristics.

Abstract: A polyester blended yarn giving a woven or knitted fabric exhibiting a swollen touch and a high grade texture is stably obtained by melt-spinning a polyester composition A comprising a substrate polymer comprising a polyester and 0.5 to 5.0 percent by weight of a polymer P, and the substrate polymer from an identical spinneret or different spinnerets to obtain the filament group A comprising the polyester composition A and the filament group B comprising the substrate polymer, blowing cooling air on the filament groups B and A at a speed of 0.20 to 0.80 m/sec and at a speed of not less than 1.1 times said speed, respectively, to once separately cool and solidify the filament groups B and A, doubling the cooled filament groups, and then taking off the obtained doubled yarn at a speed of not less than 2,500 m/min.

Abstract: A method for producing an anisotropic magnet with high energy product through extrusion and, more specifically, by placing a particle charge of a composition from the which magnet is to be produced in a noncircular container, heating the container and particle charge and extruding the container and particle charge through a noncircular extrusion die in such a manner that one of the cross-sectional axes or dimension of the container and particle charge is held substantially constant during the extrusion to compact the particle charge to substantially full density by mechanical deformation produced during the extrusion to achieve a magnet with anisotropic magnetic properties along the axes or dimension thereof and, more specifically, a high energy product along the transverse of the smallest cross-sectional dimension of the extruded magnet.

Abstract: A process is disclosed in which coarse silica, calcium oxides and magnesium oxides are treated in a ball mill together with grinding aids and cold-strength binders. This material is then agglomerated with water to produce a product that reacts at elevated temperatures, e.g. in a fluidized bed reactor, to produce synthetic silicates.