Abstract: The present invention provides a method of forming an electroluminescent circuit by screen printing. The method according to the invention includes screen printing a rear electrode pattern on a substrate, which is preferably a polyester sheet, screen printing a dielectric layer over the rear electrode pattern, screen printing a front electrode pattern on the dielectric layer, and screen printing a phosphor layer over the front electrode layer. The rear electrode pattern preferably includes a solid layer disposed upon the substrate and the front electrode pattern preferably includes a plurality of opaque lines separated by spaces. In an alternative embodiment, the method according to the invention includes screen printing the phosphor layer on the substrate, screen printing the front electrode pattern on the phosphor layer, screen printing the dielectric layer over the front electrode pattern, and screen printing the rear electrode pattern over the dielectric layer.

Abstract: The method for fabricating a semiconductor device of this invention includes the step of: forming a first compound semiconductor layer by crystal growth on a surface of a semiconductor substrate which includes a plurality of crystal planes having different orientations exposed due to a concave portion and/or a convex portion formed on the semiconductor substrate, the first compound semiconductor layer containing nitrogen and a V group element other than nitrogen.

Abstract: An infrared sensor including a substrate, a plurality of infrared detection pixels arrayed on a substrate with each of the infrared detection pixels including an infrared absorption portion formed over the substrate and configured to absorb infrared radiation, a thermoelectric converter portion formed over the substrate and configured to convert a temperature change in the infrared absorption portion into an electrical signal, and support structures configured to support the thermoelectric converter portion and the infrared absorption portion over the substrate via a separation space, the support structures having conductive interconnect layers configured to deliver the electrical signal from the thermoelectric converter portion to the substrate.

Abstract: A method of trimming for a semiconductor device comprising bolometers arranged in two-dimensional form corresponding to pixels for converting incoming infrared rays into electrical signals includes vertical switches, a vertical shift register, horizontal switches, and a horizontal shift register as means for selecting an arbitrary pixel. The semiconductor device is configured to allow an overcurrent to be supplied to a bolometer in a pixel selected by those means.

Abstract: The present invention is directed to semiconductor films and a process for their preparation. In accordance with the process of the present invention, semiconductor organic material is blended with a multi-component solvent blend and the blend is deposited on a receiving material to provide a continuous highly ordered film having greater periodicity than films produced with a single solvent/semiconducting material blend under similar processing conditions.

Abstract: A method for electronically connecting a semiconductor device comprising a substrate having a backside surface and a top surface on which is formed active elements, to an electronic circuit board having at least two electrical contacts connected to sources of different potentials for communicating at least two different signals; the method comprising forming at least two through-wafer via holes on the backside surface of the semiconductor substrate beneath each of the active regions extending therethrough to the top surface; forming a conductive layer of material within each of the via holes extending therethrough, each of the conductive layers formed within the corresponding via holes being electrically separated from one another; the at least two electrical contacts on the circuit board congruently aligned with corresponding conductive layers and associated via holes; and attaching the circuit board to the semiconductor substrate at each of the corresponding electrical contacts and conductive layers so as t

Abstract: A method for forming terminations on the opposite ends of a chip component includes placing a chip component in a cavity with one end of the chip component exposed. Termination conductive material is then deposited on the exposed end of the chip component and the component is removed from the cavity and reversed. Termination material is then deposited on the other exposed end. One modification of the invention includes extending the chip components completely through holes in a plate so that the opposite ends of the chip component are exposed. The termination material is then placed on the opposite ends of the chip component.

Abstract: A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e. solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.

Abstract: A system for dispensing a viscous material onto a substrate which includes a dispensing element, a viscous material reservoir and a metering device coupled between the reservoir and the dispensing element for metering a variable amount of a viscous material through the dispensing element. The dispensing element and metering device can be moved by a positioner along a predetermined pattern adjacent a surface of a substrate. A weigh scale located adjacent the substrate receives a metered amount of the viscous material and produces signals representative of a variable weight of the material dispensed during a predetermined time interval. A controller adjusts a speed of movement of the positioner along the predetermined pattern to cause the dispensing element to dispense a desired amount of material based on a calculated flow rate.

Abstract: A method of joining first and second substrates through a solder element interconnect, the method including the steps of forming solder elements, such as solder balls, in a first array on a first substrate, forming pads of solder paste in a second array on a second substrate wherein the first and second arrays are mirror images of one another, establishing a standoff element on one of the first or second substrates, assembling the first and second substrates such that each of the solder elements on the first substrate are embedded in each of the solder paste pads and the standoff element is interposed between the first and second substrates, heating the first and second substrates at a preferred temperature to cause melting of the solder elements and the solder pads into single solder elements, wherein the standoff controls the separation distance between the first and second substrates.

Abstract: A resin-sealed semiconductor device according to this invention is an LOC type semiconductor device comprising a semiconductor chip having a circuit surface on which an electrode is formed; a lead which is arranged in such a manner that the distal end of the lead overlaps the semiconductor chip, and which is electrically connected to each electrode; a lead fixing resin layer interposed between the semiconductor chip and the lead to fix them; and a sealing resin layer coated to cover the semiconductor chip and the lead. The diameter of filler contained in the lead fixing resin layer is about 1/10 to 1/5 the diameter of filler contained in the sealing resin layer, and is about 1/10 a gap between the lead and the semiconductor chip.

Abstract: A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are electrically connected to the nodes. A multimedia chip has an active surface and a corresponding back surface, and a plurality of bonding pads are formed on the active surface of the multimedia chip. The back surface of the multimedia chip is adhered on the die pad of the substrate unit. A molding compound encapsulates the multimedia chip, the first surface of the substrate unit, and the conductive wires, and exposes the second surface of the substrate unit and the external nodes.

Abstract: A process for producing a semiconductor package and a structure thereof are provided in that yield per unit wafer is increased, yield and reliability are improved, and the number of production steps are decreased. The process includes the steps of a step of forming a bump on a semiconductor wafer for respective semiconductor chip constituting a semiconductor package; a step of dicing a substrate, which has been prepared, into a substrate piece corresponding to the respective semiconductor chip; a step of die-boding the substrate piece, which has been diced, on the semiconductor wafer with making the bump to correspond to the respective semiconductor chip; a step of sealing a gap between the semiconductor wafer and the substrate piece, which have been die-bonded, with a resin; and a step of dicing the semiconductor wafer and the substrate piece, which have been sealed with the resin, into the respective semiconductor package.

Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a barrier layer is provided to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.

Abstract: A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate pre-defined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semi-conductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package.

Abstract: A lead frame is configured with conductor leads, a dam bar and an extension between the conductor leads. The extension projects from the dam bar toward a central region of the lead frame. An electronic component is mounted on the lead frame and is brought into electrical contact with inner leads. The component and the lead frame are encased by injection molding. The extension is then isolated from the rest of the lead frame and is removed from the housing body. Thus a separating face is produced between the housing body and the extension. The separating face is used as a reference when positioning the component in a test socket.

Abstract: The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material. In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material.

Abstract: A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like.

Abstract: A semiconductor device includes a conductive semiconductor substrate laminated or bonded on a conductive support substrate through a first insulating film, a separation trench which separates a device formation region where at least a desired element is formed, from a region of the semiconductor substrate, a separation trench, and a substrate contact region where the semiconductor substrate is not present. The semiconductor device further includes a second insulating film which fills the separation trench and covers a surface of the substrate contact region, an external connection electrode formed above the semiconductor substrate, and a support substrate connecting section which passes through the first insulating film and the second insulating film in the substrate contact region to connect the external connection electrode and the support substrate.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film is formed in this step. At this time, gettering of the nickel element into the thermal oxide film takes place. Then, the thermal oxide film is removed. Thereby, a crystal silicon film having low concentration of the metal element and a high crystalinity can be obtained.

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition.

Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract: A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.

Abstract: In one illustrative embodiment, the method comprises forming a sacrificial layer of material above a substrate comprised of silicon, performing a wet etching process to remove the sacrificial layer, implanting fluorine atoms into selected portions of the substrate after the sacrificial layer is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers above the substrate, the gate insulation layers formed above the fluorine implanted selected portions of the substrate having a thickness that is greater than a thickness of the gate insulation layers formed above portions of the substrate not implanted with fluorine.

Abstract: The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si1-xGex, x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.

Abstract: A method of fabricating a polysilicon thin film transistor on a substrate includes forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode including the substrate, sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the gate insulating layer, forming a catalytic metal layer on the doped amorphous silicon layer by an ion doping method, simultaneously crystallizing the doped amorphous silicon layer and the intrinsic amorphous silicon layer so as to form a doped polysilicon layer and an intrinsic polysilicon layer, respectively, forming a source electrode and a drain electrode on the doped polysilicon layer, and removing a portion of the doped polysilicon layer between the source and drain electrodes.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array and a peripheral region adjacent the array containing related logic devices. Structure planarization is enhanced by utilizing a pattern of dummy material in the peripheral region. The control gates of the memory cells and the logic gates of the logic devices are formed separately so each can be independently optimized.

Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Abstract: A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating film and gate electrode stacked on a channel forming region of a semiconductor provided on the surface of a substrate and planarly dispersed charge storing means such as carrier traps in a nitride film or near the interface with the top insulating film, provided in the gate insulating film, the gate insulating film including an FN tunnel film having a dielectric constant larger than that of a silicon oxide film and exhibiting an FN electroconductivity, whereby the thickness of the gate insulating film, converted to that of a silicon oxide film, can be reduced and the voltage can be reduced.

Abstract: A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions.

Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.

Abstract: A plurality of active pixel sensors are formed on the surface of a semiconductor wafer. The semiconductor wafer comprises a P-type substrate, an active pixel sensor region and a periphery circuit region. A first active pixel sensor block mask (APSB mask) is formed to cover the active pixel sensor region, then at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask is formed. A second APSB mask and at least one N-well mask are formed to cover the active pixel sensor region and the region outside the P-well region. At least one P-well on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask is formed. Finally, at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.

Abstract: Disclosed are a capacitor for semiconductor device capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. According to the present invention. A lower electrode is formed on a semiconductor substrate. The lower electrode is surface-treated so as to prevent generation of a natural oxide layer. An amorphous TaON layer is, as a dielectric layer, deposited on the upper part of the lower electrode. Afterwards, the amorphous TaON layer is thermal-treated in a range of maintaining its amorphous state. Next, an upper electrode is formed on the upper part of the TaON layer.

Abstract: A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.

Abstract: The disclosure relates to a method for fabricating a capacitor that prevents a rise in the production cost and complexity of production processes caused by performing deposition and subsequent treatment thereof whenever a layer is formed. The disclosure provides a method for fabricating a capacitor, including the steps of: forming a Ti1-xZrxN layer on a substrate, wherein x is in the range of 0 to 0.5, inclusive; forming an electrode layer on the Ti1-xZrxN layer; and forming a ZrO2 layer on an interface between the electrode layer and the Ti1-xZrxN layer by performing a thermal treatment in an atmosphere containing oxygen gas, whereby a capacitor having a bottom electrode formed with the Ti1-xZrxN layer, a dielectric layer formed with the ZrO2 layer, and a top electrode formed with the electrode layer is fabricated.

Abstract: In a DRAM having information storage capacitative elements over their corresponding bit lines BL, wiring grooves are defined in an insulating film for wire or interconnection formation, which are formed over gate electrode serving as word lines of the DRAM. Sidewall spacers are formed on their corresponding side walls of the wiring grooves. Each bit line BL and a first layer interconnection composed of a tungsten film are formed so as to be embedded in the wiring grooves whose intervals are respectively narrowed by the sidewall spacers. The bit lines BL are respectively connected to a semiconductor substrate through connecting plugs. The bit lines BL and the connecting plugs are respectively connected to one another at the bottoms of the wiring grooves.

Abstract: The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with one another to forming a locally delimited insulating layer in the substrate. In this way, trench capacitors implemented as buried circuit elements can be manufactured with a structure size of less than 100 nm in a simple and cost-effective manner.

Abstract: A semiconductor device has such a configuration that a contact hole is formed in a fourth inter-layer insulator film which covers an upper electrode of a capacitor, to expose part of the upper electrode; and below the contact hole, a trench covered by a capacitive insulator film formed in a trench is formed larger than the contact hole in width, to have therein a polycrystalline silicon film which constitutes the upper electrode.

Abstract: A method of fabricating a bipolar transistor. The method comprising: forming an emitter opening in a dielectric layer to expose a surface of a base layer; performing a clean of the exposed surface, the clean removing any oxide present on the surface and passivating the surface to inhibit oxide growth; and forming an emitter layer on the surface after the performing a clean.

Abstract: A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Abstract: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

Abstract: A new method is provides for the creation of a hardmask over a layer of polysilicon for the etching of floating gate for split-gate flash memory devices. A layer of gate oxide is created over the surface of a substrate, a layer of polysilicon is deposited over the surface of the layer of gate oxide. In a first embodiment of the invention, a layer of native oxide is grown over the surface of the layer of gate material, this layer of gate oxide is used to enhance oxidation of exposed portions of the layer of gate material. In a second embodiment of the invention, enhanced oxidation of exposed portions of the layer of polysilicon is achieved by modifying the conventional sequence of the oxidation process. This latter modification is realized by modifying the forward motion of the substrates through the oxidation furnace or by modifying the sequence in which the substrates move through the oxidation furnace.

Abstract: A semiconductor device and a method of manufacturing the same are provided which are novel and fully improved and are capable of lowering satisfactorily a high-frequency resistance or direct current resistance in a signal line. The semiconductor device is composed of a semiconductor substrate on which predetermined circuit devices are mounted, an insulating film formed on the substrate in a manner that it covers the circuit devices and a conductive path formed on the insulating film to electrically connect the circuit devices. A concave trench is formed in a predetermined position on the semiconductor substrate and the conductive path is formed at a bottom of the concave trench in a manner that it extends along the concave trench, with interlayer dielectrics interposed between conductive layers constituting the conductive path.

Abstract: A method for fabricating a MOSFET includes a step of forming an isolation layer on an isolation region of a substrate, to thereby define an active region ion implanting As and P into the active region, and a step of forming a gate on the active region. An ion implanting step of low-concentration impurity using the gate as a mask is performed to form a low-concentration ion-implanted region in a predetermined portion of the substrate which is placed on the right and left sides of the gate. A sidewall spacer on the sides of the gate is formed, and thereafter, and ion implanting high-concentration impurity into the substrate is performed.

Abstract: In the method for fabricating an element isolating film of a semiconductor device, a trench is formed in the semiconductor substrate, and a side wall spacer is formed at a side wall of the trench. A silicon layer is formed on a bottom surface of the trench, and a groove portion is formed in the bottom surface of the trench by removing the side wall spacer. An element isolating film is then formed by filling an oxide film in the trench.

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.

Abstract: A substrate processing apparatus includes a heater which heats a substrate through a susceptor on which the substrate is placed. The heater is divided into a plurality of zone heaters, and a reflecting member is interposed between at least two of the plurality of zone heaters.

Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.