Patents Issued in May 6, 2003
  • Patent number: 6559053
    Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Zhongze Wang, Li Li, Yongjun Jeff Hu
  • Patent number: 6559054
    Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Moore, Trung Tri Doan
  • Patent number: 6559055
    Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: May 6, 2003
    Assignee: Mosel Vitelic, Inc.
    Inventors: Hsing Ti Tuan, Chung Wai Leung
  • Patent number: 6559056
    Abstract: The object of the present invention is to provide an aqueous dispersion for chemical mechanical polishing which can be polished working film for semiconductor devices and which is useful for STI. The aqueous dispersion for chemical mechanical polishing of the invention is characterized by comprising an inorganic abrasive such as silica, ceria and the like, and organic particles composed of a resin having anionic group such as carboxyl group into the molecular chains. The removal rate for silicon oxide film is at least 5 times, particularly 10 times the removal rate for silicon nitride film. The aqueous dispersion may also contain an anionic surfactant such as potassium dodecylbenzene sulfonate and the like. And a base may also be included in the aqueous dispersion for adjustment og the pH to further enhance the dispersability, removal rate and selectivity.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: May 6, 2003
    Assignee: JSR Corporation
    Inventors: Masayuki Hattori, Hitoshi Kishimoto, Nobuo Kawahashi
  • Patent number: 6559057
    Abstract: Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, John K. Zahurak
  • Patent number: 6559058
    Abstract: One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 6, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6559059
    Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: May 6, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Sun-Chieh Chien, Chien-Li Kuo
  • Patent number: 6559060
    Abstract: A process for the structuring of a substrate with structures in the micrometer to nanometer range that does not involve the provision of gaseous fluoro-organic compounds is described. The process is carried out by means of reactive ion etching using a mask arranged on the substrate and a plasma as well as fluorine-containing organic compounds, which fluorine-containing organic compound(s) is/are provided in the form of solid polymers. A process for the etching of a coating on a substrate or the surface of a substrate is also described.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 6, 2003
    Assignee: Carl-Zeiss-Stiftung
    Inventors: Uwe W. Hamm, Markus Kasparek, Oliver Jacobs
  • Patent number: 6559061
    Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 6, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Imran Hashim, Tony Chiang, Barry Chin
  • Patent number: 6559062
    Abstract: A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: May 6, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Stephen Ward Downey, Allen Yen, Thomas Michael Wolf, Paul B. Murphey
  • Patent number: 6559063
    Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: May 6, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akiyuki Minami, Satoshi Machida
  • Patent number: 6559064
    Abstract: For removing a photoresist formed on a semiconductor wafer by using an ozone-dissolved water, until just before a low temperature ozone-dissolved water generated by an ozone-dissolved water generator is discharged from a discharge nozzle onto a semiconductor wafer placed on a stage, the semiconductor wafer is heated to a predetermined temperature which is higher than ordinary temperatures. When the low temperature ozone-dissolved water having a high concentration of ozone is discharged onto the semiconductor wafer, the temperature of the ozone-dissolved water elevates upon the instant. Thus, the photoresist formed on the semiconductor wafer can be removed by a high temperature, high ozone concentration, ozone-dissolved water.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: May 6, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Yuji Shimizu
  • Patent number: 6559065
    Abstract: In order to provide a vapor deposition method for forming an organic thin film, which is advantageous in that a deposition rate can be easily controlled and deposition can be conducted with stable high controllability, there is prepared a crucible which is provided with an opening portion at an upper portion of the body, and a projection in a cone shape on an inner bottom surface of the crucible so as to be opposite to the opening portion. When the crucible is irradiated with an infrared light from the bottom side of the crucible, the light in one region among the infrared light transmits the bottom of the crucible and is then radiated to an organic material contained in the crucible. Therefore, the organic material is heated and vaporized at a desired temperature in the range of about 100 to 400° C. by controlling the irradiation dose of the infrared light.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: May 6, 2003
    Assignee: Sony Corporation
    Inventor: Toshitaka Kawashima
  • Patent number: 6559066
    Abstract: A switching element is formed by sequentially depositing on an insulating substrate a gate electrode, a gate insulating film made of an inorganic insulating film, a semiconductor layer, a channel protecting layer, an n+Si layer that will form a source electrode and a drain electrode. Next, a metal layer and a transparent conductive film are formed on edges of the source electrode and the drain electrode. The insulating substrate on which the above films have been deposited is cleaned with vacuum ultraviolet light, before further depositing an interlayer insulating film and a pixel electrode. A substrate for use in a display element obtained in this manner exhibits an excellent adhesion strength between the film processed with vacuum ultraviolet light and a film adjacent to the film processed with vacuum ultraviolet light.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: May 6, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shin-ichi Terashita, Shinji Yamagishi
  • Patent number: 6559067
    Abstract: An antireflection coating (ARC) polymer layer is patterned by DUV (deep ultraviolet) lithography followed by an ARC open etching step and subsequent etching of the metal layer. Low resist consumption and hence steeper resist sidewalls are achieved by virtue of the ARC polymer intermediate layer being etched with a CF4 ARC open process with high selectivity with respect to the photoresist. The gas flows are set to the following ranges: CF4 35-45 sccm, CHF3 17-23 sccm, O2 5-7 sccm and Ar 80-120 sccm.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: May 6, 2003
    Assignee: Infineon Technologies AG
    Inventors: Matthias Lehr, Gregoire Grandremy
  • Patent number: 6559068
    Abstract: A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 6, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Dev Alok, Emil Arnold, Richard Egloff, Satyendranath Mukherjee
  • Patent number: 6559069
    Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: May 6, 2003
    Assignee: Infineon Technologies AG
    Inventors: Matthias Goldbach, Albert Birner
  • Patent number: 6559070
    Abstract: The present invention generally provides a process and an apparatus for depositing low dielectric constant films on a substrate. The low dielectric constant films are phosphorus doped mesoporous oxide films formed by depositing and curing a phosphorus containing sol-gel precursor to form an oxide film having interconnecting pores of uniform diameter, and then annealing the film in an inert gas atmosphere or exposing the film to an oxidizing atmosphere containing a reactive oxygen species to form a phosphorus doped mesoporous oxide film.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: May 6, 2003
    Assignee: Applied Materials, Inc.
    Inventor: Robert P. Mandal
  • Patent number: 6559071
    Abstract: A process for forming a nanoporous silica dielectric coating on a substrate. A substrate containing a deposited film is suspended within a sealable hotplate, while remaining free of contact with the hotplate. The hotplate is sealed and an inert gas is flowed across the substrate. The hotplate is heated to a temperature of from about 350° C. or higher, and the substrate is forced to contact the heated hotplate. The substrate is heated for a time that sufficiently removes outgassing remnants from the resultant nanoporous dielectric coating.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: May 6, 2003
    Assignee: AlliedSignal Inc.
    Inventors: Teresa Ramos, Douglas M. Smith, James Drage, Rick Roberts
  • Patent number: 6559072
    Abstract: A develop process for reduced cycle time and reduced defects in the develop process for semiconductor/IC fabrication is shown. The use of a linear slit scan nozzle provides even distribution of a layer of develop material within an acceptable thickness and uniformity range such that a pre-wet step is not needed to spread the develop material evenly over the surface of a wafer. The use of a whip operation prior to rinsing with DI water significantly reduces develop defects.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventors: John T. Davlin, Greg Montanino
  • Patent number: 6559074
    Abstract: A silicon nitride layer is formed over transistor gates while the processing temperature is relatively high, typically at least 500° C., and the pressure is relatively high, typically at least 50 Torr, to obtain a relatively high rate of formation of the silicon nitride layer. Processing conditions are controlled so as to more uniformly form the silicon nitride layer. Generally, the ratio of the NH3 gas to the silicon-containing gas by volume is selected sufficiently high so that, should the surface have a low region between transistor gates which is less than 0.15 microns wide and have a height-to-width ratio of at least 1.0, as well as an entirely flat area of at least 5 microns by 5 microns, the layer forms at a rate of not more than 25% faster on the flat area than on a base of the low region.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 6, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Steven A. Chen, Xianzhi Tao, Shulin Wang, Lee Luo, Kegang Huang, Sang H. Ahn
  • Patent number: 6559075
    Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: May 6, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Kelly, Oliver Ambacher, Martin Stutzmann, Martin Brandt, Roman Dimitrov, Robert Handschuh
  • Patent number: 6559076
    Abstract: A method is disclosed for removal of free halogen from a semiconductor device insulating layer, in particular, a halogen-containing polymer insulating layer. The free halogen is removed by contacting the insulating material with hydrogen ions under conditions which generate gaseous hydrogen halide which is then removed. A semiconductor device containing such treated insulating materials is also disclosed. The invention is particularly useful in removing free fluorine from fluorinated polymer insulating layers.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6559077
    Abstract: A mesh structure is formed from a set of a warp strands and a set of intersecting weft strands. The warp strands are formed of a knitted synthetic material which shrinks when exposed to heat, and the weft strands pass through the weave of the warp strands at the nodes where the strands intersect. Heat is applied to the mesh structure to shrink the weave of the warp strands tightly around the weft strands at the nodes, thereby co-joining the weft and warp strands to form a high-strength mesh.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: May 6, 2003
    Assignee: Polytech Netting, L.P.
    Inventor: Donal Moore
  • Patent number: 6559078
    Abstract: A flame retardant suitable for use in mesh sheets comprising a polyolefin resin aqueous dispersion having a resin solid content of 25-75 wt %, 40 to 130 parts by weight of an ammonium polyphosphate compound based on 100 parts by weight of said polyolefin resin aqueous dispersion, and 60 to 150 parts by weight of a metal hydroxide based on 100 parts by weight of the solid content of said polyolefin resin aqueous dispersion.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 6, 2003
    Assignee: Kyowa Kabushiki Kaisha
    Inventors: Saiji Nozaki, Kuniaki Kamiya
  • Patent number: 6559079
    Abstract: A ballistic resistant pad having a first group of at least two successive overlying woven sheets constructed of high strength fibers. The warp and the weft for individual ones of the successive overlying woven sheets of the first group are substantially in alignment to one another. A second group of at least two successive overlying woven sheets constructed of high strength fibers is also provided. The warp and the weft for individual ones of the woven sheets of the second group are substantially in alignment to one another and are angularly displaced from the warp and the weft of the woven sheets of the first group.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 6, 2003
    Assignee: Second Chance Body Armor, Inc.
    Inventor: Thomas E. Bachner, Jr.
  • Patent number: 6559080
    Abstract: Dual glass fibers can be processed into coherent webs and felts by first blending the dual glass fibers with an equal or greater amount of uncrimped fibers. Optionally, other crimped fibers can be added without significant impact on processibility.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: May 6, 2003
    Assignee: Toray Industries, Inc.
    Inventor: Reginald Thomas Kruszewski
  • Patent number: 6559081
    Abstract: This invention relates to fibrous absorbent articles containing particles useful in the manufacture of disposable diapers, adult incontinence pads, sanitary napkins and the like, scrubbing pads, scouring pads and cleaning pads that contain a detergent or soap and the like, and pads that contain coffee, tea, and the like More particularly, the invention is directed to an absorbent articles having sealed lateral edges to contain loose fibers and particles within the structure. Additionally, this invention is related to airlaid methods to manufacture unitary absorbent products.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: May 6, 2003
    Assignee: BKI Holding Corporation
    Inventors: John P. Erspamer, Jeffrey S. Hurley, Brian E. Boehmer, Derrix Betts
  • Patent number: 6559082
    Abstract: The invention concerns a crack-free insulating refractory material made from a composition comprising 20-80% by weight of a ceramic matrix, 5-40% by weight of insulating microspheres, 0.5-15% by weight of one more binders, 5-20% by weight of a metal or a metal alloy able to melt during the preheating or the first minute of use and 0-25% by weight of water. The ceramic matrix is preferably comprised of vitreous and non-vitreous grains.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: May 6, 2003
    Assignee: Vesuvius Crucible Company
    Inventors: Cecile Desvignes, Gilbert Rancoule
  • Patent number: 6559083
    Abstract: The present invention provides a dielectric ceramic composition comprising a base material represented by the general formula: (x) Al2O3+(y) TiO2, where x and y are percentages of the total weight of the base material, with x being in the range of about 60 to about 96 and y being in the range of about 4 to about 40. Also provided is a first additive material comprising Nb2O5 and a second additive material comprising BaZrO3. In another embodiment the present invention provides a sintered dielectric ceramic composition comprising a base material represented by the general formula: (x) Al2O3+(y) TiO2, where x and y are percentages of the total weight of the base material, with x being in the range of about 60 to about 96 and y being in the range of about 4 to about 40. Also provided is a first additive material comprising Nb2O5 and a second additive material comprising BaZrO3.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: May 6, 2003
    Assignee: CTS Corporation
    Inventors: Jeffrey R. Jacquin, Randy E. Rose
  • Patent number: 6559084
    Abstract: A dielectric ceramic composition comprising a main component of BaTiO3, a first subcomponent including at least one compound selected from MgO, CaO, BaO, SrO and Cr2O3, a second subcomponent of (Ba, Ca)xSiO2+x (where, x=0.8 to 1.2), a third subcomponent including at least one compound selected from V2O5, MoO3, and WO3, and a fourth subcomponent including an oxide of R1 (where R1 is at least one element selected from Sc, Er, Tm, Yb, and Lu), a fifth subcomponent including an oxide of R2 (where R2 is at least one element selected from Y, Dy, Ho, Tb, Gb and Eu), wherein the ratios of the subcomponents to 100 moles of the main component of BaTiO3 are first subcomponent of 0.1 to 3 moles, second subcomponent of 2 to 10 moles, third subcomponent of 0.01 to 0.5 mole, fourth subcomponent of 0.5 to 7 moles, and fifth subcomponent of 2 to 9 moles (where the number of moles of the fourth and fifth subcomponents are respectively the ratio of R1 and R2 alone).
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: May 6, 2003
    Assignee: TDK Corporation
    Inventors: Yoshinori Fujikawa, Yoshihiro Terada, Shigeki Sato
  • Patent number: 6559085
    Abstract: A method for regeneration of a molybdenum-containing oxide fluidized bed catalyst which comprises impregnating a fluidized catalyst of a metal oxide containing molybdenum, bismuth and iron which has been deteriorated by being used for a reaction in production of acrylonitrile by ammoxidation of propylene, with a solution of a molybdenum compound and a solution of at least one compound containing at least one element selected from the group consisting of iron, chromium, lanthanum and cerium which are prepared separately or with a previously prepared mixed solution of the above compounds, drying the resulting catalyst and, then, firing the catalyst at a temperature of 500-700° C.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: May 6, 2003
    Assignee: Mitsubishi Rayon Co., Ltd.
    Inventors: Yutaka Sasaki, Kunio Mori, Yoshimi Nakamura, Akimitsu Morii
  • Patent number: 6559086
    Abstract: An exhaust-gas-purifying catalyst wherein a first zeolite loaded with a catalyst metal and a second zeolite unloaded with a catalyst metal are mixed. By actively adsorbing HC onto the second zeolite, it is possible to inhibit the catalyst metal loaded on the first zeolite from being poisoned by HC, and to sufficiently adsorb HC. Accordingly, since the HC adsorbing capability is improved, and since the HC poisoning of the catalyst metal is suppressed, the NOx purifying capability is enhanced and the durability is also upgraded.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: May 6, 2003
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroaki Takahashi, Toshihiro Takada, Saeko Kurachi
  • Patent number: 6559087
    Abstract: A method for the treatment of catalyst or catalyst support material in an apparatus in which the treatment is carried out continuously in such a way that the physical and/or chemical conditions change during entry of the catalyst or catalyst support material into the apparatus and/or during exit thereof from the apparatus and/or the catalyst or catalyst support material is transported in the apparatus through zones (5, 6, 7) having different physical and/or chemical conditions.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: May 6, 2003
    Assignee: Basell Polyolefins GmbH
    Inventors: Paulus De Lange, Rainer Karer, Philipp Rosendorfer, Kaspar Evertz, Wolfgang Micklitz, Hans-Jacob Feindt
  • Patent number: 6559088
    Abstract: Provided is a catalyst system for polymerization of monomer having at least one Ziegler-Natta polymerizable bond comprising: c) a supported Ziegler-Natta transition metal catalyst component comprising a Group 15 atom having two groups selected from the group consisting of alkyl and aryl, wherein the support is a magnesium halo dialkylamide; and d) an effective co-catalyst.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: May 6, 2003
    Assignee: Fina Technology, Inc.
    Inventors: Edwar Shoukri Shamshoum, Hong Chen, Margarito Lopez
  • Patent number: 6559089
    Abstract: Provided is a metallocene catalyst component for use if preparing isotactic polyolefins, which component has the general formula (I): R″ (CpR1R2R3)(Cp′R′n) MQ2 wherein Cp is a substituted cyclopentadienyl ring; Cp′ is substituted or unsubstituted fluorenyl ring; R″ is a structural bridge imparting stereorigidity to the component; R1 is a substituent on the cyclopentadienyl ring which is distal to the bridge, which distal substituent comprises a bulky group of the formula XR*3 in which X is chosen from Group IVA, and each R* is the same or different and chosen from hydrogen or hydrocarbyl of from 1 to 20 carbon atoms, R2 is substituent on the cyclopentadienyl ring which is proximal to the bridge and positioned non-vincinal to the distal substituent, and is of the formula YR#3, in which Y is chosen from Group IVA, and each R# is the same or different and chosen from hydrogen or hydrocarbyl of 1 to 7 carbon atoms, R3 is a substituent on the cyclopentadienyl ring which is pro
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: May 6, 2003
    Assignee: Fina Technology, Inc.
    Inventors: Abbas Razavi, Vincenzo Bellia
  • Patent number: 6559090
    Abstract: The present invention is directed to a coordinating catalyst system comprising at least one metallocene or constrained geometry pre-catalyst transition metal compound, (e.g., di-(n-butylcyclopentadienyl)zirconium dichloride), at least one support-activator (e.g., spray dried silica/clay agglomerate), and optionally at least one organometallic compound (e.g., triisobutyl aluminum), in controlled amounts, and methods for preparing the same. The resulting catalyst system exhibits enhanced activity for polymerizing olefins and yields polymer having very good morphology. The support-activator is a layered material having a negative charge on its interlaminar surfaces and is sufficiently Lewis acidic to activate the transition metal compound for olefin polymerization.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: May 6, 2003
    Assignee: W. R. Grace & Co.-Conn.
    Inventors: Keng-Yu Shih, Dean Alexander Denton, Michael John Carney
  • Patent number: 6559091
    Abstract: Catalyst compositions useful for the polymerization or oligomerization of olefins are disclosed. Certain of the catalyst compositions comprise metal complexes of mono through tetradentate ligands comprising N-pyrrolyl substituted nitrogen donors bonded to the metal. Also disclosed are processes for the polymerization or oligomerization of olefins using the catalyst compositions.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: May 6, 2003
    Assignee: Eastman Chemical Company
    Inventors: Leslie Shane Moody, Peter Borden Mackenzie, Christopher Moore Killian, Gino Georges Lavoie, James Allen Ponasik, Jr., Anthony Gerard Martin Barrett, Thomas William Smith, Jason Clay Pearson
  • Patent number: 6559092
    Abstract: The present invention concerns a process for sulphurising a hydrocarbon hydrotreatment catalyst in the presence of hydrogen and at least one sulphur-containing compound. The process is characterized in that the catalyst comprises a carbon-containing compound the major portion of which is not leachable deposited in its pores. The invention is of particular application to sulphurization carried out off-site.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: May 6, 2003
    Assignee: Europeenne de Retraitement de Catalyseurs Eurecat
    Inventors: Pierre Dufresne, Franck Labruyere, Michel Lacroix, Christophe Geantet, Cecile Glasson
  • Patent number: 6559093
    Abstract: A catalyst active in ammonia synthesis with improved activity and a process for the recovery of useful components from the catalyst.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: May 6, 2003
    Assignee: Haldor Topsoe A/S
    Inventors: Martin Muhler, Olaf Hinrichsen, Hubert Bielawa, Claus J. H. Jacobsen
  • Patent number: 6559094
    Abstract: The invention pertains to the preparation and use of catalytic materials and catalyst members for the selective oxidation of carbon monoxide in a gas stream that contains hydrogen. One such catalyst member may be produced by depositing by electric arc spraying a metal feedstock onto a metal substrate to provide a metal anchor layer on the substrate, and depositing a catalytic material comprising platinum and iron dispersed on a refractory inorganic oxide support material onto the metal substrate. The catalytic material may optionally be produced by wetting the support material, especially a particulate support material, with a platinum group metal solution and iron solution and drying and calcining the wetted support material in air at a temperature in the range of from 200° C. to 300° C., preferably using a solution containing bivalent platinum ion species. The catalyst member may be used by flowing the gas stream therethrough at a temperature at about 90° C.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: May 6, 2003
    Assignee: Engelhard Corporation
    Inventors: Olga Korotkikh, Robert J. Farrauto, Andrew McFarland
  • Patent number: 6559095
    Abstract: An exhaust gas purifying catalyst has an Ir powder. The Ir powder has a two peak particle size distribution, with a peak in a particle size D>25 nm region, and the other peak in a particle size D<25 nm region, respectively.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: May 6, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Tomomi Sugiyama, Kazuhide Terada, Takeshi Narishige
  • Patent number: 6559096
    Abstract: A desiccant composition and a method for making the desiccant composition. The dessicant composition includes an absorbent such as calcium chloride or lithium chloride which is impregnated onto a highly porous support such as activated carbon that has well controlled porosity characteristics. The material is particularly useful for absorbing high levels of water.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: May 6, 2003
    Assignee: Nanopore, Inc.
    Inventors: Douglas M. Smith, Elizabeth A. Lucky, Veronica Natividad
  • Patent number: 6559097
    Abstract: The present invention is a novel thermally-responsive record material comprising a substrate having provided thereon in substantially contiguous relationship an electron donating dye precursor, an acidic developer material, a compound of the formula wherein R1, R2 and R3 are independently selected from hydrogen, alkyl, alkoxy, aryl, aralkyl, aralkoxy, halogen, alkoxyalkoxy, and aralkoxyalkoxy; with the proviso that when R1, R2 and R3 are hydrogen, that R4 is not benzyloxyethoxy or alkyl-substituted benzyloxyethoxy; wherein R4 is independently selected from alkoxyalkyl, alkoxyalkoxy, and aralkoxyalkoxy, and a suitable binder therefor. In the context of the present invention the alkyl moieties in the alkyl, aralkyl, aralkoxy, alkoxyalkyl, alkoxyalkoxy and aralkoxyalkoxy preferably are eight carbons or less, and more preferably from one through four carbons. Substituents on aryl moieties in aryl, aralkyl, aralkoxy, and aralkoxyalkoxy groups can include hydrogen, alkyl, alkoxy and halogen.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: May 6, 2003
    Assignee: Appleton Papers Inc.
    Inventors: Ponnampalam Mathiaparanam, Mark Robert Fisher, John Charles DeBraal
  • Patent number: 6559098
    Abstract: Solid mixtures comprising a) an active ingredient from the group of the sulfonylureas and b) a sulfate- or sulfonate-containing surfactant.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: May 6, 2003
    Assignee: BASF Aktiengesellschaft
    Inventors: Matthias Bratz, Karl-Friedrich Jäger, Rainer Berghaus
  • Patent number: 6559099
    Abstract: The present invention relates to a method of enhancing the health of plant or seed in order to protect a plant or a seed from a stress-related injury by treating a plant with a composition containing at least one lysophospholipid. The present invention further relates to a method of enhancing or accelerating the recovery of an injured plant by treating such injured plant with a composition containing at least one lysophospholipid. Finally, the present invention relates to a method of enhancing the germination of seeds and seedling vigour by treating seeds with a composition containing at least one lysophospholipid.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: May 6, 2003
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Karim Farag, Jiwan P. Palta, Stephen B. Ryu
  • Patent number: 6559100
    Abstract: Substituted 2-benzoylcyclohexane-1,3-diones of the formula I where: R1 and R2 are each hydrogen, mercapto, nitro, halogen, cyano, thiocyanato, C1-C6-alkyl, C1-C6-haloalkyl, C1-C6-alkoxy, C2-C6-alkenyl, C2-C6-alkynyl, —OR3, —OCOR3, —OSO2R3, —S(O)nR3, —SO2OR3, —SO2N(R3)2, —NR3SO2R3 or —NR3COR3; R3 is hydrogen, C1-C6-alkyl, C1-C6-haloalkyl, C2-C6-alkenyl, C2-C6-alkynyl, phenyl or phenyl-C1-C6-alkyl; where the abovementioned alkyl radicals may be partially or fully halogenated and/or may carry one to three of the following groups: hydroxyl, mercapto, amino, cyano, R3, —OR3, —SR3, —N(R3)2, ═NOR3, —OCOR3, —SCOR3, —NR3COR3, —CO2R3, —COSR3, —CON(R3)2, C1-C4-alkyliminooxy, C1-C4-alkoxyamino, C1-C4-alkylcarbonyl, C1-C4-alkoxy-C2-C6-alkoxycarbonyl, C1-C4-alkylsulfonyl, heterocyclyl, heterocyclyloxy, phenyl, benzyl, hetaryl, phenoxy, benzyloxy and hetaryloxy, where the eight last mentioned radic
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: May 6, 2003
    Assignee: BASF Aktiengesellschaft
    Inventors: Stefan Engel, Joachim Rheinheimer, Ernst Baumann, Wolfgang von Deyn, Regina Luise Hill, Guido Mayer, Ulf Misslitz, Oliver Wagner, Matthias Witschel, Martina Otten, Helmut Walter, Karl-Otto Westphalen
  • Patent number: 6559101
    Abstract: N-(5,7-dimethoxy[1,2,4]triazolo[1,5-a]pyrimidin-2-yl) arylsulfonamide compounds were prepared from 2-amino-5,7-dimethoxy[1,2,4]triazolopyrimidine and appropriately substituted benzenesulfonyl chloride and pyridinesulfonyl chloride compounds. The compounds were found to be useful as herbicides.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: May 6, 2003
    Assignee: Dow AgroSciences LLC
    Inventors: Timothy Calvin Johnson, John Cord VanHeertum, David George Ouse, Kim Eric Arndt, Mark Andrew Pobanz, David Keith Walker
  • Patent number: 6559102
    Abstract: The invention relates to novel substituted 3-aryl-pyrazoles of the general formula (I) in which n, Q, R1, R2, R3, R4, R5 and X are each as defined in the description, and also to processes for their preparation and to their use as herbicides.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: May 6, 2003
    Assignee: Bayer Aktiengesellschaft
    Inventors: Otto Schallner, Karl-Heinz Linker, Joachim Kluth, Mark Wilhelm Drewes, Dieter Feucht, Rolf Pontzen, Ingo Wetcholowsky
  • Patent number: 6559103
    Abstract: A process is provided for preparing solid superconducting mixed-metal oxides whereby the superconductor can be formed into any predetermined shape by way of viscous sol precursors. The superconductors are also formed by this process into homogeneous phases.
    Type: Grant
    Filed: March 17, 1989
    Date of Patent: May 6, 2003
    Assignee: The Boeing Company
    Inventors: Brad Lee Kirkwood, Thomas S. Luhman, Ronald Roy Stephenson, Michael Strasik