Abstract: The present invention relates to an isolated protein or polypeptide corresponding to a coat protein or polypeptide of a grapevine leafroll virus. The encoding DNA molecule either alone in isolated form or in an expression system, a host cell, or a transgenic grape plant is also disclosed. Another aspect of the present invention relates to a method of imparting grapevine leafroll resistance to grape plants by transforming them with the DNA molecule of the present invention. A method for imparting tristeza virus resistance in citrus plants using the DNA molecule of the present invention is also disclosed.

Abstract: Disclosed are a method and compositions for delivering nucleic acids to bacterial cells. The method does not require manipulation of the bacteria and is therefore particularly suited to delivery of nucleic acids to bacteria in natural environments, including inside animals bodies. The method generally involves conjugating the nucleic acid to be delivered with a cationic porphyrin and bringing the conjugate and the target bacterial cells into contact. Both the porphyrin and conjugated nucleic acid are taken up by the bacterial cells and the nucleic acid can then have a biological effect on the cells. Specifically disclosed is a method for converting drug-resistant bacterial cells to drug-sensitive cells by delivery of external guide sequences to the cells which then promote cleavage of RNA molecules involved in conferring the drug-resistant phenotype on the cells. The drug-resistant phenotype of the cells is thus converted to a drug-sensitive phenotype.

Abstract: Disorders are diagnosed by analyzing biological samples of ad libitum-fed and dietary-restricted individuals to generate frequency distribution patterns representative of molecular constituents of the samples, and comparing the patterns.

Abstract: Techniques and devices for detecting and analyzing controlled substances and the like are discussed including highly reactive sensor molecules which are coated on a spectroscopic sample surface (4) and which may chemically react with a given analyte to form a covalently bonded adduct with spectral characteristics unique to the new adduct. The techniques provide the basis of a detection system with high sensitivity and high specificity in which the surface can even be washed to remove interfering or nonreactive compounds. The sensor molecules which comprise the coating (8) may have three major components: a central molecular scaffold (“CMS”), a “tether” terminated by a surface attachment group “SAG,” and a reactive functional group “RFG” which may be highly reactive towards certain classes of molecules.

Abstract: The present invention relates to an improvement in a detection system used for continuously measuring the release of a drug from a pharmaceutical dosage form comprising a singular dissolution vessel or multiple dissolution vessels containing a dissolution medium and a measuring device for detecting the amount of drug released at a given time, the improvement comprising a mixing shaft and a probe placed within the mixing shaft or outside the individual dissolution vessels, the probe capable of measuring the dissolution characteristics using UV, IR, near-IR, fluorescence, electrochemical, and Raman spectroscopy techniques. The present invention also relates to a method for predicting the dissolution curve provided by a controlled release pharmaceutical dosage form comprising taking continuous measurements of the amount of drug released from a dosage form for a portion of the time over which the drug is expected to be released and predicting the remainder of the dissolution curve based on the values obtained.

Abstract: An optical fiber is tapered, preferably adiabatically, and has a material coated on it for chemical bonding with fluorophores. When the fluorophores couple with the material, evanescent radiation generated fibers causes the fluorophores to fluoresce, and the fluorescence is coupled back into the fiber.

Abstract: An analytical device comprising a surfactant-treated porous reaction membrane having an exposed sample-contacting surface and at least one receptor area located in a limited region of the exposed sample-contacting surface. The limited region has a higher concentration of surfactant than areas of the sample-contacting surface that are peripheral to the limited region. To make the device, a surfactant-containing solution comprising at least 0.2% surfactant is added to the reaction membrane and allowed to dry. Then, a receptor reagent is added to a limited region of the reaction membrane. In the assay, the surfactant causes the liquid sample to flow faster through the portion(s) of the reaction membrane where receptor molecules are located.

Abstract: The present invention provides novel microfluidic devices and methods that are useful for performing high-throughput screening assays. In particular, the devices and methods of the invention are useful in screening large numbers of different compounds for their effects on a variety of chemical, and preferably, biochemical systems.

Abstract: Methods for assessing immunocompetence, cellular or humoral immunity, antigen exposure, or allergic conditions in an individual by accelerating diagnostic particles into a target skin site in the individual are provided.

Abstract: A method of manufacturing semiconductor devices uses a wafer carrier having conditioning units to control internal conditions of the wafer carrier. The wafer carrier stores and carries wafers between manufacturing equipments used in manufacturing processes. For each of the manufacturing processes, the method includes placing the wafer carrier on a load port, transferring the wafers from the wafer carrier into the manufacturing equipment through the load port, changing operating conditions of the conditioning units according to the process or test being carried out by the manufacturing equipment, returning the wafers into the wafer carrier through the load port after the completion of the process or test, and operating the conditioning units according to the changed operating conditions to control the internal conditions until the wafer carrier is carried to the next manufacturing equipment.

Abstract: In general, the present invention is directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method comprises forming a layer of titanium nitride by a chemical vapor deposition process, sensing a thickness of the layer of titanium nitride, and providing the sensed thickness of the layer of titanium nitride to a controller. The method further comprises determining at least one parameter of a plasma process to be performed on the layer of titanium nitride based upon the sensed thickness of the layer of titanium nitride and performing the plasma process comprised of the determined at least one parameter on the layer of titanium nitride.

Abstract: In one method for monitoring a semiconductor wafer during a spin drying operation, a capacitance value between a capacitance sensor and the wafer is measured as the wafer is being spun to dry a surface thereof. When it is determined that the measured capacitance value has reached a substantially constant level, a signal is generated indicating that the surface of the semiconductor wafer is dry. In another method, light is directed toward a surface of the wafer as the wafer is being spun to dry a surface thereof. The light is directed such that the light that reflects off of the surface of the wafer is substantially perpendicular to the surface of the wafer. The intensity of the light reflected off of the surface of the semiconductor wafer is measured.

Abstract: A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.

Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die.

Abstract: A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: A fluid-jet printhead has a substrate on which at least one layer defining a fluid chamber for ejecting fluid is applied. The printhead includes an elevation layer disposed on the substrate and aligned with the fluid chamber. The printhead also includes a resistive layer disposed between the elevation layer and the substrate wherein the resistive layer has a smooth planer surface interfacing with the resistive layer.

Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.

Abstract: A method for manufacturing an LCD panel comprises the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.

Abstract: According to this method, in order to fabricate active elements which comprise at least one doped part comprising a doping capable of absorbing a pump beam and at least one undoped part, and which have opposed faces of the same geometrical shape, a process of preparing an elongate active rod (5), which has a cross section identical to said geometrical shape, said process comprising at least one step of cutting and one step of joining at least one doped block (6) and at least one undoped block (7, 8), and a process of forming a plurality of active elements from the active rod (5), said formation process comprising at least one step of transverse cutting along the active rod (5) and the step of collectively treating surfaces of the active elements, are carried out in succession.

Abstract: A method and apparatus for fabricating a metamorphic long-wavelength, high-speed photodiode, wherein a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading region which grades past the desired lattice constant is configured at a low temperature. A reverse grade back is performed to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in a grading layer and a reverse grading layer. Thereon a strained layer superlattice substrate is created upon which a high-speed photodiode can be formed. Implant or diffusion layers grown in dopants can be formed based on materials, such as Be, Mg, C, Te, Si, Se, Zn, or others. A metal layer can be formed over a cap above a P+ region situated directly over an N-active region. The active region also includes a p-doped region.

Abstract: The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.

Abstract: A process for producing a semiconductor device comprising the steps of providing a wafer having a surface furnished with semiconductor circuits and a back; forming grooves of a depth smaller than the thickness of the wafer, said grooves extending from the wafer circuit surface; sticking a surface protective sheet onto the wafer circuit surface; grinding the back of the wafer so that the thickness of the wafer is reduced, resulting in division of the wafer into individual chips with spaces therebetween; sticking a pressure sensitive adhesive sheet onto the ground back of the wafer, pressure sensitive adhesive sheet comprising a base and, superimposed thereon, an energy radiation curable pressure sensitive adhesive layer; exposing the energy radiation curable pressure sensitive adhesive layer to an energy radiation; and peeling the surface protective sheet from the wafer circuit surface.

Abstract: A novel array of optically and electrically interacting optical MEMS dies physically and electrically integrally attached upon an optically transmissive preferably (transparent) printed circuit substrate that is monolithically formed with one or more optical components, such as lenses, for providing fixed optical path alignment and interaction therebetween, and with provision for the integration also of active optical components such as lasers and photodiodes and the like.

Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages.

Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The present invention also relates to assemblies comprising one or more of these substrates.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: An encapsulated semiconductor chip module. The chip module has the overlying encapsulant adhered directly and integrally to bare portions of the substrate to which the chip is mounted. This configuration enhances the adhesion and inhibits unintended delamination of the encapsulant from the balance of the module. The module is made by patterning anchor openings into the solder mask. The anchor openings expose corresponding portions of the substrate. It is important to locate the anchor openings over parts of the substrate that do not have circuitry on them, that is, on bare portions, so as to avoid corrosion or contamination of the circuit connections.

Abstract: A semiconductor device manufacturing method and a mold die that make it possible to expose the upper portions of external terminals with ease without having to implement a polishing process, are provided. The semiconductor device manufacturing method comprises a step in which external terminals are formed as bumps on a semiconductor element substrate, a step in which the semiconductor element substrate is mounted on the upper surface of a lower die of a mold die comprising an upper die and the lower die that is used to seal the semiconductor element substrate in resin, a step in which a tape is placed over the area of the upper surface of the lower die where the semiconductor element substrate is mounted and a step in which the upper die is placed in close contact with the external terminals. By employing this manufacturing method, it is possible to control the clamping force of the mold die.

Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.

Abstract: A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections.

Abstract: A CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity. The CCD having photodiodes in matrix form, includes a first interlevel insulating layer and first transfer gate sequentially formed between the photodiodes arranged in the row direction, a block insulating layer formed along the center of the first transfer gate, a second interlevel insulating layer formed on the first transfer gate, second and third transfer gates formed on the first transfer gate, being isolated from each other on the block insulating layer, a third interlevel insulating layer formed on the second and third transfer gates, and a fourth transfer gate formed on the third interlevel insulating layer, being placed on the second and third transfer gates.

Abstract: A method of crystallizing an amorphous silicon thin film is disclosed including the steps of preparing a substrate having a conductive layer, depositing an amorphous silicon thin film on the substrate, forming a metal thin film selectively overlying the amorphous silicon thin film, and performing a heat treatment and application of electric field to the metal thin film; and a method of fabricating a thin film transistor including the steps of preparing a substrate having a conductive layer, forming an active layer of amorphous silicon on the substrate, forming a gate insulating layer and a gate electrode on the active layer, doping the active layer with a first conductivity type impurity using the gate electrode as a mask, forming a metal thin film on the entire surface of the substrate including the active layer doped with the impurity, and performing a heat treatment and applying electric field to the substrate including the metal thin film.

Abstract: A method of manufacturing a thin film transistor. A gate electrode is formed on a substrate. Then a first gate insulation layer is formed on the gate electrode and on the substrate. The first gate insulation layer is then cleaned to remove contaminates. After cleaning, a second gate insulation layer is then formed on the first gate insulation layer. Beneficially, the first and second gate insulation layers are of the same material. An active layer having an ohmic contact layer is then formed on the second insulation layer. Spaced apart source and drain electrodes are then formed on the ohmic contact.

Abstract: The present invention provides a method for manufacturing a crystalline semiconductor thin film and is characterized in that it includes forming an amorphous semiconductor thin film on an insulated substrate, providing a single crystal semiconductor substrate primarily composed of the same material as that of the amorphous semiconductor thin film, including a catalytic metal on the surface thereof, putting the surface of the single crystal semiconductor substrate into contact with the amorphous semiconductor thin film, and performing a thermal process on the single crystal semiconductor substrate and amorphous semiconductor thin film in contact with each other at a temperature lower than the natural crystallizing temperature of the amorphous semiconductor thin film to crystallize the amorphous semiconductor thin film.

Abstract: A method for crystallizing an amorphous silicon film which includes the steps of: preparing a substrate having the amorphous silicon film, the amorphous silicon film being formed on an intermediate layer in which an inner space exists; applying an energy to the amorphous silicon film in order to crystallize the amorphous silicon film, wherein the step of preparing the substrate includes the steps of: forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, forming the amorphous silicon film on the intermediate layer,selectively removing the amorphous silicon film and the intermediate layer to expose a part of the material layer for forming space, and removing the material layer for forming space; or forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, selectively removing the intermediate layer to expose a part of the material layer, removing the mater

Abstract: A manufacturing method of a SOI substrate (10) comprises the steps of: forming an oxide film (12) at cross-sectional both main surfaces and cross-sectional both end surfaces of a silicon substrate (11); forming a resist layer (13) on the oxide film (12) at cross-sectional both end surfaces of the substrate (11); and removing the oxide film (12) at those portions which are left from the covering of the resist layer (13), to thereby expose the both main surfaces of the substrate (11). Next, the resist layer (13) is removed to thereby leave the oxide film (12) at the both end surfaces of the substrate (11); and oxygen ions (I) are dosed into the substrate (11) from one of the exposed both main surfaces, followed by an anneal processing to thereby form an oxide layer (14) in a region at a predetermined depth from the one main surface of the substrate (11). The oxide film (12) left on the both end surfaces of the substrate (11) is then removed.

Abstract: Laser annealing is performed by irradiating, while scanning, a semiconductor thin-film with laser light. The laser light that is linear on the irradiation surface is moved in its line-width direction and applied non-continuously. The laser light has, in its line-width direction, an energy density profile that assumes a step-like form in which the energy density varies in a step-like manner. In particular, the scanning pitch D and the step widths Ln are so set as to satisfy a relationship Ln≧D.

Abstract: A method to fabricate the TFT of a flat panel display. The method includes four photo etching processes and a back-exposure step. The gate is formed by the first photo etching process. The source and the drain are formed by the second photo etching process. Next, the back-exposure step is performed from the back of the substrate to form an island structure. Then, a protect layer is formed by the third photo etching process. Finally, the pixel electrode is formed by the fourth photo etching process.

Abstract: There is provided a semiconductor device using a TFT structure of high reliability. A gate electrode of a TFT includes a first conductive layer, a second conductive layer, and a third conductive layer. An LDD region has a part which overlaps the gate electrode via a gate insulating film and a part which does not overlap the gate electrode. As a result, this can prevent the deterioration when the TFT is on and can reduce a leakage current when the TFT is off.

Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Abstract: A semiconductor device is constructed of at least one indium nitride or indium nitride alloy nanostructure on a substrate or other thing film layer. The method used to create the semiconductor device involves illuminating the substrate with a lateral intensity patterning of ultraviolet light in the presence of at least hydrazoic acid and a compound containing indium gas flows. Additionally, a semiconductor light-emitting/detecting modulating device composed of at least one indium nitride or indium nitride alloy nanostructure. The method used to create the semiconductor light-emitting/detecting modulating device involves embedding at least one nanostructure in the interior layer of the device. Further, a monolithic photovoltaic-photoelectrochemical device where one layer is composed of an indium nitride or indium nitride alloy film or nanostructure.

Abstract: Plural p+-type regions are formed on a silicon substrate, and thereafter, an n-type epitaxial growth layer is formed. Narrow concave portions are formed to extend between the surface of the epitaxial growth layer 14 and the silicon substrate and to have the almost the same lateral sectional shape. As a result, remaining parts, which are defined by the concave portions, of the epitaxial growth layer on p+-type field limiting rings are separated from the silicon substrate. Thus, a depletion layer is spread beyond the field limiting rings and a large forward voltage-resistance can be realized.

Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.

Abstract: Integrated circuit comprising: at least one first and one second power supply terminal (418, 420), at least one active area (302, 304, 306, 308) formed in a thin layer (206) of a substrate and electrically connected to at least one of the power supply terminals. According to the invention, the circuit also comprises capacitive decoupling means formed by at least one dielectric capacitor (110, 112, 114) connected between the said, first and second power supply terminals and formed in a region of the substrate that is electrically insulated from the thin substrate layer (206). Applications include the manufacture of portable electronic equipment.

Abstract: The present invention provides a method for forming a storage electrode on a semiconductor substrate, and in particular to a storage electrode formation method which can prevent formation of a sharp upper edged cylindrical storage electrode, thereby improving a dielectric property and reliability of a capacitor.

Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device. The present invention forms a Ru film as a lower electrode of the capacitor in which a Ta2O5 film is used as a dielectric film by introducing Ru of a raw material, oxygen and NH3 in order to reduce oxygen or a NH3 plasma process as a subsequent process is performed in order to remove oxygen existing on the surface of the Ru film. Therefore, the present invention can prevent oxidization of a diffusion prevention film due to oxygen existing in a Ru film during annealing process performed after deposition of a Ta2O5 film and thus improve reliability of the device.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.