Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.

Abstract: A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

Abstract: The method according to the invention enables the roughness of an HSG surface to be substantially transferred to the surface of an electrode. The electrode consequently acquires a microstructured surface, the area of which can be increased by more than 25%, preferably by more than 50% and particularly preferably by more than 100%. An HSG layer is used to locally mask the electrode surface or the sacrificial layer. Subsequent structuring processes, such as for example wet-chemical and/or plasma-assisted etching processes, nitriding or oxidation processes, make it possible—working on the basis of micromasking effects—to significantly roughen the electrode surface and thereby to increase the electrode surface area.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: The present invention provides a method of fabricating a flash memory. The method first involves forming a gate oxide layer on a silicon substrate of a semiconductor wafer. Then, a first polysilicon layer, and a silicon nitride layer are formed, respectively, on the gate oxide layer. A lithographic process is then used to pattern a first photoresist layer for defining a memory array area and a peripheral region. The first photoresist layer is then used to etch the silicon nitride layer down to the surface of the silicon substrate to form a wide gap at the boundary between the memory array area and the peripheral region, and a plurality of gaps in the memory array area. An HDP oxide layer is then deposited, followed by coating of a photoresist (PR) on the wafer to achieve cell planarization. Thereafter, an oxide etch back process is performed followed by stripping of both the PR coating and the silicon nitride layer. Finally, a floating gate and a control gate are formed, respectively.

Abstract: A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

Abstract: The specification describes a dual level gate for reducing hot carrier effects in MOS transistors. The dual level gate is formed by undercutting the edges of the gate using a wet etch, and growing oxide in the undercut to a thickness exceeding the gate oxide thickness, thereby lifting the edge of the gate and reducing the electric field concentration at the drain edge of the gate.

Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.

Abstract: A method for fabricating a mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a thick oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the thick oxide layer. A portion of the thick oxide layer is then removed to expose the substrate, followed by forming a gate oxide layer on the exposed substrate surface for forming a plurality of coded memory cells, wherein the coded memory cells with a gate oxide layer corresponds to a logic state “1” while the code memory cells with a thick silicon oxide layer corresponds to a logic state “0”. A polysilicon layer is then formed on the substrate, followed by back-etching the polysilicon layer to expose the bar-shaped silicon nitride layer. After this, the bar-shaped silicon nitride layer is removed.

Abstract: A semiconductor device and a method of making the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, wherein one of the first dielectric material and the second dielectric material is a high-K. dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on a portion of the active device area. First spacers are formed on sidewalls of the gate electrode and the gate dielectric. A contact dopant is implanted into exposed regions of the active device area to form drain and source contact junctions. A contact laser thermal anneal is performed to activate the contact dopant within the drain and source contact junctions. The first spacers are removed, and an extension dopant is implanted into exposed regions of the active device area to form drain and source extension junctions. An extension laser thermal anneal is performed to activate the extension dopant within the drain and source extension junctions. The fluence of the extension laser thermal anneal is lower than the fluence of the contact laser thermal anneal.

Abstract: A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

Abstract: A method of using amorphous carbon as spacer material in a disposable spacer process can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous carbon spacers, and implanting dopants to form shallow structures in the substrate.

Abstract: A new processing sequence is provided for the process of creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency into the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co—Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix.

Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.

Abstract: The present invention silicon germanium bipolar device is fabricated by growing a silicon germanium layer on a semiconductor substrate followed by depositing a first oxide layer, a first polysilicon layer, and a first nitride layer on the silicon germanium layer. A well is etched through the first nitride layer and first polysilicon layer, exposing the first oxide layer on the bottom of the well, and the first nitride layer and first polysilicon layer on the side walls of the well. To cover the exposed edges of the first nitride layer and first polysilicon layer along the walls of the well, a second nitride layer is deposited and etched, forming nitride spacers along the sides of the well. The first oxide layer at the bottom of the well area is etched, creating gaps between the silicon germanium and first polysilicon layer. A second polysilicon layer is deposited in the gaps, creating a contact region electrically connecting the first polysilicon layer to the silicon germanium layer.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with an aqueous chemical solution to remove particles. To the cleaned surface, phosphorus ions arc implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300° C. to 550° C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.

Abstract: A method of fabricating a hyperabrupt junction varactor diode structure comprises the steps of forming a non-uniformly doped n-type, hyperabrupt cathode region in a layer of semiconductor material and depositing, by ultra high vacuum chemical vapor deposition (UHVCVD), a p-type anode region onto a surface of the hyperabrupt cathode region. The deposition process is performed at relatively low temperature (i.e., below 600° C.). The anode region and the hyperabrupt cathode are joined at a junction between them such that an impurity concentration level of the hyperabrupt region increases in a direction toward the junction. During the forming step, n-type impurity ions are implanted at an implantation energy level substantially less than 300 keV, preferably between from about 10 to about 70 keV, with the implanted ions being thermally activated at a relatively low temperature (between from about 700 to about 800° C.).

Abstract: A method for manufacturing a capacitor for a semiconductor device, that method including forming a first insulating layer having a contact hole on a semiconductor substrate and forming a diffusion barrier layer in the contact hole, with the diffusion barrier layer electrically connecting to the semiconductor substrate. Forming a second insulating layer and a third insulating layer sequentially on the first insulating layer, and providing a hole in the second insulating layer and third insulating layer to expose the diffusion barrier layer. Forming a conductive layer on the semiconductor substrate such that the conductive layer covers the inner wall of the hole in the second insulating layer and the third insulating layer. Forming an insulating fill layer that fills the remainder of the hole containing the conductive layer. Removing upper portions of the fill layer until the third insulating layer is exposed but a portion of the fill layer remains in the hole.

Abstract: A trench-fill material is deposited to fill a trench in a substrate disposed in a process chamber. An inert gas is introduced into the process chamber and a plasma is formed to heat the substrate to a preset temperature, which is typically the temperature at which deposition of the trench-fill material is to take place. The plasma is terminated upon reaching the preset temperature for the substrate. A process gas is then flowed into the process chamber without plasma excitation until the process gas flow and distribution achieve a generally steady state in the process chamber. A plasma is then formed to deposit the trench-fill material on the surface of the substrate and fill the trench. By establishing generally steady state conditions in the chamber prior to deposition, transient effects are reduced and more uniform deposition of the trench-fill material is obtained.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: The method as disclosed reduces the topological step between the uppermost surface of a substrate and the uppermost surface of a shallow trench isolation feature. The method includes the steps of forming a pad oxide layer overlying a substrate, forming a stop layer overlying the pad oxide layer, forming a second oxide layer overlying the stop layer, forming a patterning layer overlying the second oxide layer, and patterning the patterning layer and underlying stack to form an exposed portion of the substrate. The exposed portion of substrate is etched to form a trench, and the remaining portion of the oxidation resistant layer is removed. Further, a dielectric layer is formed overlying the remaining portion of the second oxide layer, and filling the trench. A portion of the dielectric layer is removed to leave the top of the dielectric layer substantially level with the stop layer, and then the stop layer is removed.

Abstract: The present invention provides a method of fabricating a semiconductor device having a trench isolation structure. The method includes the following steps. A hard mask layer is formed on the semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and simultaneously to define a second isolation region at the peripheral circuit region. A sacrificial material layer is conformally formed at the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first trench region and a second trench region at the cell array region and the peripheral circuit region, respectively.

Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.

Abstract: A method of fabricating a semiconductor device capable of sufficiently rounding an opening upper end of an element isolation trench is obtained. This method of fabricating a semiconductor device comprises steps of forming an element isolation trench on a semiconductor substrate, performing thermal oxidation on at least an opening upper end of the element isolation trench while increasing the atmosphere temperature of the semiconductor substrate beyond a prescribed temperature thereby forming a first oxide film and suppressing formation of the first oxide film on the opening upper end before the atmosphere temperature is increased beyond the prescribed temperature. Thus, the semiconductor substrate is prevented from oxidation under a low temperature, whereby oxidation is more thickly performed by thermal oxidation in a high-temperature region while relaxing stress applied to the semiconductor substrate.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Abstract: A method of fabricating a semiconductor device capable of improving productivity by efficiently polycrystallizing an amorphous silicon film is obtained. This method of fabricating a semiconductor device comprises steps of forming an amorphous film on a substrate, forming a conductor film on the substrate, arranging the substrate so that the surface of the conductor film is substantially parallel to an electric field in a waveguide and irradiating the conductor film with an electromagnetic wave thereby making the conductor film generate heat and crystallizing the amorphous film with the heat. Thus, the substrate is arranged to be substantially parallel to the electric field in the waveguide, whereby the absorptivity of the conductor film for the electromagnetic wave is improved and hence the conductor film can be efficiently heated. Thus, crystallization is performed in a short time, thereby improving productivity.

Abstract: Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Abstract: There is provided a method in which a TFT with superior electrical characteristics is manufactured and a high performance semiconductor device is realized by assembling a circuit with the TFT. The method of manufacturing the semiconductor device includes: a step of forming a crystal-containing semiconductor film by carrying out a thermal annealing to a semiconductor film; a step of carrying out an oxidizing treatment to the crystal-containing semiconductor film; a step of carrying out a laser annealing treatment to the crystal-containing semiconductor film after the oxidizing treatment has been carried out; and a step of carrying out a furnace annealing treatment to the crystal-containing semiconductor film after the laser annealing. The laser annealing treatment is carried out with an energy density of 250 to 5000 mJ/cm2.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.

Abstract: A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

Abstract: The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.

Abstract: In a semiconductor device that uses a low-resistance ohmic contact and which is suitable for high-speed operation, the ohmic contacts are formed by a single-crystal CoSi2 film that is formed on the (100) surface of a silicon substrate.

Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: A method for forming contacts in a semiconductor device including a plurality of active devices formed over a substrate that includes depositing a first layer of dielectric material over the substrate and plurality of active devices, forming a first opening in the first layer of dielectric material, depositing a second layer of dielectric material over the first layer of dielectric material and in the first opening, providing a mask over the second layer of dielectric material, wherein the mask material is distinguishable over silicon oxides, and forming a second opening and a third opening in the second layer of dielectric material, wherein the second opening is aligned with the first opening and exposes a first silicide of a first active device, and the third opening exposes one of diffused regions of a second active device.

Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.

Abstract: An insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices formed by curing a flowable oxide layer and annealing. The annealing is carried out in the presence of hydrogen and aluminum to obtain a dielectric constant of the oxide layer to a value below 3.2. Also provided is electrical insulation between neighboring devices using the flowable oxide which is cured and annealed. In this case, the annealing can be carried out in hydrogen with or without the presence of aluminum.

Abstract: The formation of intermetallic residue regions during the formation of a semiconductor metal layer, which has a base metal layer and a cap metal layer formed on the base metal layer, is substantially reduced by forming a layer of oxide on the base metal layer before the cap metal layer is deposited.

Abstract: Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material.

Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

Abstract: A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via.

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

Abstract: Method and apparatus for depositing an amorphous silicon film on a substrate using a high density plasma chemical vapor deposition (HDP-CVD) technique is provided. The method generally comprises positioning a substrate in a processing chamber, introducing an inert gas into the processing chamber, introducing a silicon source gas into the processing chamber generating a high density plasma, and depositing the amorphous silicon film. The amorphous silicon film is deposited at a substrate temperature 500° C. or less. The amorphous silicon film may then be annealed to improve film properties.