Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.

Abstract: A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

Abstract: In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

Abstract: Setting the clock frequency provided to a load circuit as function of the operating temperature and supply voltage of the load circuit, and setting the supply voltage as a function of the operating temperature of the load circuit. The load circuit can be safely operated above the frequency which would be the limit if the load circuit were operating at the maximum test temperature. At the given operating temperature, the supply voltage can be raised to permit even higher frequency operation, or lowered to reduce power.

Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Abstract: A carrier recovery apparatus for digital Quadrature Amplitude Modulation (QAM) receivers is disclosed. The carrier recovery apparatus includes a phase detector, a lock controller, a frequency locker and a phase loop filter, and provide phase/frequency error information for a numerically controlled oscillator (NCO) to generate recovered carrier frequency. The phase detector detects the symbol energy information and the phase error information of the extracted symbols from the I/Q extractor. The lock controller monitors the symbol energy from the phase detector, separates the extracted symbols into two groups: valid and non-valid, and outputs the control flag of valid symbols into both the frequency locker and the phase loop filter. To achieve a wide range acquisition and a good tracking performance, the lock controller controls the operation of the frequency locker and the phase loop filter in three operations.

Abstract: A system and method for carrier recovery independent of a pilot signal uses the frequency and phase information in the upper and lower band edges of a signal to generate a signal for correcting the frequency and phase of the local oscillator. A particular combination of raised-root cosine filters, low-pass filters, multipliers, and adders effectively uses the tails of a received signal in the frequency domain to correct phase errors.

Abstract: A DC offset compensation circuit, and method thereof are capable of reducing the settling time of an output signal through fast compensation of a DC offset of the output signal although a DC voltage of an input signal varies in a closed loop operational amplifier. The DC offset compensation circuit of a closed loop operational amplifier includes a first closed loop operational amplifier and a second closed loop operational amplifier. The first closed loop operational amplifier amplifies an input signal based on a compensation voltage. The second closed loop operational amplifier amplifies a signal output from the first closed loop operational amplifier based on a reference voltage to generate a final output signal.

Abstract: A signal handling stage provides variable gain, for example for automatic gain control functions, in a radio frequency tuner. The stage comprises a transconductance stage having negative feedback via further transconductance stage. The output current of the transconductance stage is supplied to an AGC core, which steers the output current between output loads and loads for driving the transconductance stage in accordance with an AGC voltage. The amount of negative feedback is therefore varied in accordance with the AGC voltage. For relatively low gain, a large amount of feedback is used and this improves the distortion performance. For relatively high gain, the negative feedback is reduced but a good noise figure can be achieved.

Abstract: A polar modulator creates an amplitude signal and a frequency signal and digitally adjusts the signals so that the frequency and amplitude signals arrive at the power amplifier at the appropriate times. A digital predistortion filter is applied to the frequency signal. The frequency signal is then provided to a single port of a fractional N divider in a phase locked loop. The output of the phase locked loop drives an input of the power amplifier while the amplitude signal is converted to an analog signal and controls the power supply input of the power amplifier.

Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Abstract: An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Abstract: A differential amplifier is constructed in such a manner that the sources of a first and a second MOS transistor and the drain of a third MOS transistor are connected to each other, these MOS transistors being of the same conductivity type, the other end of a current source whose one end is connected to a power supply or the ground is connected to the drain of the first MOS transistor and the gate of the third MOS transistor, and the source of the third MOS transistor is connected to the power supply or the ground. The differential amplifier supplies a differential input signal to the gates of the first and second MOS transistors and obtains the output from the drain of the second MOS transistor. Two units of the differential amplifier are connected in parallel, with the input terminals cross-coupled with each other, thereby constructing a differential amplifier of the completely differential type.

Abstract: The present invention provides a variable gain amplifier with a plurality of gain stages in which each of the gain stages is implemented using a circuit that implements a neutralization approach. This variable gain amplifier provides stable operation characteristics as different gain stages within the variable gain amplifier are turned on and off. This variable gain amplifier also increases linearity across the entire operating range. Additionally, the variable gain amplifier of the present invention provides a constant input impedance through different gain settings. Further, the present invention provides a variable gain amplifier in which each of the various gain stages therein maximize the available voltage swing. Finally, this variable gain amplifier improves common-mode rejection performance and attenuates unwanted harmonics.

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

Abstract: An output power control system includes an amplifier configured to supply a first current, a reference source configured to supply a second current which is proportional to and less than the first current, and a feedback converter responsive to the second current to control a gain of the amplifier.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio &ohgr;3/&ohgr;ref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio &ohgr;3/&ohgr;ref are substantially independent of the divider ratio N.

Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

Abstract: A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.

Abstract: A circuit arrangement for reducing the decay and build-up transient times of an intermittently operating oscillating circuit increases the data transmission rate of a transmission unit using such an oscillating circuit. A control unit is connected to the oscillating circuit including a capacitor, a coil, and a resistor. A switch element controlled by the control unit selectively connects a voltage source to the capacitor, or selectively connects a current source to the coil. In the former case, another switch element selectively disconnects the capacitor from the coil and the resistor. In this circuit arrangement the current and/or the voltage are maintained when the excitation voltage for the oscillating circuit is interrupted. This eliminates the decay of the oscillating circuit amplitudes. When the excitation voltage is switched on again, the oscillating circuit continues oscillating without delay.

Abstract: A method of tuning a DCXO includes the step of providing a coarse tuning array and a fine tuning array of capacitors fabricated on the same integrated circuit die. The coarse array is adjusted until the difference between a desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array. A DCXO apparatus includes at least one integrated circuit segmented switched capacitor network providing a capacitance that is a nonmonotonic function of a composite input code. The segmented switched capacitor network includes parallel coupled binary weighted and thermometer coded switched capacitor networks for coarse and fine tuning, respectively.

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: In some embodiments of the present invention, there is a system and method of synchronizing a QAM demodulator by determining a phase offset error value between an actual phase shift of a received symbol and an estimated phase shift value.

Abstract: The invention generally relates to tuning arrangements and tuning components for influencing an electric field in a microwave device, in particular in a microwave communication device such a microwave circulator and isolator, comprising a tuning element having a tuning portion which cooperates with the housing of the device in an electrically non-conductive manner.

Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

Abstract: The present invention relates to a concurrent multi-band amplifiers and to a monolithic, concurrent multi-band low noise amplifier (LNA). The inventive LNA includes a three-terminal active device, such as a transistor with a characteristic transconductance, gm, disposed on a semiconductor substrate. The active device has a control input terminal, an output terminal, and a current source terminal. The amplifier also includes an input impedance matching network system, Zin, and an output load network. Zin simultaneously and independently matches the frequency-dependent input impedance of the three-terminal active device to a predetermined characteristic impedance at two or more discrete frequency bands. The output load network simultaneously provides a voltage gain, Av, to an input signal at the amplifier input at each of the two or more discrete frequency bands.

Abstract: An impedance matching circuit includes a conductor line having an input port and an output port, a ground conductor, a tunable dielectric material positioned between a first section of the conductor line and the ground conductor, a non-tunable dielectric material positioned between a second section of the conductor line and the ground conductor, and means for applying a DC voltage between the conductor line and the ground conductor. The impedance matching circuit may alternatively include a first planar ground conductor, a second planar ground conductor, a strip conductor having an input port and an output port, and positioned between the first and second planar ground conductors to define first and second gaps, the first gap being positioned between the strip conductor and the first planar ground conductor and the second gap being positioned between the strip conductor and the second planar ground conductor.

Abstract: A filter network designed for providing high frequency selectivity with a high degree of reliability and availability. The filter network comprises a superconducting filter and a non-superconducting filter, or a combination thereof to form multiplexers. A receive side of the non-superconducting filter pre-filters received RF signals before inputting them to the superconducting filter. The non-superconducting filter is constructed and arranged to pass RF signals having a frequency within a first pass band to the superconducting filter. The superconducting device is constructed and arranged to exhibit a high-degree of frequency selectivity in further narrowing the received RF signals. Other aspects are directed to the arrangement, construction, and uses of the same structures to accomplish different but similar goals.

Abstract: A high-frequency switch includes a transmission terminal, an antenna terminal, a reception terminal, and a voltage-control terminal; a first diode, the cathode thereof being electrically connected to the transmission terminal, and the anode being electrically connected to the antenna terminal; a first transmission line, electrically connected between the antenna terminal and the reception terminal; a second diode, the cathode thereof being electrically connected to the reception terminal, and the anode being electrically connected to the voltage-control terminal; a second transmission line, one end thereof being electrically connected to the transmission terminal, and the other end being connected to ground; and a capacitor, electrically connected between the voltage-control terminal and ground. The above high-frequency switch can be miniaturized and has superior performance.

Abstract: A device for impedance matching a signal generator to a plurality of elements of a multi-element load. The device includes an outer conductor having an inner surface and an inner conductor positioned within the outer conductor, and having an outer surface. The device further includes a first and second set of transformation sections, which provide a particular separation distance between the inner surface of the outer conductor and the outer surface of the inner conductor to yield a particular characteristic impedance for each of the first and second sets of transformation sections, thereby substantially matching the impedance of the generator to the elements of the load.

Abstract: An electromagnetic filter has a pair of solder-in filters assembled together outside of a filter housing, inserted into, and soldered to the filter housing. The solder-in filters have a metal casing and a capacitor encapsulated within the metal casing and attached to the metal casing. A glass hermetic seal on one end of the solder-in filters reduces the risk of moisture entering the filter during the testing process and adversely affecting the electrical properties of the filter.

Abstract: A waveguide filter made a rectangular waveguide section 12 with cavities 14 forming resonators spaced along opposite walls of the waveguide is configured to reduce the harmonic passband amplitude noise due to higher order harmonics. The cavities 14 are modified from conventional cavities by having different lengths L1-L8 and widths A1-A8, as opposed to equal length and equal width values. Each cavity is designed to resonate at the desired principal frequency f1 according to the combination of the cavity width and length, but with cavities having different lengths and widths, synchronous resonances do not occur at higher order harmonic frequencies f2 and f3 normally occurring when the cavities all have equal widths and equal lengths.

Abstract: A millimeter wave module includes a silicon substrate with first and second cavityes formed by anisotropic etching on the silicon substrate, and a glass substrate having a microstrip filter pattern and microbumps for connecting the glass substrate to the silicon substrate. A filter is provided using an air layer as a dielectric disposed in the first cavity. An MMIC is mounted by the flip chip method over the second air layer. A coplanar waveguide is on the silicon substrate for connecting the filter and MMIC. The filter having low loss is achieved because it has the microstrip structure using air as an insulating layer. Also change in characteristics of the MMIC during mounting is eliminated because the MMIC is protected by contacting air. Accordingly, the millimeter wave module has excellent characteristics and is made using a simple method.

Abstract: An object of the present invention is to provide a radio frequency integrated circuit module that is less susceptible to the electromagnetic influence and that is not degraded in electric connection. The radio frequency circuit module of the present invention including circuit elements mounted on a multi-layer circuit substrate having dielectric layers is characterized in that an exposed connection portion is provided by removing a part of the dielectric, and a strip line connected to said circuit elements and a co-axial line for transmitting a radio frequency signal from/to said strip line are connected together in a bottom portion of said exposed connection portion so as to be rectilinear in a three dimensional way.

Abstract: This invention relates to a circuit interrupting device having a trip button for disconnecting a load from a source of electrical power and a reset button for resetting the device after it has tripped. When the device is operating in its reset state, a source of electrical power is connected to a load through a set of contacts located within the device. The contacts are held closed by the spring loaded reset button which holds captive and urges a latch plate to move up to close normally open contacts. In the preferred mechanical trip mechanism, depressing the trip button causes the latch plate to move forward and be released from the reset button. The latch plate, upon being released from the reset button moves down to allow the contacts, which are biased to be normally open, to assume their normally open position. At this time, pressing the reset button initiates an electrical cycle which causes the normally open contacts to close only if the device is operating properly and there is no fault on the line.

Abstract: An adjustable magnetic trip unit for a circuit breaker includes a torsion spring which applies a bias force to the plunger of a trip solenoid. The torsion spring is mounted on a driven bevel gear and wound by an adjustment knob coupled to a driving bevel gear to adjust the current at which the solenoid is activated. An indexer having peripheral flats which engage a seat in the circuit breaker housing provides a plurality of discrete positions of the adjustment knob. Depressing the adjustment knob against a second spring unseats the indexer for rotation of the adjustment knob between settings. In addition, a slide with an inclined surface bearing against the plunger and coupled to the driven bevel gear, provides simultaneous adjustment of plunger gap with adjustment of the torsion spring force to increase the range of adjustment.

Abstract: A core for a three-phase transformer, the core comprising a centrally-disposed flux collector and three generally C-shaped core leg sections peripherally arranged about the flux collector in an angularly spaced relationship and connected to the flux collector. The three core leg sections are each adapted to support a transformer coil and the flux collector is adapted to provide a low reluctance path to magnetically link the coils of the transformer.

Abstract: Slot core inductors and transformers and methods for manufacturing same including using large scale flex circuitry manufacturing methods and machinery for providing two mating halves of a transformer winding. One winding is inserted into the slot of a slot core and one winding is located proximate to the exterior wall of the slot core. These respective halves are joined together using solder pads or the like to form continues windings through the slot and around the slotted core.

Abstract: An inductor is constructed to achieve efficient formation of external electrodes, and exhibits high reliability of connection between the external electrodes and an internal conductor, and desired characteristics. In the method of manufacturing the inductor, a magnetic material formed by kneading a magnetic material and a resin is molded to form a magnetic material compact body in which the internal conductor is partially exposed from the external surface thereof, and then the surface of the magnetic material compact body is plated to form the external electrodes including a plated metal film and connected to the internal conductor. The surface of the magnetic material compact body is roughened, and then the external electrodes are formed via plating.

Abstract: A dust core consists essentially of ferromagnetic powder; and an insulating binder, in which the ferromagnetic powder is dispersed; wherein the insulating binder is a silicone resin comprising a trifunctional alkyl-phenyl silicone resin and optionally containing an inorganic insulator such as an inorganic oxide, carbide or nitride. Preferably the alkyl-phenyl silicone resin is a methyl-phenyl silicone resin and comprises about 20 to 70 mol % of trifunctional groups. The dust core can be produced by pressure-molding a ferromagnetic powder, a lubricant and a trifunctional alkyl-phenyl silicone resin binder and heat treating the molded core at a temperature in the range of about 300 to about 800 ° C. for a time period in the range of about 20 minutes to about 2 hours in a non-oxidizing atmosphere. The dust core has high magnetic permeability representing the direct current superimposition characteristics, has reduced core loss and has increased mechanical strength.

Abstract: A magnetic sticking sheet comprising a non-magnetic base and a magnetic layer formed on the non-magnetic base by coating a magnetic coating material containing ferromagnetic particles and a binder, the magnetic layer having a thickness of 0.03 to 0.10 mm, oriented longitudinally to give a squareness ratio of 80 to 90%, and multipolar-magnetized longitudinally; the sheet having a total thickness of 0.08 to 0.25 mm and flexibility for rolling; the magnetic layer having a surface magnetic flux density of 35 to 100G; and the sheet having a magnetic sticking force, required for removing a magnetic sticking sheet fixed magnetically on a magnetic surface via the magnetic layer while keeping the magnetic surface and the sheet parallel, of 0.4 to 0.9 gf/cm2.