Abstract: A radioactive dust monitor comprising a dust collecting electrode serving also as a radiation detecting surface, an ionization line extending in air in a spaced relation with the dust collecting electrode and a radiation detection part. The radiation detection part is provided with a scintillator disposed close to said dust collecting electrode and a photoelectric conversion part converting light emitted from the scintillator into an electric signal. Dust in air is collected by the dust collecting electrode due to a corona discharge which is generated by applying a negative high voltage to the ionization line and by applying a positive high voltage to the dust collecting electrode, and light emitted from the scintillator due to radioactive rays radiated from the collected radioactive dust is detected by the photoelectric conversion part.

Abstract: In a radiographic apparatus or a digital cassette in which a metal support is fitted to the interior of a casing of the apparatus through spacers, an x-ray image detection panel is disposed on a front surface of the support, an electric circuit board is fixed to a back surface of the support through projections, and the x-ray image detection panel and the electric circuit board are connected to each other by flexible circuit boards. Because shock absorbers made of sheet-like elastic material or gel material are disposed on the inner side of the side walls of the casing, even if the apparatus is dropped on its side wall by mistake and the side wall of the casing is instantaneously deformed, the shock is absorbed by the shock absorber, and as a result the shock transmitted to the support, the x-ray image detection panel, the flexible circuit board or the like can be reduced, and the shock resistance of the apparatus is improved.

Abstract: An apparatus for producing an electron beam, containing a vacuum chamber, a source of electron beams within the vacuum chamber, and a device for focusing the electrons beams. An electron transparent window is formed at the end of the vacuum chamber; and the vacuum chamber has a volume of less than about 1 cubic millimeter and a pressure of less than 10−7 Torr. In one embodiment, the focusing device is located outside of the vacuum chamber.

Abstract: A germicidal UV chamber for use on air passing through a duct system, such as a central air system which replace one or more sections of the duct and, in essence, becomes part of the duct work. Each chamber is in the form of one or more ellipsoid sections which focus the energy uniformly throughout the chamber. The UV lamp is in the form of a helix around the center line of the chamber. Its pitch may very along its length so as to concentrate the UV radiation towards the center of the chamber. A UV transparent conduit may be positioned in the center of the coils of the helical UV lamp to convey a liquid through the lamp.

Abstract: The present invention transmits, to an electronic board controller 14, click signals generated upon manipulating multiple switches provided on a coordinates-inputting pen 13, timing signals upon detecting infrared scanning beams 18a and 18b, and the like without using a connecting wire. Specifically, light-emitting elements are provided which can emit visible or infrared light to the coordinates-inputting pen 13. A timing signal upon detecting the infrared scanning beam with the pen and a click signal generated upon manipulating the switch on the pen are sent out on a modulated light 19 to be received by a light receiver 20 arranged at a fixed position and transmitted to the electronic board controller 14.

Abstract: An optical detection system for flow cytometry that uses two or more light sources positioned laterally at different distances from a central axis of a flow stream for providing light through different parts of the flow stream. One or more lenses are used to focus the light from the two or more light sources through the flow stream and onto a common focal point or region on the opposite side of the flow stream. One or more light detectors are then placed at, near or around the common focal point or region. A processor or the like receives at least one output signal from the one or more light detectors to analyze and determine selected characteristics of the flow stream.

Abstract: A method of compensating for differences in detective gain between a plurality of different scanning heads in a multiple scanning head imaging plate scanner, comprising: (a) scanning each of the scanning heads across an imaging plate thereby determining the detected signal at successive locations across the imaging plate for each of the scanning heads; (b) calculating an inverse relationship to the detected signal at successive locations across the imaging plate for each of the scanning heads; (c) scanning each of the scanning heads across an imaging plate containing an image thereon, thereby determining an image value at the successive locations across the imaging plate for each of the scanning heads; and (d) applying the inverse relationship to the determined image values at the successive locations across the imaging plate for each of the scanning heads.

Abstract: A display device includes a backside and a front-side substrates facing each other with a vacuum space therebetween; and a plurality of electron emission sites provided on the backside substrate. Each electron emission sites includes a bottom electrode formed on a surface of the backside substrate proximate to the vacuum space, an insulator layer formed over the bottom electrode, and a top electrode formed on the insulator layer and arranged individually apart from each other and facing the vacuum space. The display device also includes a plurality of bus electrodes for electrically connecting the neighboring top electrodes; and insulating protective films each provided between the bus electrode and the insulator layer and between the bus electrode and the backside substrate.

Abstract: A film having a high thermal conductivity material such as aluminum nitride is formed on a substrate, and then a silicon film is formed. When a laser light or an intense light corresponding to the laser light is irradiated to the silicon film, since the aluminum nitride film absorbs heat, a portion of the silicon film near the aluminum nitride film is solidified immediately. However, since a solidifying speed is slow in another portion of the silicon film, crystallization progresses from the portion near the aluminum nitride film. When a substrate temperature is 400° C. or higher at laser irradiation, since a solidifying speed is decreased, a crystallinity of the silicon film is increased. Also, when the substrate is thin, the crystallinity of the silicon film is increased.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the same, the device being provided with a semiconductor circuit consisting of a semiconductor element that is capable of improving characteristics of a TFT and has uniform characteristics, the device and the method being provided by improving the interface between an active layer, in particular, a region for constructing a channel formation region and an insulating film.

Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Abstract: A light emitting device (LED) package comprises: a thermally conductive layer; an electrically insulating layer having openings extending therethrough; LEDs situated within the openings of the electrically insulating layer and including contact pads; and electrically conductive strips attached to the contact pads and the electrically insulating layer.

Abstract: A light emitting diode device has a reflector member having an approximately semispherical recess. A reflector surface is provided on an inner surface of the recess and a light emitting diode is provided in the recess. The light emitting diode is located at a position so that a part of light beams emitted from the light emitting diode recedes from an optical axis, and another part of the light beams approaches to the optical axis.

Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.

Abstract: The main surface on the side of a p-type layer of a GaP-base semiconductor is defined as a first main surface, and the main surface opposite thereto as a second main surface. The second main surface is lapped and then etched using aqua regia to thereby collectively form thereon specular concave curved surfaces which swell inwardly into the semiconductor substrate in order to enhance total reflection of light. On the other hand, the area on the surface of semiconductor substrate excluding that for forming a first contact layer and excluding the second main surface are subjected to anisotropic etching to thereby collectively form outwardly-swelling convex curved surfaces in order to reduce total reflection of light. A second contact layer (second electrode) to be formed on the second main surface is composed of an alloy of Au, Si and Ni, and a first contact layer to be formed on the first main surface is composed of an alloy of Au as combined with either of Be and Zn.

Abstract: A thyristor for switching microwave signals includes semiconductor layers disposed on a substrate. A first surface of the thyristor defines an anode, and a second surface of the thyristor defines a cathode. The semiconductor layers include at least one semi-insulating layer. The thyristor transmits a microwave signal between the anode and the cathode in an ON state and blocks the microwave signal between the anode and the cathode in an OFF state.

Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.

Abstract: The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and the bottom surface. An integrated circuit is fabricated on the semiconductor wafer and includes a working set of discrete functional modules arranged into a central rectangular array of rows and columns defined by a boundary that includes four rectilinear sides and four corners. The integrated circuit further includes a spare set of discrete functional modules formed outside the boundary of the working set into at least one line that is disposed along a side of the rectangular array of the working set. If a discrete functional module in the working set is found to be defective, it can be replaced by a discrete functional module in the spare set.

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer; a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type. The laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer provides a diode for photoelectric conversion. A first insulator layer and a second insulator layer are formed respectively in at least a portion below the bipolar transistor and the MIS transistor.

Abstract: A capacitor structure characterized by improved capacitance as a result of increasing the capacitance associated with charge spreading that occurs within the electrodes of the capacitor. The electrodes are formed of superconducting or high-dielectric constant conductor materials, and are preferably used in combination with high-dielectric constant insulator materials. The capacitor structures are particularly suited as thin-film capacitors of the type used for high-density applications such as DRAM.

Abstract: A semiconductor memory device able to increase the effective area of a capacitor in a memory cell and ensure a sufficient amount of charge contained in a read signal while maintaining the smallest cell area and a method for producing the same, wherein a first node electrode, a first ferroelectric film, and plate electrodes form four ferroelectric capacitors, plate electrodes, a second ferroelectric film, and a second node electrode form other four ferroelectric capacitors, the first node electrode is electrically connected to the second node electrode, a capacitor below a plate electrode is connected in parallel with the capacitor above the plate electrode, and these two capacitors connected in parallel form a memory cell storing 1 bit of data.

Abstract: There is provided such a structure that a first insulating layer, a conductive pattern, a second insulating layer, a capacitor Q, a third insulating layer, and a lower electrode leading wiring are formed sequentially on a semiconductor substrate, and a lower electrode of the capacitor is connected to an upper surface of the conductive pattern, and the lower electrode leading wiring is also connected electrically to the conductive pattern from its upper side.

Abstract: A stacked DRAM cell capacitor having HSG silicon only on a top portion of a storage node, not on a bottom portion thereof. The storage node has a double layer structure including a bottom layer and a top layer. The bottom layer is made of a conductive material that suppresses the growth of HSG seeds. Accordingly, electrical bridges between adjacent storage nodes, particularly at a bottom portion, can be prevented.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug.

Abstract: An embodiment of the memory cell for an EEPROM device may comprise a trench coupling capacitor wherein the coupling oxide of the coupling capacitor is formed only in the trench (i.e., such that coupling occurs only in the trench). In addition, a first portion of a floating gate of the memory cell is formed in the trench to function as a part of the coupling capacitor as well as a floating gate. A floating gate second portion is electrically connected to the first portion. A control gate is connected to a doped region of the substrate and a thin tunnel dielectric physically separates the floating gate second portion from the coupling oxide layer and from the doped region of the substrate.

Abstract: A device and method uses charge trapping to configure and adjust a threshold voltage (Vt) for a field effect transistor (FET). The charge trapping mechanism can be controlled by bias voltages applied to the FET, so that rapid/dynamic changes can be made to Vt without the use of conventional program/erase cycles. The threshold voltage can thus be set as a function of applied operating voltages.

Abstract: An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At least one third semiconductor layer of the first conductivity type is formed in a surface area of each of the second semiconductor layers. A fourth semiconductor layer is formed on a bottom of the first semiconductor layer. At least one fifth semiconductor layer of the second conductivity type is provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers. The fifth semiconductor layer has impurity concentration that is lower than that of the second semiconductor layers.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A method of making a trench MOSFET structure having upper trench corner protection, the method not requiring trench corner rounding or sacrificial oxide/strip steps. The trench MOSFET structure fabricated according to the method of the present invention exhibits higher oxide breakdown voltage and lower gate-to-source capacitance.

Abstract: The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second side-wall insulator layers formed on side walls and on a portion of first surface, and a nitrogen-containing extending from the portion of silicon substrate that is in the vicinity of second surface to the portion of silicon substrate that is in the vicinity of the interface between first and second side-wall insulator layers and silicon substrate.

Abstract: An improved DMOS power transistor (20) with a single p-body implant (12) and including an n-type channel compensating implant (NCCI) (24). The improved DMOS power transistor (20) provides a more favorable trade-off between threshold voltage (VT) and on-state resistance, while increasing the safe operating area (SOA). The NCCI (24) also improves the off-state breakdown voltage, and allows a larger fraction of the gate bias voltage to be supported on the thin gate oxide (32). The present invention can be fabricated using self-aligned fabrication techniques so that the channel length (22) is insensitive to lithography equipment.

Abstract: A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable element by either providing a current flow through the programmable element, or directing a laser beam onto the programmable element. The conductive materials are interdiffused to form an alloy of the conductive materials. A resistance value of the variable resistor is determined, at least in part, by the degree to which the conductive materials are alloyed or interdiffused. The method and structure of the variable resistor prevents ablative damage to adjoining circuit structure, allowing tighter pitch, and has application to digital programmable elements, and to resistance trimming for impedance matching in RF integrated circuits.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

Abstract: In order to divert damaging currents into an electrostatic discharge (ESD) protection device during an ESD event, a tungsten wire resistor is incorporated into a current path connected in parallel with the ESD protection circuitry. The tungsten wire resistor has linear current-voltage (IV) characteristics at low currents, and non-linear IV characteristics at high current levels. The width and length of the resistor is chosen so that the resistor experiences significant self-heating caused by the higher currents generated by the ESD event. At a higher current level, the resistor becomes hot and its resistance increases dramatically. As a result the voltage drop across it increases thus diverting excess current into the parallel connected ESD protection circuitry. This limits the current through the resistor and thereby protects circuit elements in series with the resistor.

Abstract: A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but is electrically coupled with these bit lines. The silicide layer is located over and electrically coupled with the silicon-based layer. Moreover, suicide layer and silicide layer could be replaced by a silicon-base conductor layer, and are directly electrically coupled with some separated doped regions that located inside a substrate.

Abstract: A memory cell has two cross-coupled inverters each formed from a load transistor and a drive transistor. In the memory cell, the gates of the load transistor and the drive transistor are electrically coupled to the same gate line having a poly-metal gate structure. In the memory cell, a potential change at a storage node corresponding to an output node of one inverter is transmitted to the gate of the load transistor of the other inverter through a contact resistance at the interface between a silicon layer and a metal layer of the poly-metal structure.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: A layout structure of column pass transistors of a semiconductor memory device, in which the area occupied with the transistors is reduced. Thus, in spite of high integration of the semiconductor memory device and miniaturization of memory cells, column path transistors can be arranged efficiently. In the aforementioned layout structure, the active regions of the column path transistors are longitudinally in perpendicular to the bit line pairs to reduce the area occupied with the total number of memory cells.

Abstract: A semiconductor memory device of the present invention having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving the sense amplifier transistors, wherein the sense amplifier transistors and the sense amplifier driver transistors have gate electrodes dividing a common diffusion layer region formed on the surface of a semiconductor substrate into two, respectively, the gate electrodes being arranged on the boundary of the diffusion layer region.

Abstract: An insulated gate transistor in which nitride oxide film having a nitrogen concentration of 1×1020 (/cm3) or more and containing a halogen element is used as a gate insulator. Because the gate insulator has a nitrogen concentration of 1×1020 (/cm3) or more, boron contained in the gate electrode of the p-type transistor is never diffused into the channel. Further because a halogen element is contained in the gate insulator, transistor conductance is increased and reliability in hot carrier injection is improved. Thus, an insulated gate transistor which has a sufficiently large conductance and which is superior in reliability can be fabricated.

Abstract: The use of doped or undoped rare-earth silicates, according to the formula MSixOy wherein M is a rare-earth element, in semiconductor technology is disclosed. In particular, gadolinium silicate as a gate dielectric of a metal-insulating-semiconductor device is disclosed. The insulator of the metal-insulating-semiconductor device is fabricated by exposing a suitably cleaned and terminated surface of a semiconductor substrate to a simultaneous or sequential flux of rare-earth atoms, silicon atoms and oxygen atoms, and annealing the resulting rare-earth containing layer. The use of higher dielectric constant material, such as provided by the invention, reduces the tunneling current through the device, since layers of greater thickness can be used.

Abstract: A switch includes a conductive region, a membrane, and a dielectric region. The dielectric region is formed from a dielectric material and is disposed between the membrane and the conductive region. When a sufficient voltage is applied between the conductive region and the membrane, a capacitive coupling between the membrane and the conductive region is effected. The dielectric material has a resistivity sufficiently low to inhibit charge accumulation in the dielectric region during operation of the switch.

Abstract: MEM devices are fabricated with integral dust covers, cover support posts and particle filters for reduced problems relating to particle contamination. In one embodiment, a MEM device (10) includes an electrostatic actuator (12) that drives a movable frame (14), a displacement multiplier (16) for multiplying or amplifying the displacement of the movable frame (14), and a displacement output element (18) for outputting the amplified displacement. The actuator (12) is substantially encased within a housing formed by a cover (36) and related support components disposed between the cover (36) and the substrate (38). Electrically isolated support posts may be provided in connection with actuator electrodes to prevent contact between the cover and the underlying electrodes. Such a support post may also incorporate an electric filter element for filtering undesired components from a drive signal.

Abstract: A pressure sensor having a flexible membrane which is moved by an external force, such as pressure from an air flow. The flexible membrane extends over a semiconductor frame having an opening, such that a portion of the flexible membrane extends over the semiconductor frame, and a portion of the flexible membrane extends over the opening. An inherent tensile stress is present in the membrane. One or more strain gage resistors are formed on the portion of the membrane which extends over the opening of the semiconductor frame. The membrane deforms in response to an externally applied pressure. As the membrane deforms, the strain gage resistors elongate, thereby increasing the resistances of these resistors. This change in resistance is measured and used to determine the magnitude of the external pressure. In one embodiment, a Wheatstone bridge circuit is used to translate the change in resistance of the strain gage resistors into a differential voltage.