Abstract: As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directionally etched until an underlying layer is exposed. Then, the substrate is exposed to one or the other or both of: 1) a silicon-containing ambient to form a self-aligned layer of tungsten silicide on sidewalls of the tungsten layer; and 2) a source of nitrogen to form a thin layer of tungsten nitride on sidewalls of the tungsten layer. Such tungsten silicide and/or tungsten nitride layers serves to protect the tungsten during subsequent processing, among which may include sidewall oxidation (e.g. for a polysilicon base conductor layer) and/or the forming of silicon nitride spacers on sidewalls of the gate stack.

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: A light-receiving element having a light-receiving portion is formed on a chip surface. A digital circuit element, an analog circuit element and a circuit adjusting element are provided for cooperatively processing a detection signal produced from the light-receiving element. And, a light-shielding film is provided for selectively setting a light-receiving region on the chip surface.

Abstract: A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.

Abstract: Hithereto, there was a problem involving that the VF and IR characteristics of a Schottky barrier diode were in a tradeoff relationship, and an increase in leak current was unavoidable to implement low VF. In some preferred embodiments, a plurality of P+-type orthohexagonal semiconductor regions are provided in a Schottky junction region. Since they are spaced from one another equidistantly, depletion layers are spread from the P+-type semiconductor regions when a reverse voltage is applied, and are fully filled in an epitaxial layer. As a result, a leak current occurring at the Schottky junction interface can be prevented from leaking to the cathode side. Even when a high leak current occurs, it can be intercepted by the depletion layers, so that the tradeoff relationship between VF and IR can be eliminated. Thus, a low VF can be implemented without consideration for IR.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: A method of fabricating a decoupling capacitor includes depositing a first barrier metal on a conducting metal. The first barrier metal acts as a first electrode of the decoupling capacitor. A dielectric is deposited on the first barrier metal. A second barrier metal is deposited on the dielectric. The second barrier metal acts as a second electrode of the decoupling capacitor. A photoresist is exposed to ultraviolet light. The photoresist is applied on the second barrier metal. A mask is utilized to define an approximate shape of the decoupling capacitor. A portion of the second barrier metal is etched. A quantity of the photoresist is removed.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: A technique in accordance with the invention includes obtaining a semiconductor structure that has a metal disposed thereon. At least a portion of the metal is etched using an etching fluid while sonic energy is applied to the etching fluid.

Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: A leadframe design (and method of forming the leadframe design), comprising: an inner die pad structure lying in a first plane; and an outer die pad structure supported by outer tie bars and connected to the inner die pad by inner tie bars. The outer die pad structure lying in a second plane spaced apart from the inner die pad structure first plane. An outer package surrounds at least the inner die pad structure and the inner tie bars. The outer die pad structure being supported by the outer tie bars. The outer package having outer walls. Lead fingers extend through the outer package outer walls and include respective inner portions extending into the outer package proximate the inner and outer die pad structures.

Abstract: In a semiconductor device 1, a substrate 3 carries the first semiconductor element 2a and the second semiconductor element 2b. The first semiconductor element 2a has a plurality of first pads 4a and a plurality of second pads 4b arrayed along two facing sides of a major surface. The second semiconductor element 2b has a plurality of third pads 4c along sides where the first pads 4a and the second pads 4b are arrayed, and a plurality of fourth pads 4d along sides where the first pads 4a and the second pads 4b are not arrayed. First wirings 8 electrically connect the plurality of third pads 4c to the plurality of fourth pads 4d on the major surface. A plurality of electrodes 5 is arrayed along all the circumferential sides of the major surface of the substrate 3. Second wirings 6a electrically connect the plurality of first pads 4a and the plurality of fourth pads 4d respectively to the plurality of electrodes 5.

Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.

Abstract: A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.

Abstract: Discrete semiconductor packages are described. The discrete package contains: a lead frame pad which has a first surface and a second surface, wherein the second surface which is the opposite surface of the first surface; leads connected to a side of the lead frame pad; a semiconductor chip attached to the first surface of the lead frame pad; a ceramic layer that directly contacts the second surface of the lead frame pad; and a molding material that entirely encapsulates the lead frame pad, the semiconductor chip, and a portion of the ceramic layer, except for a portion of the leads and the second surface of the ceramic layer. Methods for making such discrete packages are also described.

Abstract: A microdevice that comprises a device microstructure (22), a substrate (24), and a silicon cap (30, 130). The device microstructure (22) is attached to the substrate (24). The silicon cap (30, 130) has a base portion (32, 132) and a sidewall (34, 134) that defines a recess (36, 136) in the cap (30, 130). The silicon cap (30, 130) is attached to the substrate (24) such that the recess (36, 136) in the cap (30, 130) houses the device microstructure (22) and forms a hermetically sealed cavity (38) adjacent the device microstructure (22). The silicon cap (30, 130) further has a single crystalline silicon getter layer (40, 140) embedded along its recess (36, 136) for maintaining a vacuum within the cavity (38). There are also methods of making a microdevice containing a single crystalline silicon getter layer (40, 140).

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: Various embodiments of an apparatus for holding and processing semiconductor workpieces are provided. In one aspect, an apparatus is provided that includes a first base, a second base and three elongated members coupled to and between the first base and the second base. The three elongated members are spatially arranged so that a semiconductor workpiece may be positioned therebetween. Each of the elongated members has a first lateral edge, a second lateral edge and at least one radially inwardly projecting member. The at least one radially inwardly projecting member has a third lateral edge, a fourth lateral edge and an upper surface for receiving a portion of the semiconductor workpiece and a lower surface. The third lateral edge is displaced laterally inward from the first lateral edge and the fourth lateral edge is displaced laterally inward from the second lateral edge.

Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.

Abstract: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: The linearity of a wideband RF power transistor amplifier is improved by including output matching circuit and an integrated bias/RF diplexer with RF and video bypassing capacitor network within the transistor package and connected directly to the transistor. By placing the RF and video bypass power supply circuitry within the package and close to the transistor, the input impedance resonance can be increased from approximately 50 MHz to over 125 MHz, thereby reducing AM/PM distortion in the output signal.

Abstract: A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus comprises an integrated circuit (IC) having a plurality of connection pins, a carrier socket configured to carry the IC. The carrier socket protects the pins of the IC from bending. In addition, the carrier socket straightens pins that have been bent prior to placing the IC into the carrier socket.

Abstract: A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package.

Abstract: An integrated circuit heat dissipation system for reducing the number of junctions in packaged integrated circuits thereby decreasing thermal impedance and increasing thermal dissipation efficiency. The integrated circuit heat dissipation system includes a lid attached to a substrate, a cap attached about the lid creating a heat dissipation chamber, and a semiconductor chip attached to the lid by a thermally conductive adhesive. The lid may or may not form a cavity about the semiconductor chip depending upon the substrate utilized. The lid preferably includes a plurality of fins extending from thereof defining a plurality of channels or a plurality of grooves thereby increasing the heat flux of the lid.

Abstract: An internally matching type transistor includes a semiconductor element and an internally matching circuit, and includes a resonant circuit for short-circuiting differential frequencies of two signals of different frequencies is employed as the internally matching circuit. Thereby, intermodulation distortion characteristics in the internally matching type transistor 1 can be improved. Therefore, complicated operations, such as adjustment by externally connecting a resonant circuit to a semiconductor device, can be eliminated, and the internally matching type transistor 1 of improved intermodulation distortion characteristics can be provided as a stand-alone part.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: A multi-chip module that includes a conductive element to serve as an electrical connector for electrically connecting respective electrical contacts of at least two power semiconductor devices and serving as an output connector. The conductive element improving heat transfer from the power semiconductor devices through the top of the module.

Abstract: A window-type ball grid array (WBGA) semiconductor package is proposed, wherein a chip is mounted over an opening formed through a substrate via an adhesive in a manner as to leave regions adjacent to the opening on the substrate uncovered by the adhesive. A first encapsulant is formed to fill the opening and encapsulate bonding wires formed through the opening for electrically connecting the chip to the substrate. A second encapsulant is fabricated to encapsulate the chip. A non-conductive material is applied by a dispensing process to seal gaps formed between the chip and the regions on the substrate, so as to allow the chip to be firmly supported on the substrate during a molding process for fabricating the second encapsulant, and thus to prevent chip cracks from occurrence.

Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.

Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.

Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract: Ultra high-speed multi-level interconnect structure and fabrication process flows are disclosed for a semiconductor integrated circuit chip. The interconnect structures of this invention include a plurality of electrically conductive metallization levels. Each of the metallization levels includes a plurality of electrically conductive interconnect lines. A plurality of electrically conductive plugs make electrical connections between various metallization levels as well as between the metallization levels and the semiconductor devices fabricated on the semiconductor substrate. The invention further includes a free-space medium occupying at least a substantial fraction of the electrically insulating regions within the multi-level interconnect structure surrounding the interconnect lines and plugs. A top passivation overlayer hermetically seals the multi-level interconnect structure.

Abstract: A method is disclosed of forming an air gap using etch back of an inter layer dielectric (ILD) with self-alignment to metal pattern. The method entails forming a first metallization layer deposited on a first dielectric, forming a second metallization layer deposited on a second dielectric, wherein the second metallization layer is spaced apart from the first metallization layer, forming a sacrificial ILD between the first and second metallization layers, forming a diffusion layer over the first and second metallization layers and over the sacrificial ILD, and removing the sacrificial ILD to form an air gap between the first and second metallization layers. This method is particular applicable for dual copper damascene processes.

Abstract: An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Abstract: A multilayer substrate device formed from a base substrate and alternating metalization layers and dielectric layers. Each layer is formed without firing. Vias may extend through one of the dielectric layers such that two metalization layers surrounding the dielectric layers make contact with each other. The vias may be formed by placing pillars on top of a metalization layer, forming a dielectric layer on top of the metalization layer and surrounding the pillars, and removing the pillars. Dielectric layers may be followed by other dielectric layers and metalization layers may be followed by other metalization layers. Vias in the substrate may be filled by forming an assembly around the substrate, the assembly including printing sheets containing a conductive ink and pressure plates for applying pressure. A vacuum may be applied to remove air in the ink. Pressure may then be applied to the printing sheets through the pressure plates.

Abstract: After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stopper 5 which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film 4 which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal 10.

Abstract: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Abstract: A metallization insulating structure, having

Abstract: A porous MSQ film 14 is provided on a semiconductor substrate, and a non-porous MSQ film 17 is formed on top of the porous MSQ film 14. A same film material containing Si, O and C is employed in common to form the porous MSQ film 14 and the non-porous MSQ film 17.

Abstract: A method for forming a copper interconnect with improved via integrity and elimination of via voiding employs a copper seed layer having an alloy element within the seed layer. The alloy element increases the resistance of the copper seed layer to acidic plating chemistry as the vias are filled and as the pulse-reverse wave form is initiated in the electrochemical plating process. The prevention of void formations at the bottom of the via improves the copper filling, with resulting improved electromigration performance, reduced via resistance and improved product speed.

Abstract: A semiconductor device comprises a semiconductor substrate having semiconductor elements integrally formed therein, a wiring layer formed on the surface of the semiconductor substrate, and a conductive connecting plug formed in a through-hole extending through the semiconductor substrate, wherein the connecting plug has a region whose cross section parallel to the upper surface of the semiconductor substrate has an area smaller than the area of each of upper and lower surfaces of the connecting plug.

Abstract: A window-type ball grid array (WBGA) semiconductor package is proposed. A substrate is formed with an opening and a tape attach area around the opening. A polyimide tape having an aperture is applied over the tape attach area, allowing the aperture to be aligned with the opening of the substrate. A chip is mounted over the polyimide tape and electrically connected to the substrate via the opening by bonding wires, wherein the polyimide tape is interposed between the chip and the substrate so as not to leave any gaps between the chip and the substrate. A first encapsulant is formed to fill the opening and encapsulate the bonding wires. A second encapsulant is fabricated to encapsulate the chip. With no gaps between the chip and the substrate, the chip is firmly supported on the substrate during a molding process for fabricating the second encapsulant, thereby preventing chip cracks from occurrence.