Abstract: The present invention is an anti fall device for use with scissor type mechanically actuated lifting devices. The anti fall device comprises a a slave safety hydraulic cylinder capable of supporting a lifting device upon failure of a drive assembly thereby arresting descent of the lifting device when the lifting device is normally stationary or moving upwardly and a drive assembly of the lifting device fails and the lifting device begins to descend uncontrollably. The hydraulic cylinder includes a one way check valve for preventing reverse hydraulic fluid flow upon uncontrolled descent of the lifting device thereby arresting movement of the hydraulic cylinder and arresting descent of the lifting device. The invention also includes an hydraulic velocity fuse in fluid communication with the hydraulic cylinder. The velocity fuse is triggered at a preselected fluid flow rate for controllably lowering the lifting device.

Abstract: A carpet installation device having multiple adjustment features to facilitate carpet installation. These features include a base member of variable length having carpet gripping spikes mounted on the bottom thereof. A winch support mounted on said base member for receiving a winch. The winch includes a winch cable for connecting the winch to a remote anchor. The winch being able to stretch the carpet by pulling said base member toward said anchor. An additional carpet adjusting tool is moveably mounted on the base member for adjusting carpet sections. The carpet adjusting tool includes carpet gripping spikes thereon and linkage operated movement for stretching small sections of carpet between the spikes on the base member and those on the carpet adjusting tool.

Abstract: A level winder is provided for winding cable in a winch system. The winch is suitable for use on a tracked vehicle, such as a snow grooming vehicle, to assist the vehicle in maneuvering on steep inclines. The level winder uses a pivoting pulley assembly to feed cable onto and off of a drum.

Abstract: An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

Abstract: Provided is a light emitting diode and a method of fabricating the light emitting diode. The light emitting diode includes a substrate, an n-type compound semiconductor layer which is formed on the substrate, an active layer which is formed on the n-type compound semiconductor layer, a p-type compound semiconductor layer which is formed on the active layer, an n-type electrode which contacts the n-type compound semiconductor layer, and a p-type electrode which contacts the p-type compound semiconductor layer. Here, a surface of the active layer from which the light is emitted is a continuous curved surface. Thus, the light emission rate of the active layer can be much higher than an active layer in the conventional light emitting diode. As a result, the light which is estimated to be emitted from the light emitting diode increases, and the light is uniformly emitted in all directions.

Abstract: An assembly includes a first electrical circuitry for providing a first electrical signal containing data and a transmitting arrangement, connected with the first electrical circuitry, for receiving the first electrical signal and for converting the first electrical signal into an electromagnetic signal containing at least a portion of the data. The electromagnetic signal has a carrier frequency greater than 300 GHz. The assembly also includes a receiving arrangement for receiving the electromagnetic signal and for converting the electromagnetic signal into a second electrical signal containing at least some of the portion of the data, and a second electrical circuitry connected with the receiving arrangement and configured for receiving the second electrical signal.

Abstract: A top emitting OLED display includes a substrate; an array of OLED light emissive elements formed over the substrate; an encapsulating cover located over the OLED light emissive elements; and a circular polarizer located between the encapsulating cover and the OLED light emissive elements.

Abstract: A dual panel-type organic electroluminescent display device includes a first substrate and a second substrate bonded together to include a plurality of sub-pixel regions, a first electrode on an inner surface of the second substrate, an insulating pattern on the first electrode along a border portion between adjacent sub-pixel regions, a plurality of partition walls on the insulating pattern, a plurality of organic electroluminescent layers, each within one of the sub-pixel regions between adjacent partition walls, a second electrode on the organic electroluminescent layer, a plurality of thin film transistors on an inner surface of the first substrate each within one of the sub-pixel regions, and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, a passivation layer covering the thin film transistors and including a contact hole exposing the drain electrode, and a plurality of connection patterns on the passivation layer, each including a first pattern and a second

Abstract: A first moisture blocking layer formed of a silicon type nitride film such as SiNx or the like is formed over the entire surface so as to cover a drain electrode and a source electrode of a TFT. On the first moisture blocking layer, a first planarization film formed of an organic material is provided. On the first planarization film, a second moisture blocking layer formed of SiNx or the like is provided. In the peripheral region, the second moisture blocking layer extends down on the first moisture blocking layer and is connected with the first moisture blocking layer. Also, a sealing glass is bonded to the second moisture blocking layer using the sealing member. By enclosing the first planarization film by the first moisture blocking layer and the second moisture blocking layer, intrusion of external moisture can be effectively prevented.

Abstract: A new and improved bonding pad having separate areas for probe needle contact and wire bonding in semiconductor packaging technology. The bonding pad typically has a generally elongated, rectangular configuration with a wire bonding area at one end and a probe needle contact area at the other end of the pad. At least one notch mark may be provided on or adjacent to the bonding pad between the wire bonding area and the probe needle contact area for demarcating these areas during chip production.

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.

Abstract: A thin film transistor includes an insulating substrate, an active layer located over the substrate, a gate electrode located over the substrate; and a charge storage region located between the active layer and the gate electrode. The charge storage region includes a tunneling dielectric located adjacent to the active layer, a blocking dielectric located adjacent to the gate electrode and a charge storage dielectric located between the tunneling dielectric and the blocking dielectric. At least one of the tunneling dielectric, the charge storage dielectric and the blocking dielectric comprises a layer having a dielectric constant greater than 3.9, such as a metal oxide layer.

Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Some preferred electronic devices are described that use a layer or pattern of a perovskite cuprate (2125, 2305, 2310, 2315, 2405) such as YBa2Cu3O7−y(YBCO) or Y1−xPrxBa2Cu3O7−y(YPBCO, 0<x<1) over a buffer layer (2120) of lanthanum strontium aluminum tantalate (LSAT).

Abstract: An optoelectronic unit and a transparent conductive substrate of the same are disclosed. The transparent conductive substrate comprises a transparent plate, a transparent electrode film, an insulation part, and a bounding pad, wherein the transparent electrode film and the insulation part are formed on the transparent plate, the insulation part divides the transparent electrode film into a first transparent electrode film area and a second transparent electrode film area that non-conduct each other, and the bounding pad is formed on the second transparent electrode film area. The optoelectronic unit comprises the aforementioned transparent conductive substrate, an optoelectronic element, and a conductive wire, wherein one electrode of the optoelectronic element is electrically connected to the aforementioned first transparent electrode film area, and the other electrode of the optoelectronic element is electrically connected to the aforementioned bounding pad by the conductive wire.

Abstract: A light emitting device has a substrate, an LED mounted on the substrate. A first transparent layer seals the LED, and a second transparent layer is provided around the first transparent layer. Particles of fluorescent material are included in the second transparent layer. A reflector layer is formed on outside walls except an upper side.

Abstract: Gated field emission devices and systems and methods for their fabrication are described. A method includes growing a substantially vertically aligned carbon nanostructure, the substantially vertically aligned carbon nanostructure coupled to a substrate; covering at least a portion of the substantially vertically aligned carbon nanostructure with a dielectric; forming a gate, the gate coupled to the dielectric; and releasing the substantially vertically aligned carbon nanostructure by forming an aperture in the gate and removing a portion of the dielectric.

Abstract: A feedback-enhanced light emitting device is disclosed. A feedback element coupled to an emissive element allows the emissive element to emit collimated light by stimulated emission. Feedback elements that provide this function may include but are not limited to holographic reflectors with refractive index that varies at least in part periodically and continuously.

Abstract: The principal surface of a substrate made of group III-V compound semiconductor is about (100) plane. A light emitting lamination structure is disposed on the principal surface. The light emitting lamination structure includes a quantum well layer made of group III-V mixed crystal semiconductor containing In, a pair of carrier confinement layers made of semiconductor material having a band gap wider than the quantum well layer and sandwiching the quantum well layer, and a pair of clad layers made of semiconductor material having a band gap wider than the carrier confinement layers and sandwiching the quantum well layer and the carrier confinement layers. A difference of 100 meV or larger exists between an energy level of the carrier confinement layers at a conduction band lower end and a ground level of an electron in the quantum well layer.

Abstract: Multiple board fiber optic modules and methods related thereto. Fiber optic modules include one or more vertical printed circuit boards and/or one or more horizontal printed circuit boards and/or one or more slanted printed circuit boards. The one or more printed circuit boards are parallel to optical axis of one or more optoelectronic devices such as a receiver or transmitter. The one or more printed circuit boards may include a ground plane to minimize electrical cross talk. A shielded housing or cover provides shielding for electromagnetic interference. The base or shielded housing or cover may include a septum to separate the fiber optic modules into a first side and a second side and provide additional shielding to minimize crosstalk. Horizontal, vertical, and N×N arrays of fiber optic channels in fiber optic modules. Fiber optic modules including a mini back plane for edge connecting printed circuit boards.

Abstract: A structure member is used wherein a circuit board is connected to a solid-state image pickup element and placed between a portion of the structure member to which the solid-state image pickup element is attached, and another portion to which a light-transmitting member is attached, and the circuit board is sealed integrally into the structure member. The solid-state image pickup element is attached to a through-opening portion 1C, and a light-transmitting member is attached so as to cover the through-opening portion 1C with being separated from the solid-state image pickup element by a predetermined distance. In a process of molding the structure member, the circuit board is integrally molded, whereby the manpower can be reduced, and the structures of the attaching portions can be simplified to miniaturize the device.

Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a transparent conductive substrate, an optoelectronic element, and a base. The transparent conductive substrate comprises a transparent plate, a transparent electrode film formed on the transparent plate, and an insulating part formed on the transparent plate. The insulating part divides the transparent electrode film into a first transparent electrode film and a second transparent electrode film that non-conduct each other. The optoelectronic element comprising a positive electrode and a negative electrode is disposed on the transparent conductive substrate and electrically connected to the first transparent electrode film and the second transparent electrode film individually. The base is formed with an opening that has a reflective surface on the bottom of the opening, and the optoelectronic element is held in the opening in a manner of suspending from or connecting with the bottom of the opening.

Abstract: A LED of flip-chip design comprises a light emitting region and one or more transparent substrates overlying the light emitting region. The light emitting region includes a negatively doped layer, a positively doped layer, and an active p-n junction layer between the negatively doped layer and the positively doped layer. At least one of the substrates has a pyramidal shape determined by (1) the composition of electrically conductive or electrically non-conductive material, (2) the number of side surfaces, (3) the degree of offset of an apex or top surface, and (4) the slope angle of each side surface relative to a bottom surface.

Abstract: A light emitting diode (LED) element includes a LED chip disposed on a base plate and connecting with an electrode circuit thereon via a gold wire; the LED chip is covered by a protective resin lid with fluorescer; the present invention is characterized that a colored lens is disposed on the LED chip sealed by resin with fluorescer; the colored lens is made of polycarbonate and molded through injection by mixing and adding a slight amount of ultra-violet absorbent, golden yellow chromogen, green chromogen, golden red chromogen and blue chromogen; the abovementioned combination changes the light ray generated by the LED chip into a light source with a color temperature at 2000˜5000° K.

Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

Abstract: A semiconductor structure having a textured nitride-based layer. The textured nitride-based layer can be formed above one or more crystalline nitride layers and a substrate, and can be formed into any desired pattern. The semiconductor structure can be incorporated as part of, for example, a field effect transistor, a light emitting diode, or a laser.

Abstract: A light-emitting microelectronic package includes a light-emitting diode (110) having a first region (114) of a first conductivity type, a second region (116) of a second conductivity type, and a light-emitting p-n junction (118) between the first and second regions. The light-emitting diode defines a lower contact surface (120) and a mesa (122) projecting upwardly from the lower contact surface. The first region (114) of a first conductivity type is disposed in the mesa (122) and defines a top surface of the mesa, and the second region (116) of a second conductivity type defines the lower contact surface that substantially surrounds the mesa (122). The mesa includes at least one sidewall (130) extending between the top surface (124) of the mesa and the lower contact surface (120), the at least one sidewall (130) having a roughened surface for optimizing light extraction from the package.

Abstract: A protection device provides to integrated circuits against high voltages. The diode includes a diode connected to provide a safe discharge path for the high voltage currents. The diode is configured so that in reverse bias breakdown occurs across an area portion of its active junction. The device can dissipate a large amount of ESD energy in a minimal area.

Abstract: The present invention provides for variable-range hydrogen sensors and methods for making same. Such variable-range hydrogen sensors comprise a series of fabricated Pd-Ag (palladium-silver) nanowires—each wire of the series having a different Ag to Pd ratio—with nanobreakjunctions in them and wherein the nanowires have predefined dimensions and orientation. When the nanowires are exposed to H2, their lattace swells when the H2 concentration reaches a threshold value (unique to that particular ratio of Pd to Ag). This causes the nanobreakjunctions to close leading to a 6-8 orders of magnitude decrease in the resistance along the length of the wire and providing a sensing mechanism for a range of hydrogen concentrations.

Abstract: Vertical field effect transistors are fabricated by depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microelectronic substrate. Source and drain regions are formed at respective opposite ends of the vertical channel, and an insulated gate is formed adjacent the vertical channel. More specifically, a first doping layer is formed on a microelectronic substrate, an intermediate layer is formed on the first doping layer opposite the substrate and a second doping layer is formed on the intermediate layer opposite the first doping layer. A trench is then formed in the first doping layer, the intermediate layer and the second doping layer, the trench including a trench sidewall. The trench sidewall is lined with a conformal amorphous silicon layer.

Abstract: A dual port memory cell is provided. The dual port memory cell includes a storage cell. A first bitline pair defining access to the storage cell by a first port and a second bitline pair defining access to the storage cell by a second port are defined. Each bitline of the first and second bitline pairs is defined from metallization line features, and the first bitline pair is defined on one side of the storage cell and the second bitline pair is defined on the other side of the storage cell. The bitlines of the first port are physically separate from the bitlines of the second port.

Abstract: A carbon nanotube product formed from a metallic catalytic particle and single-walled carbon nanotubes deposited thereon. The catalytic particles preferably contain at least one metal from Group VIII, including for example Co, Ni, Ru, Rh, Pd, Ir, and Pt, and at least one metal from Group VIb including for example Mo, W and Cr. The metallic catalytic particle preferably further comprises a support material such as silica. The carbon nanotube product is preferably formed by exposing the metallic catalytic particle to a carbon-containing gas at a temperature sufficient to form the single-walled nanotubes as a primary portion of a solid carbon product on the metallic catalytic particles.

Abstract: A contactor is used for testing an integrated circuit electronic component provided with a plurality of electrodes. The contactor includes an insulating base material provided with holes formed at positions corresponding to the electrodes, a first conductive layer having contacts which are plastically deformed portions of the first conductive layer, and reinforcement members provided on the contacts on a first surface of the contacts. The first surface of the contacts is facing towards the holes. The contacts are provided at positions corresponding to the electrodes for enabling an electrical connection to the electronic component and are protruded from the insulating base material.

Abstract: The invention relates to an image sensor device comprising a substrate, formed in CMOS technology, in particular, with an integrated semiconductor structure (ASIC) and, arranged above that, an optically active thin-film structure comprising in each case at least one layer made of doped and undoped amorphous silicon, spatially adjacent pixels in each case being formed in the horizontal plane, which pixels each have an optoelectronic transducer for converting incident light into an electric current proportional to the incident quantity of light and also a charge store assigned to the optoelectronic transducer, the charge state of which charge store can be varied in a manner dependent on the light incident on the assigned optoelectronic transducer.

Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.

Abstract: A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.

Abstract: A base of an optoelectronic device is disclosed. The present invention comprises an opening and a reflective surface. The base of the optoelectronic device incorporates with a transparent conductive substrate and an optoelectronic element to construct the optoelectronic device, wherein the optoelectronic element is disposed on the transparent conductive substrate, and the opening is used to hold the optoelectronic element. Moreover, the transparent conductive substrate is placed on the top of the opening, and the reflective surface is located at the bottom in the opening.

Abstract: A ferroelectric subassembly for an integrated circuit includes a second layer lying between and in contact with first and third layers. The second layer comprises a ferroelectric material while the first and third layers comprise capacitor electrodes in contact with the second layer. At least a portion of the first layer contacting the second layer has the same crystal structure as the second layer. The first layer acts as both a seed layer for the ferroelectric material and as a capacitor electrode. One or both of the first and third layers may comprise LaNiO3 (LNO). The second layer may, for example, comprise lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT) or SrBi2TaO9 (SBT) or an appropriate combination thereof. Any lattice mismatch between the first and second layers and/or between the second and third layers may be less than about 5 percent.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying subs regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in the vicinity of a surface of a substrate, first and second impurity regions, acting as a source and a drain in operation, formed in the vicinity of the surface of the substrate sandwiching the channel forming region between them, a gate insulating film stacked on the channel forming region and having a plurality of films, and a charge storing means that is formed in the gate insulating film dispersed in the plane facing the channel forming region. A bottom insulating film includes a dielectric film that exhibits a FN type electroconductivity and makes the energy barrier between the bottom insulating film and the substrate lower than that between silicon dioxide and silicon.

Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

Abstract: A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. The minimum marginal width of an impurity diffusion layer is defined to reduce by a given width. The reduced width of the impurity diffusion layer is compensated for through a silicon growth layer formed on the top of a device isolation film having a relatively higher degree of freedom than the bottom of the device isolation film. Thus, the degree of integration in the semiconductor device can be improved while keeping intact the minimum marginal width of the impurity diffusion layer.

Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m: and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

Abstract: An NROM memory cell is of a planar configuration without an additional oxidation being affected for the fabrication of the bit line oxide. The ONO layer is provided as a memory layer and is disposed with a uniform thickness on the semiconductor material of the source and drain regions and of the channel region, so that the ONO layer forms not only the gate dielectric, but also the insulation of the bit lines from the word lines or the gate electrode.

Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Abstract: A double-side IGBT (DIGBT) phase leg architecture that uses the DIGBT as a substitute for a free wheeling diode to achieve reduced turn-on loss and reduced reverse recovery peak current during turn-on is described and characterized. Approximately a 50% reduction in reverse recovery peak current and an 80% reduction in recovery charge are achieved. In addition, low power dissipation (≈1 A current level) protection circuitry is described that can be incorporated into the DIGBT phase leg architecture to allow the flow of reverse current even if the gate driver circuit is disabled so that conventional high current free wheeling diodes are not required to provide protection.

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.