Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.

Abstract: In order to apply a predetermined voltage to a silicon layer (3) to thereby control a threshold voltage, a second gate electrode (5) is provided on the surface of the silicon layer (3) with a gate oxide film (insulating layer) (4) interposed therebetween so as to fall within the same surface of the silicon layer (3) as a surface on which a source (7) and a drain (8) placed in the silicon layer (3) and a first gate electrode (6) are disposed.

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract: Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.

Abstract: A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided. The device includes (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta2O5, Ta2(O1-xNx)5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta2O5)r—(TiO2)1-r wherein r ranges from about 0.9 to 1, a solid solution (Ta2O5)s—(Al2O3)1-s wherein s ranges from 0.9 to 1, a solid solution of (Ta2O5)t—(ZrO2)1-t wherein t ranges from about 0.9 to 1, a solid solution of (Ta2O5)u—(HfO2)1-u wherein u ranges from about 0.9 to 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (b) a gate electrode having a width of less than 0.

Abstract: A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than in a side contacting the gate electrode.

Abstract: Ferromagnetic semiconductor-based compositions, systems and methods that enable studies of the dynamics and magnetoresistance of individual magnetic domain walls, and which provide enhanced magnetic switching effects relative to metallic ferromagnets. Aspects of the present invention are enabled by recent studies of the Giant Planar Hall effect (GPHE), and in particular GPHE in (Ga,Mn)As-based devices. The GPHE generally originates from macro- and micromagnetic phenomena involving single domain reversals. The GPHE-induced resistance change in multiterminal, micron-scale structures patterned from (Ga,Mn)As can be as large as about 100&OHgr;, four orders of magnitude greater than analogous effects previously observed in metallic ferromagnets. Accordingly, recent data provide sufficient resolution to enable real-time observations of the nucleation and field-induced propagation of individual magnetic domain walls within such monocrystalline devices.

Abstract: Provided is a solid state image pickup element which can exponentially reduce the in-plane photoelectric conversion portion characteristic distribution that is created in forming color filters by a common photolithography technique and which, when color filters are formed by split exposure, can reduce image non-uniformity between exposure regions in a picked-up image, and a method of manufacturing the same. The method includes: applying negative type color resist for forming first color filters onto an entire surface of a given film; forming the first color filters by irradiation of given portions with exposure light and by subsequent development; applying negative type color resist for forming second color filters onto the entire surface of the first color filters while covering the first color filters; and forming the second color filters by irradiating an area smaller than a region that is surrounded by the first color filters with exposure light and by subsequent development.

Abstract: Micromirror devices, especially for use in digital projection are disclosed. Other applications are contemplated as well. The devices employ a superstructure that includes a mirror supported over a hinge set above a substructure. Various improvements to the superstructure over known micromirror devices are provided. The features described are applicable to improve manufacturability, enable further miniaturization of the elements and/or to increase relative light return. Devices can be produced utilizing the various optional features described herein, possibly offering cost savings, lower power consumption, and higher resolution.

Abstract: An anti-reflection film that is an optical film, at least has a hard coat layer, and a low-refractive-index layer containing a binder polymer, on a transparent support, wherein said hard coat layer and/or said low-refractive-index layer contains: (a) a hydrolysate of an organosilane in which a hydroxyl group or a hydrolysable group is directly bonded to silicon, and/or a partial condensation product thereof; and (b) at least one metal chelate compound of an alkylalcohol, and a compound of R4COCH2COR5, in which R4 is an alkyl group, and R5 is an alkyl or alkoxy group, as ligands, and a metal selected from Zr, Ti and Al, as a central metal.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A CMOS image sensor is disclosed which has a photodiode formed by implanting ions into an area of a substrate. The photodiode surface area corresponds to about 15% to 40% of the surface area of a photoreceptor part region of the sensor. Thus, the capacitance associated with the photodiode is reduced relative to prior art photodiodes, and, thus, the output signals generated by the detected light are increased. Further, by reducing the size of the photodiode in manufacturing the CMOS image sensor, the junction region is reduced to thereby improve the absorption efficiency of light and high integration of the CMOS image sensor can be achieved to thereby prevent deterioration of device characteristics.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. Initial dielectric layers are formed on a semiconductor substrate (10). The initial layers are removed in regions of the substrate and a third dielectric layer (160) is formed in these regions. Forming the third dielectric layer (60) modifies the initial dielectric layers and results in final dielectric layers (170, 180). MOS transistors are then fabricated using the dielectric layers (160) (170, 180).

Abstract: A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to extend from the front surface to the back surface of the substrate, and first and second MOSFETs formed on opposite sides of the isolating region, respectively.

Abstract: In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the resistor material having an initial width determined by a width of the channel. The stencil structure has been adapted to receive a planarizing material that protects against reduction of the initial width of the resistor material during subsequent process steps for removing the stencil structure. A head mask overlays an end portion of the thin film resistor and a dielectric overlays the head mask, the dielectric defining a via formed in the dielectric above a portion of the head mask. A conductive material has been deposited in the via, coupled to the portion of the head mask and electrically connecting the thin film resistor to other components of the integrated circuit.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A vertical resistor structure with a variable resistance is realized by biasing an adjacent control junction through a shallow trench isolation (STI) structure, thereby forming a depletion layer in the resistor region and varying its resistance. A vertical FET structure which is based on the foregoing vertical resistor structure, and which has a control junction isolated by a base region, can induce an accumulation or depletion layer for turn-on or turn-off operation. A band-gap voltage reference circuit is described using either two such vertical n-channel FET structures (in an n-well) with complimentary control junctions (a p+ junction and an n+/p-base junction) or two such vertical p-channel FET structures with complimentary control junctions (an n+ junction and a p+/n-base junction). The fabrication methods for vertical FETs are compatible with existing CMOS technology.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the microstructure of the substrate cause the bending of the substrate, in one or more propagation directions.

Abstract: To provide a semiconductor device capable of corresponding to an applied bending stress by flexibly changing its shape, and to provide a semiconductor device module, a manufacturing method of the semiconductor device, and a manufacturing method of the semiconductor device module. In a silicon substrate whose front surface is provided with an element forming layer having an element forming region where a semiconductor element is formed, a groove is formed in a portion of the rear surface of the silicon substrate corresponding to a region of the element forming layer where a semiconductor element is not formed.

Abstract: An IC chip has externally and selectively cuttable members F1-F3, which can be cut, or cut open, at more than one cuttable points C1 and C2. So long as at least one of the multiple cuttable points C1 and C2 remains cut open, the cuttable member works as a cut member. Thus, a cut member has an exceedingly small probability that it is short-circuited by particles in an ACF or by dust.

Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

Abstract: In a lead frame, a die-pad is delimited for a semiconductor element to be mounted thereon, a plurality of leads are arranged along the periphery of an area to be ultimately separated as a semiconductor device for the die-pad, and furthermore, a conductor portion for power/ground terminal is formed around the die-pad in the area between the die-pad and the leads corresponding to the die-pad. The die-pad, the leads, and the conductor portion for power/ground terminal are supported by an adhesive tape. The conductor portion for power/ground terminal is formed in the form of a single or double rings around the corresponding die-pad, or formed to partially surround the corresponding die-pad. The conductor portion for power/ground terminal is connected to at least one lead among the plurality of leads.

Abstract: A COF tape carrier includes a resist formed on the COF tape carrier. The resist has portions that define a resist opening within the resist so that a semiconductor element is mounted on the COF tape carrier in alignment with the resist opening. The COF tape carrier also includes ridges and valleys formed within the resist opening, the ridges and valleys extending in directions oblique to a perimeter of the resist opening. Inner leads are provided in the resist opening and have portions that extend in a direction oblique to the perimeter. The semiconductor element may include a surface, and ridges and valleys. The surface has perimeters that define the surface. The ridges and valleys are formed on said surface, each of the ridges and valleys extending in directions oblique to the perimeters.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A semiconductor chip and connection ends of corresponding external electrode terminals are encapsulated with a glass based sealing material, and the semiconductor chip includes a wide gap semiconductor element, and the electrodes of the semiconductor chip are connected to the end portions of the external electrode terminals by a silver based brazing member and/or pressure contact.

Abstract: A semiconductor device includes two semiconductor chips that are interposed between a pair of radiation members, and thermally and electrically connected to the radiation members. One of the radiation members has two protruding portions and front ends of the protruding portions are connected to principal electrodes of the semiconductor chips. The radiation members are made of a metallic material containing Cu or Al as a main component. The semiconductor chips and the radiation members are sealed with resin with externally exposed radiation surfaces.

Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.

Abstract: An semiconductor device (100) comprising a first semiconductor die (120) and a leadframe (200). The leadframe includes a first laminate (210) having a bottom surface formed with a lead (220) of the semiconductor device, a second laminate (230) overlying the first laminate for mounting the semiconductor die, and an adhesive tape (250) for attaching the first and second laminates.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 &mgr;m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: A semiconductor device includes semiconductor chips, a first conductive pattern, an external terminal and an encapsulating resin. Each of the semiconductor chips has a front side formed with integrated circuits and a back side. The semiconductor chips are stacked each other. The first conductive pattern electrically connects the integrated circuits. The external terminal is electrically connected to the first conductive pattern. The encapsulating resin encapsulates the semiconductor chips and the first conductive pattern.

Abstract: A die wire bonded to a semiconductor substrate includes insulated signal wire, insulated power wires and uninsulated ground wires between the die and the semiconductor substrate. A conductive material is provided over the signal, power and ground wire bonds which provides an electrical connection between the uninsulated ground wires. The conductive material follows the same profile as the wire bonds and provides a controlled impedance environment for the signal wirebonds.

Abstract: A polygonal nut 5 for receiving a clamping bolt 7 is securely inserted in a nut insertion hole 6 which is formed in the thin portion 1a of the resin case 1, and the polygonal nut is engaged with an inner surface 6a of the nut insertion hole 6. The inner surface 6a of the nut insertion hole 6 has a round-shaped notch concave portion 6b formed at a position confronting to a corresponding corner portion 5b of the polygonal nut 5 so that the corner portion 5b of the polygonal nut 5 is not in contact with a resin case member to thereby prevent the resin case from being cracked.

Abstract: It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate.

Abstract: The problem of the present invention is to provide an insulation film capable of highly universal use for the production of semiconductor packages of different sizes and shapes.

Abstract: The invention encompasses microelectronic package lids, heat spreaders, and semiconductor packages comprising microelectronic lids or heat spreaders. In particular aspects of the present invention, a microelectronic lid comprises a material having a rectangular peripheral shape that defines 4 peripheral sides. Further, the lid has projecting peripheral rails along less than all of the peripheral edge. For instance, the lid can have projecting peripheral rails along only 2 of the sides. Alternatively, such microelectronic lid can be described as comprising a generally rectangular shape defining four peripheral edges, with two of the edges having a greater thickness than the other two edges.

Abstract: A heat spreader including a plurality of carbonaceous particles present in an amount of at least about 50% by volume of the heat spreader. A non-carbonaceous infiltrant is also present in an amount of at least about 25% by volume of the heat spreader, the non-carbonaceous infiltrant including an element selected from the group consisting of Cu, Al and Ag. In another aspect, the carbonaceous particles may be sintered or fused directly to one another. The heat spreader can be incorporated into a cooling unit for transferring heat away from a heat source, which includes a heat sink with the heat spreader disposed in thermal communication with both the heat sink and the heat source.

Abstract: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles may be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material is then introduced which substantially fills the remaining voids and should have favorable thermal properties as well as form chemical bonds with the diamond. Alternatively, the packed diamond may be subjected to ultrahigh pressures over 4 GPa in the presence of a sintering aid. The resulting diamond heat spreader has diamond particles which are substantially sintered together to form a continuous diamond network and small amounts of a sintering agent.

Abstract: A semiconductor device includes two semiconductor chips that are interposed between a pair of radiation members, and thermally and electrically connected to the radiation members. One of the radiation members has two protruding portions and front ends of the protruding portions are connected to principal electrodes of the semiconductor chips. The radiation members are made of a metallic material containing Cu or Al as a main component. The semiconductor chips and the radiation members are sealed with resin with externally exposed radiation surfaces.

Abstract: A package substrate having pads for receiving an integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. In this manner, additional structures such as solder on the pads do not need to be added, and coined, in order to ensure a minimum gap between the package substrate and the monolithic integrated circuit. The pads may be formed of at least one of copper, nickel, and gold. Also described is a packaged integrated circuit having a package substrate with pads for receiving a monolithic integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. The monolithic integrated circuit is attached to the pads with solder bumps.

Abstract: The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire.

Abstract: The present invention provides an integrated circuit having at least one elastically deformable elevation (11) on a circuit substrate (10) of an integrated circuit; a contact-making device (13) on the elevation (11) for providing an electrical link; a rewiring device (12, 14, 15) for electrically connecting an active semiconductor section of the integrated circuit (12) to the contact-making device (13); the rewiring device (12, 14, 15) being formed in ring-shaped fashion around the flexible elevation (11) at the foot of the elevation (11), and this ring (15) being electrically conductively connected to the contact-making device (13). The present invention likewise provides a method for producing a composite comprising a tested integrated circuit (10) and an electrical device (16).

Abstract: An semiconductor chip package for image sensor includes an semiconductor chip for image sensor, a base member with a groove to that the semiconductor chip is mounted therein, a lead formed through the base member and spaced apart from the semiconductor chip, a conductive connecting member for electric connection between the lead and the semiconductor chip, and a transparent seal material formed in the groove for sealing the semiconductor chip for image sensor and the conductive connecting member, wherein an upper surface of the seal material is parallel with an upper surface of the semiconductor chip.

Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating film including a first insulating film formed above the substrate and having a relative dielectric constant smaller than 2.5 and a second insulating film formed to cover the first insulating film and having a relative dielectric constant larger than that of the first insulating film, and a buried wiring formed within the interlayer insulating film. A bottom portion of the second insulating film is buried in the first insulating film at a number of points.

Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.