Abstract: A light consolidating system is provided for converging light emitted from at least one lamp positioned at the focus of an ellipse. A light guiding means is provided in the system for guiding the converged light to the output side. The system is characterized by the focusing feature of the ellipse lamps and therefore increases the efficiency of consolidating light.

Abstract: A lampshade assembly comprises a lampshade and a connection mechanism. The lampshade has a plurality of lampshade pieces. The connection mechanism has a plurality of connecting rods each of which is respectively attached to the lampshade pieces. The connection mechanism further comprises an upper cap, a first fitting piece, a fitting set and a spring. When the spring is stretched outwardly to separate the upper cap from the first fitting piece and then stack the lampshade pieces. When the lampshade pieces are assembled, the connecting rods radiate around a circle. Since the space occupied by the lampshade assembly is reduced, the packing cost and the transport cost are reduced.

Abstract: A decorative lamp shade design element for use with a table or floor lamp, a ceiling or wall mounted lighting fixture or other lighting fixture where the shade is comprised of a man's or woman's dress or casual hat with a suspension mechanism mounted within the hat such that the hat shade is so positioned over the lighting element as to shade and direct the light from the element in a pleasing and useful manner.

Abstract: A track lighting attachment for effectively directing light emitted from a track light and reducing the light wash. The track lighting attachment includes a cylinder member, a first aperture and a second aperture within the cylinder member, a first clip member positionable within the first aperture and a second clip member positionable within the second aperture. The first clip member and the second clip member are formed to engage the outer lip portion of a light unit of the track lighting system. The light emitted from the light unit thereby directed through the lumen of the cylinder member thereby focusing the light beam upon a specific location and reducing the light wash.

Abstract: A lamp that utilizes a lamp base locking ring to secure a lamp base shell to a lamp. A hollow light transmitting body terminates in a neck that includes threads and a keyway. A lamp base locking ring having an indentation that extends into to the keyway is disposed around the circumference of the neck. A lamp base shell is threaded onto the threads of the neck. The lamp base shell is mechanically fastened to the lamp base locking to secure the lamp base shell to hollow light transmitting body.

Abstract: A luminaire includes a base, a frame supporting a lamp, an optical assembly and an arm connecting the base and the frame. The arm has opposite first and second terminal ends rotatably coupled to the base and the frame, respectively, first and second opposite sides extending between the first and second terminal ends, and first and second actuating members unitary with the arm. The first actuating member extends from the first side at the first terminal end and the second actuating member extends from the second side at second terminal end. The first actuating member rotates the arm with respect to the base about a first axis and the second actuating member rotates the frame with respect to the arm about a second axis, perpendicular to the first axis.

Abstract: A modular pole system and light fixture is disclosed wherein the modular pole system is comprised of an internal skeletal structure and an external plastic shell. The external plastic shell may slide over the assembled internal skeletal structure and may be comprised of a singular unit. The internal skeletal structure may be comprised of an upwardly extending tapered pole which is held in place by a base and post which also provides a static structure acting as a passive defense mechanism.

Abstract: A lamp mounting apparatus engages a temporal fastening pin with a temporal fastening clip to prevent a positioning surface of a lamp unit from moving in such a direction as to depart from a flange, so that the lamp unit can be kept positioned.

Abstract: A vehicular lamp used in a vehicle, includes: alight source for emitting light in accordance with power given thereto; a lamp body for accommodating the light source and protecting the light source from water; a first resistor provided in the outside of the lamp body and connected in series with the light source; and a current limiting circuit, provided in the inside of the lamp body, for preventing an excess current supplied to the light source in a case where dump surge occurs in a supplied voltage or current to be supplied to the light source.

Abstract: The present invention comprises a lamp assembly with a boot hermetically cohered to the housing. The housing comprises a thermoplastic polymer and the boot comprises a thermoplastic elastomer. The boot is cohered to the housing by welding. According to one embodiment, the boot is sonic or vibration welded to the housing. The present invention may be used in the production of a wide range of lamp assemblies, including vehicle headlamp assemblies.

Abstract: A translucent member is arranged so as to cause light originating from an LED light source oriented toward the front of a lamp to enter the translucent member. Outgoing LED light that has entered the translucent member is reflected rearward by a front surface, and then the light is reflected forward by a rear surface, to thereby exit forward of the lamp from the translucent member. At that time, an area on the front surface located in the vicinity of an optical axis Ax is formed as a normal reflection section subjected to reflection surface treatment. The other area of the front surface is formed as an internal reflection section which causes the outgoing LED light to undergo internal reflection. A plurality of reflection elements are formed on the rear surface of the translucent member so as to cause the outgoing LED light reflected from the front surface to enter the internal reflection section at an incidence angle which is smaller than or equal to a critical angle.

Abstract: An self-contained illuminator capable of being manufactured in a plurality of shapes is built around a circuit board. The circuit board enables attuning the position of the light emitting diode assemblies to maximize light output and also provides for mounting the electrical componentry needed to control and supply the required amount of electrical energy to the LED assemblies. The circuit board also provides a substrate for a layer of the self-hardening flowable medium used to hold the light emitting diodes in their attuned position.

Abstract: The invention relates to a lighting element comprising an insulating plate (2) and two rows of LEDs (3, 4) which are fixed to the top and bottom of said plate. The LEDs are connected in series or/in parallel and both ends of said plate are provided with electrical contacts (5, 6) which are connected to the LED branches and which are intended to be fixed to the electrical supply terminals (9, 10).

Abstract: A decorative light assembly comprises a plurality of optical fibers formed into a bundle having a length greater than one inch, the bundle having a first end for receiving light, and a second end that is fused for providing the received light as decorative illumination. The decorative light assembly is for use on, e.g., Christmas trees, windows, doors, etc.

Abstract: The present invention related to an installation structure for illuminating pen, which is an melioration to the conventional pens. A press section is fixed on top of the pen which controlling the extrusion and retraction of the refill. A flexible handling section is designed at the bottom section of the pen, such easy-gripped design gives compatible handling moderation. The characteristic of present invention is where the pen is fixes with a build-in illuminant, the fixture will then liberates the illuminant continually by pressing the press section hence such invention does not only fit the stationary purpose design, but also bring in new-day leading fashion ideas.

Abstract: A switching power supply unit of the present invention a timing generating circuit (121) which receives a first control signal formed by a rectifier-transistor driving circuit (104), forms a second control signal based on the first control signal, and supplies the second control signal to a control electrode of the rectifier transistor (113).

Abstract: Provided is a DC-DC converter which is capable of obtaining a stable output irrespective of the fluctuation of the power source voltage and ensuring the reliability of a device. The DC-DC converter configured such that a current of a primary coil of a boosting transformer supplied from a power source unit is intermittently caused to flow through the converter by a power MOS-FET and an ignition capacitor is charged with electricity through a rectifier diode using the voltage of a secondary coil of the boosting transformer boosted by the flyback voltage of a coil, includes a current detecting circuit for detecting a drain current of the power MOS-FET, and a control circuit for, when the drain current detected by the current detecting circuit exceeds a predetermined threshold, turning off the power MOS-FET for a fixed period of time, and then turning on the power MOS-FET again.

Abstract: A power supply system for outputting low voltage electrical power from a high voltage power source includes an isolation-type power conversion device, such as a transformer having a primary high voltage side and an isolated secondary low voltage side. The low voltage side is interconnected with a power output arrangement, which is adapted to supply low voltage power to a load, which may be in the form of an electric blanket or the like. A switching arrangement is interconnected with the high voltage primary side of the power conversion device, for providing intermittent operation of the power conversion device. The period of intermittent operation of the power conversion device is controlled via a control arrangement, to vary the power output from the low voltage secondary side of the transformer and thereby to the electrical load.

Abstract: A transformer reset circuit includes a first capacitor serially connected to a transformer winding, a rectifier connected in parallel with the first capacitor and the transformer winding, a second capacitor, an auxiliary switch connected in series with the second capacitor to form a series circuit connected in parallel with the rectifier, and a switch control circuit. The switch control circuit can turn on the main switch and turn off the auxiliary switch to release magnetizing energy stored in an inductor to charge the first capacitor. The auxiliary switch can be turned on and the main switch can be turned off to transfer the magnetizing energy stored in the inductor and the energy stored in the first capacitor to the second capacitor. After the energy stored in the inductor is dissipated, the second capacitor charges the inductor and the first capacitor to reverse the magnetic field in the inductor so as to reset the transformer.

Abstract: Power supply sequencing systems and methods are disclosed. In one embodiment, a programmable charge pump supplies a programmable current source, which drives an external NFET that controls whether power is supplied to a device or a portion of circuitry. The maximum voltage and the turn-on ramp rate supplied to the NFET are programmable and, therefore, the NFET can be operated safely within its rated limits without requiring external protection devices. If a high-voltage output terminal is not required to drive an external NFET, the output terminal, in accordance with another embodiment, may be configured to function as an open drain logic output terminal.

Abstract: At least upper order stages of a multi-stage charge pump contain respective drive signal recovery circuits, that enable the charge pump to operate over a larger voltage range and/or be driven by a very small input voltage. The switch control signal recovery circuit has an auxiliary NFET switch whose current flow path is series-coupled with a Schottky diode between the output voltage of the next lower order stage and a PFET switch drive line. The auxiliary switch controllably clamps the PFET switch drive line at a voltage that differs from the output voltage of the next lower order charge pump stage by the voltage drop across the Schottky diode. This effectively guarantees that the level-shifted line of that stage's transient clamp network will be biased to its appropriate operating voltage level, so that the clamp rail of this stage cannot hang up at a voltage level that is well below the output voltage from the next lower order stage.

Abstract: A controller (130) for compensating reactive power and selected current load harmonics in an unbalanced multi-phase power distribution system. Control current is injected from a multi-phase voltage source inverter (118) into the multi-phase power distribution system as a function of the voltage and current provided by the source inverter 118. The injected current is operative to balance the load seen by the power distribution system including non-linear/distorted and unbalanced loads in each phase. The controller includes an inner loop control processor (216), an outer loop control processor, and an adaptation processor. The adaptation processor (238) is operative to estimate a selected set of predetermined harmonic components in the periodic disturbance which is a function of the unknown system parameters, the source current, the source voltage, and their time derivatives in stationary coordinates.

Abstract: A power supply controller having a multi-function terminal. In one embodiment, a power supply controller for switched mode power supply includes a drain terminal, a source terminal, a control terminal and a multi-function terminal. The multi-function terminal may be configured in a plurality of ways providing any one or some of a plurality of functions including on/off control, external current limit adjustments, under-voltage detection, over-voltage detection and maximum duty cycle adjustment. The operation of the multi-function terminal varies depending on whether a positive or negative current flows through the multi-function terminal. A short-circuit to ground from the multi-function terminal enables the power supply controller. A short-circuit to a supply voltage from the multi-function terminal disables the power supply controller. The current limit of an internal power switch of the power supply controller may be adjusted by externally setting a negative current from the multi-function terminal.

Abstract: A method and apparatus, known as an inverter, for converting a source of DC power such as that from batteries, to an alternating voltage similar to what is available from a standard domestic wall plug, but with substantially less power wasted in the inverter itself at low loads, than prior art inverters. At low loads, the inverter produces an output voltage waveform whose average value, as measured by the magnitude of the integral of each half-cycle of the output voltage waveform, is less than the average value of a half-cycle of a sinusoidal voltage waveform having the same period and same extreme voltages as the output voltage waveform.

Abstract: A split phase DC to AC polyphase inverter having M phases for driving an M-phase load includes, for each phase, N subphases for producing N PWM signals at a carrier frequency. Associated with each of the M phases is one of M averaging transformers. The N PWM signals associated with each one of the M phases is input into the associated transformer. The transformer produces a PWM signal with a frequency equal to approximately N times that of the carrier frequency of that of the N input PWM signals, and with a maximum voltage step equal to the voltage amplitude V of one of the N input PWM signals divided by N. The result is an inverter circuit which produces much lower output current ripple without increasing the total power consumed by the inverter.

Abstract: A DC/DC converter interconnecting a first DC voltage source having a first potential and a second DC voltage source having a second potential and having a stepup/stepdown transformer coupled between the two voltage sources; a controlled switching circuit coupled to the transformer for switching pulsed direct current through the transformer between the voltage sources; and a controller controlling a switching operation of the switching circuit to allow the pulsed direct current to flow between the two voltage sources, whereby current flows between the two voltage sources in dependence on load demands imposed on respective ones of the two voltage sources.

Abstract: A memory device includes a memory cell configured to be coupled to complementary first and second bit lines and a differential amplifier having first and second input terminals and operative to amplify a voltage between the first and second input terminals to produce an output signal. First and second voltage-dependent capacitors are coupled to respective ones of the first and second input terminals, and first and second isolation switches are operative to couple and decouple the first and second bit lines to and from respective ones of the first and second voltage-dependent capacitors. The first and second isolation switches may include respective first and second isolation transistors (e.g., NMOS transistors), and the first and second voltage-dependent capacitors may include respective MOS capacitors.

Abstract: An electron beam emitting apparatus has a first plate with an electron-emitting device 15, and an electrode 8 opposed to the first plate, and the electrode 8 is applied a potential to accelerate electrons emitted from the electron-emitting device 15. In the electron beam emitting apparatus, a potential defining region 9 is provided a surface of the first plate on the electrode 8 side and a first potential defining region forming the potential defining region 9 is provided in a projective area of the electrode 8 onto the potential defining region 9; and, where d represents a distance between the electrode 8 and the potential defining region 9, an additional potential defining region is defined in the range of 0.83d in all directions parallel to the first plate from the edge of the projective area of the electrode 8 onto the potential defining region 9. This stabilizes trajectories of electrons and permits an excellent image to be formed without deviation of light emission positions.

Abstract: An anti-fuse transistor includes a source, a drain and a well connected together, and a gate. A method for programming the anti-fuse transistor includes applying a reference potential to the gate, and applying a high potential greater than the reference potential to the drain of the anti-fuse transistor. A first access transistor is connected to the anti-fuse transistor. The first access transistor includes a drain connected to the source of the anti-fuse transistor, and a source for receiving the high potential. Applying the high potential to the drain of the anti-fuse transistor includes turning on the first access transistor.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.

Abstract: A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film are included, wherein the first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines disposed on a layer overlying the semiconductor substrate.

Abstract: A non-volatile memory device, such as a Programmable Conductor Random Access Memory (PCRAM) device, having an exemplary memory stored state retention characteristic is disclosed. There is provided a method for retaining stored states in a random access memory device generally comprising the steps of programming a memory cell or an array of memory cells by applying a first voltage to the cells and stabilizing the cells by applying a second voltage to the cells, which is less than the first voltage. The second voltage, which acts as a stabilizing voltage, may be a read-out voltage. The second voltage may also be continuously applied to the cells. The second voltage may also be provided as a sweep voltage, a pulse voltage, or a step voltage.

Abstract: The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.

Abstract: A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.

Abstract: A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.

Abstract: The present invention provides a semiconductor memory cell having a semiconductor substrate (1); a trench (5) provided in the semiconductor substrate (1); a floating gate electrode (45) introduced in the trench (5), which electrode is insulated from the trench walls by a first insulation layer (50); a control gate electrode (80) provided in the semiconductor substrate (1) around the trench (5); a second insulation layer (10) provided on the surface of the semiconductor substrate (1); a conductive layer (20) provided on the second insulation layer (10), which conductive layer forms a channel region (35) above the floating gate electrode (45); and a source region (30) and drain region (40) formed in the conductive layer (20) in each case beside the channel region (35). The invention also provides a corresponding fabrication method.

Abstract: A head slider moveable relative to a storage media having a storage layer is disclosed. The disc head slider comprises a read head formed on the head slider, and comprises a first electrical contact layer adapted to carry a sensor current, a second electrical contact layer adapted to carry the sensor current, a read sensor and a bias magnet. The read sensor is configured to carry the sense current perpendicular to plane. The read sensor also has a top sensor edge, and has a bottom sensor edge aligned with the air-bearing surface to access data in the storage disc. The bias magnet magnetically biases the read sensor. Further, the first and second electrical contact layers are made of a material that does not magnetically shield the read sensor.

Abstract: In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits (3; 4). An active word line (AWL) is selected by a multiplexer (7), while inactive word lines (IWL) are clamped to ground during readout.

Abstract: The present invention discloses a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world. Faraday induction is used to provide electromagnetic coupling between adjacent computational elements and between the computational elements with interface elements of the quantum system. Therefore the corresponding magnetic flux acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements of the quantum system.

Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

Abstract: Described is a method for erasing data recorded in a data storage device in which a data bit is written onto a surface by applying a first combination of energy and force to the surface via a tip to form a pit in the surface representative of the data bit by local deformation of the surface. The method comprises applying a second combination of energy and force via the tip to prerecorded deformations of the surface to be erased to substantially level the surface.

Abstract: A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

Abstract: A non-volatile semiconductor memory device is provided, which comprises a memory array comprising memory cells, in which each memory cell is capable of storing data values depending on the voltages thereof, the data values include a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range, and the first data is written in a memory cell of the memory cells, a determination section for determining whether a voltage value of the memory cell is higher or lower than a reference value set between a maximum value and a minimum value of the first voltage range, and a rewrite section for rewriting the first data into the memory cell based on a determination result of the determination section so that a margin between the first voltage range and the second voltage range in the memory cell is enlarged.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: The wrong operation preventing circuit is supplied for preventing such accidents as destruction of data and the like, comprising a memory cell section, a sense amplifier and a operation judgement section. The memory cell section is placed at a furthest position from the sense amplifier, the sense amplifier detects the change of voltage on bit line, and the operation judgement section monitors the output of the sense amplifier and outputs a signal for controlling whether the CPU needs to reset.

Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.