Abstract: The BIOS device (108) or some other secure store of a portable computer (PC 100) or other valuable device stores a password-based security program (302), an encrypted password (306), and an encryption key (304). When the PC is booted, the security program executes first and prompts the user for a password, encrypts it with the stored key, and compares it with the stored password. If the passwords do not match, boot is aborted and the PC is disabled. Only if the passwords do match is boot continued and use of the PC enabled. If this security measure is advertised, theft of the PC is deterred because of the difficulty of accessing or bypassing the password and the security program in the BIOS device. The encrypted password is also registered with a remote trusted certificate authority (TCA 150) or is stored on a local external storage device (250). To establish or change the password, a communication connection is established from the PC to the TCA or storage device.

Abstract: The present invention includes a communication control device that connects directly to at least one camera. Either analogue or digital cameras are connected to the communication control device. The communication control device captures, compresses, digitizes and/or encrypts the photographic images communicated to the communication control device from each camera and then communicates the processed or compressed images through a TCP/IP or other network protocol to a computer for further processing. The device can further bi-directionally communicate common protocols such as RS232 or RS485 protocols over new or existing computer networks using a TCP/IP or other network protocol. This allows for data input devices such as keyboards, magnetic stripe card readers, proximity readers, barcode scanners, document scanners or similar devices to be interfaced directly into the communication control device.

Abstract: A method and apparatus provides hardware-configured wake-up events for a computer operating system compliant with an advanced configuration and power interface (ACPI) protocol without requiring additional hardware. The method and apparatus includes generation of a system management interrupt (SMI) during normal ACPI working-to-sleep transition allowing a basic input-output system (BIOS) circuit to enable additional wake-up events independent of the computer operating system.

Abstract: A device connected to an interface has operational logic and power control logic. The device further has multiple power modes, including a first mode and a second, lower power mode. In the first mode, the operational logic is coupled to the interface, and is able to communicate over the interface. In the second mode, the power control logic is coupled to the interface, and the operational logic is decoupled, and substantially powered down. This provides a low interface power mode. In this mode, the power control logic monitors the interface for command activity. The power control logic returns the device to the first mode when the device must be in the first mode to process or reply to the command. The power control logic thus provides for the restoration of function from a low interface power mode without the need for a special “wake-up” command, thereby making the low interface power mode transparent to the host.

Abstract: A method for causing a host channel adaptor which is involved with a clustered arrangement to hibernate. Before the HCA can hibernate, it is necessary for its clients to hibernate first. Once this is accomplished, all data is stored in memory and the HCA goes into hibernation. It resumes operation when a request is received. The HCA is checked to see if it has been changed and various parameters are examined to determine if an error has occurred which is unrecoverable. If not, the operation of the device is resumed.

Abstract: A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (“GFC”) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Abstract: Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.

Abstract: A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.

Abstract: The invention includes a method to communicate a data packet. At a second input of a variable delay device, a first clock signal having at least one edge is received. At a first input of a detector, a first data packet having data that defines a second clock signal is received. At a second input of the detector, an output of the variable delay device is received. The output of the variable delay device is then compared to the second clock signal to produce an offset signal. The first clock signal is adjusted as a function of the offset signal to produce an output of the variable delay device.

Abstract: An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The oscillator clock circuit operates in several modes selected by an externally writeable control register. The clock circuit synchronizes with the function clock signal or a reference clock signal as selected by the control register. Pre-scalers are employed in two paths to scale the oscillator clock frequency. The clock circuit also includes calibration and test modes selected by the control register.

Abstract: A controller fault recovery system recovers from faults that cause unscheduled stops for a distributed file system operating on an array storage system having multiple controllers. A proxy arrangement protects data integrity in the event of an unscheduled stop on just one controller in the array storage system. An atomic data/parity update arrangement protects data integrity in the event of an unscheduled stop of more than one controller.

Abstract: A host bus adapter for interconnecting a computer system to a storage area network has an embedded processor for processing frames. When frames are received by the processor, it inspects frames for encapsulated write requests and, if encapsulated write request frames are found, de-encapsulates the write request and forwards the write request to a target node of the write request.

Abstract: A process/method for controlling a digital data storage unit including a multiplicity of storage media slots for receiving media storage units, a plurality of media storage units loaded in some of the storage media slots, a plurality of data storage drives each having a unique drive address, a loader mechanism for selectively moving a media storage unit between a storage media slot and one of the plurality of data storage drives, and a storage unit controller connected to at least one host computer. One or more of the data storage drives are reserved as spare data storage drives wherein the spare data storage drives are masked from the host computer such the spare data storage drives are not directly accessible by the host computer. The storage unit controller receives and decodes host commands including a source address corresponding to a storage media slot location, and a destination address corresponding to a data storage drive specified by the host computer.

Abstract: A method and apparatus for minimizing performance degradation resulting from reassignment of data to alternate sectors as a result of a defect within the original sector. For example, when a request for writing data “a” into a sector A is made but the data is written into an alternative sector A′ in an alternative sector area X because the sector A is defective. Therefore, when a write request for writing data “b” into a sector B is made subsequently, re-assignment is performed to a sector B′ subsequent to the alternative sector A′. Similarly, a defective sector C for which a request for writing data “c” is made is re-assigned an alternative sector C′. Thus, the successive data a, b, and c are written into the successive sectors A′, B′, and C′ in the same alternative sector area X, minimizing performance degradation.

Abstract: Described is a method for isolating faults to a correct field replaceable unit (FRU) of a data processing system. When a processor timeout occurs, a fault isolation logic is triggered and checks the boot record to determine if the timeout occurred because of an FRU fault before or after the service processor completed its system initialization. When the timeout occurred because of fault that occurred while the service processor was loading operating system (OS) (e.g., AIX) instructions from the boot device in the input/output (I/O) subsystem, then the FRU callout indicates a boot fault associated with the I/O planar and the CPU (processor) card. When the FRU fault occurred prior to fetching the OS instructions from the boot device or after the service processor completed its system initialization procedures, then the FRU callout is attributed to the processor card and backplane. Attributing boot error faults to incorrect FRUs is therefore substantially eliminated.

Abstract: A method for preserving data resident in a volatile memory of a data storage unit having at least one rotatable disk platter in the event of an interruption of a primary supply power. The method includes monitoring the status of the primary supply power to the data storage unit. Following the detection of a loss of the primary supply power, kinetic energy inherent in the spinning disk platter is converted into electrical energy. Electrical energy derived from the kinetic energy of the disk platter is then utilized to power the data storage unit to write the data in the volatile memory to an outer-most track of the rotatable disk platter.

Abstract: A system and method are disclosed for aiding a field engineer in the field such as at a remote service facility in analyzing a fault log of a malfunctioning machine such as a locomotive. The method includes obtaining data associated with operation of the malfunctioning machine from a user at a second computing unit coupled via a communications network such as the Internet to a first computing unit such as a centrally located server operable to provide data associated with analysis of the malfunctioning machine, and providing at the second computing unit at least one of a diagnosis of and a repair for the malfunctioning machine based on the data associated with the operation of the malfunctioning machine and the data associated with analysis of the malfunctioning machine.

Abstract: A method for testing computer software is described. The method is intended for operation on software which may or may not have been previously subjected to unit and integration tests, to determine if it will meet the specific requirements of an end user. The method is applicable to internally developed, contractor developed, or vendor supplied software. The method includes application in six key process areas. The six key process areas are development of a test plan, development of test cases to support the plan, development of an environment to simulate the technical environment in which the program will operate, test execution in which the tests are executed in a technical environment, compiling and analyzing the results and finally reporting the results in a form whereby the end user can determine both the feasibility of the software system for the specific requirements and any areas where additional testing or modifications are necessary.

Abstract: A recording medium for storing start position information for each zone and a method of managing data using the information. In a disc having a plurality of zones which form a group, and a spare area which is allocated at the start portion or the end portion of the group for replacing defects, when start logical sector numbers of each zone are changed by slipping replacement during initialization or reinitialization, the information is stored in the defect management area to thereby increase the compatibility of the medium. In particular, by the method of managing data using information stored in a defect management area, generation of errors is prevented in reading or writing due to the change of a physical position of a real-recorded file which are caused by wrong calculation of the start logical sector numbers for each zone.

Abstract: Failures within a communications network are compensated for by establishing a set of two or more communications paths across the network between a source node and a destination node. At the source node a status of each one of the set of communications paths is maintained, and the data traffic is load-balanced across those ones of the set of communications paths having an operational status. In the event of failure of a physical network resource, a failure notification message is propagated to the source node, which registers a non-operation status of each path traversing the failed resource. Load-balancing of the data traffic continues across the remaining operational paths. Traffic may be prioritized based on service level agreements and quality of service protection guarantees.

Abstract: A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Abstract: A method for calculating and analyzing redundancies for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region. It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered. A system, preferably for on-chip implementation is also included.

Abstract: An apparatus and method for reliability testing an electrical connector for an unacceptable propagation delay. The propagation delay is detected in a transmitted test signal through the electrical connector in comparison to a reference signal having a known delay. A failure signal occurs in response to the transmitted test signal failing to transition before a corresponding transition in the reference signal. The apparatus and method is extendable to a plurality of conductor paths in the electrical connector, such as a parallel communication digital data bus. Moreover, the known delay in the reference signal is selectable for adjusting an allowable propagation delay criteria for applications with different data rate requirements.

Abstract: An apparatus and method for performing a diagnostic problem determination methodology for complex systems is provided. With the apparatus and method, a diagnostic application for a system may automatically invoke additional diagnostics for child devices and/or siblings of the child devices based on status of the child devices after testing the parent device. This allows for complete testing of a subsystem in a single diagnostic execution resulting in a more complete, accurate analysis of subsystems with complex configurations such as seen with redundant arrays of independent disk drive (RAID) systems.

Abstract: Hardware or software to test a circuit with a set of functional vectors. The invention compares expected results of functional vectors with the actual results of the test circuit. If there is a miscompare, a recursive comparison is done prior to the first clock cycle of the miscompare.

Abstract: The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplaxy embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.

Abstract: An iterative decoding system has a first decoder that decodes coded data and a first weighting circuit that reduces channel effects in the coded data based upon a reliability that the first decoder accurately decoded the encoded data. The first weighting circuit produces improved coded data. A second decoder of the iterative decoding system decodes the improved coded data, and a second weighting circuit additionally reduces channel effects in the improved coded data based upon a reliability that the second decoder accurately decoded the improved encoded data.

Abstract: Systems and methods for augmenting the performance of iterative soft decision-in soft decision-out decoding of block codes with extrinsic information based on multiple parity equations inherent to the block codes. Cyclic shifting of codewords may be applied in the context of iterative soft decision-in soft decision-out decoding to maximize the usefulness of a parity equation corresponding to any particular codeword bit. Soft decisions are determined on a bit-by-bit basis in response to multi-bit symbol measurements. This allows the use of relatively inexpensive bit-based decoders for decoding of multi-bit symbols.

Abstract: Codeword-position-caused encoder latency is reduced by avoiding the requirement for knowledge of the message prior to generating an error detecting or concealing codeword associated with the message. A pseudo error detecting or concealing codeword is inserted in place of the normal error detecting or concealing codeword appropriate for the segment of information to which the error detecting or concealing codeword relates. In order to satisfy the requirement of conventional decoders, the pseudo error detecting or concealing information must match or be appropriate for the segment so that the decoder sees the codeword and message segment as valid or error free. This is accomplished by modifying or perturbing at least a portion of the segment to which the pseudo codeword relates. The invention is particularly useful for maintaining the backward compatibility of audio data encoding formats in which the minimum latency is too long (e.g.

Abstract: An objective of the present invention is to provide a data transfer control device and electronic equipment that reduce the processing overheads of firmware and enable the implementation of high-speed data transfer. When a header CRC error occurs in a data transfer control device in accordance with the IEEE 1394 standard, the header pointer returns to the previous position to invalidate that packet. When Unktcode occurs, the packet is not written to RAM and the packet is invalidated. No reception completed status is generated. A register for holding the header CRC error status is provided. When there is a data CRC error, a data pointer returns the previous position without returning the header pointer. A first mode in which received broadcast packets are invalidated and a second mode in which they are validated may be set so that when a broadcast packet is received in the first mode, that packet is not written to RAM.

Abstract: A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.

Abstract: A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.

Abstract: Forward error correction apparatus and methods are described. A forward errro correction method includes: (a) computing syndromes values; (b) computing an erasure location polynomial based upon one or more erasure locations; (c) computing modified syndromes based upon the computed erasure location polynomial and the computed syndrome values; (d) computing coefficients of an error location polynomial based upon the computed modified syndromes; (e) computing a composite error location polynomial based upon the computed coefficients of the error location polynomial; (f) computing a Chien polynomial based upon the computed composite error location polynomial; (g) performing a redundant Chien search on the computed composite error location polynomial to obtain error location values; and (h) evaluating the computed Chien polynomial based upon the error location values to obtain error and erasure values.

Abstract: Sequentially decoding a plurality of symbol sets of an incoming data sequence with less amount of computation in an application wherein paths in a code tree do not occur equiprobably is disclosed. A code tree is previously memorized which comprises a plurality of paths defined by a plurality of sequences of nodes. A pointer generator is provided for generating a pointer that defines a node that specifies a path in the code tree. A plurality of branch metric generators each generates a metric of a branch which forms part of a path and which is to be examined with a corresponding symbol set of the incoming data sequence. Further, a plurality of path metric generators are provided which respectively receive the branch metrics from the plurality of branch metric generators and respectively generate path metrics using the branch metrics.

Abstract: A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68.

Abstract: A method for operating an automation system and an associated automation system in which all the error-free information is exchanged cyclically with a safety protocol, whereby information losses can thereby be recognized. Data that do not change even in the course of multiple transmissions are transmitted only once.

Abstract: Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.

Abstract: Various embodiments of the invention provide increased speed and decreased computer processing for playing and navigating multimedia content by using two types of data objects for displaying the multimedia content. The first data object type includes rendered multimedia content data for a rendered cache, or rendering instructions for a paint stream cache or a layout cache. The paint stream cache and layout cache can take advantage of increased client processing capabilities. The second data object type provides semantic content corresponding to the rendered multimedia content. The storage medium in which these two types of data objects are contained is referred to as a rendered cache. The semantic content can include locations, sizes, shapes, and target universal resource identifiers of hyperlinks, multimedia element timing, and other content play instructions.

Abstract: A named range defined by a cell address range in a spreadsheet comprises a plurality of cells identified in each dimension by an address, each dimension comprising two directions. An open named range is specifyed to the named range in at least one open direction. A hidden named range with the cell address range of the open named range is expanded by one address in every direction specified as open. In response to user action, at least one direction is selected, the cell address range of the hidden named range is increased by inserting between two consecutive cell addresses, a new address in selected directions, the open named range is updated with the cell address range of the hidden named range shortened by one address in every direction specified as open.

Abstract: A display process is carried out in high speed without changing a structure of a structured document. Within structural information of a structured document, a paragraph-forming element is obtained in which forming of a paragraph is designated in style definition information corresponding thereto. When the display information of the obtained paragraph-forming element is matched, a program for determining a relative layout of the respective display information within the paragraph is performed independent from a layout routine of another paragraph-forming element. Another program for visually outputting such display information of the paragraph-forming element whose layout routine is accomplished is carried out after the layout routines for all of the paragraph-forming elements located up-rank from the current paragraph-forming element have been accomplished.

Abstract: Several embodiments of an electronic document delivery system are described including a client machine (e.g., a palmtop/handheld computer or wireless communication device) coupled to a transcoder proxy. The system allows a client machine with limited resources to provide an assistive technology solution for a physically challenged user. In one embodiment, the client machine includes an assistive technology which functions as an interface for a device (e.g., a Braille display or a speech engine). The transcoder proxy receives an electronic document expressed in a first digital format (e.g., HTML or XML). The transcoder proxy assigns a unique identifier to the element, and forms a model of a logical structure of the document (e.g., a document object model or DOM). The transcoder proxy uses the model to produce an “original” script including a portion of the document expressed in a second digital format (e.g., a scripting language).

Abstract: An Internet search system is structured for efficient data retrieval from semi-structured data sources. The configurable Internet WEB search system has a browser module for navigating to and displaying a WEB page, a block selection and configuration function having input tools for a user to select at least one block portion of a displayed WEB page for data retrieval, a data-type input function for a user to denote data type to be extracted from a selected block portion, and a search implementation function for implementing a search under the search system. The data type entered by the data input function is associated with a WEB page block selected, and upon search implementation the block selected is searched for the data type requested, and data found is retrieved to be provided to the user. In a preferred embodiment portions of the system are executed on a user station, and other portions on a Portal server to which the user may subscribe.

Abstract: A translation mechanism translates between a word processing document and an XML file. The translation facility may translate the word processing document into the XML file and, conversely, may translate the XML file into the word processing document. The mechanism may be partially integrated into a word processing package so that the translation from word processing document to XML file may be performed via the user interface provided by the word processing package. The translation mechanism is extensible and flexible so as to be able to translate different varieties of document types. The translation is performed automatically by a computer system or other electronic device and eliminates the need for the user to be familiar with the syntax of XML.

Abstract: A document stream operating system and method is disclosed in which: (1) documents are stored in one or more chronologically ordered streams; (2) the location and nature of file storage is transparent to the user; (3) information is organized as needed instead of at the time the document is created; (4) sophisticated logic is provided for summarizing a large group of related documents at the time a user wants a concise overview; and (5) archiving is automatic. The documents can include text, pictures, animations, software programs or any other type of data.

Abstract: Workflow techniques for coordinating organizational processes by providing flexible representations of work using generalized process structure grammars (GPSG). The techniques take into account that, in reality, work evolves both horizontally, in the co-operation of causally unrelated, but information-sharing tasks, and vertically, in the co-ordination of causally-dependent activities. Process modeling involves (1) viewing documents and tasks as duals of each other, capturing horizontal co-operation; and (2) exploiting constraints to express the soft dependencies among related activities and documents within the framework of generative rule-based grammars for processes, thus handling vertical co-ordination. This alleviates or avoids rigidity arising in conventional workflow solutions in part from viewing work processes as unfolding along a single line of temporally chained activities.

Abstract: A digital document delivery system and method for providing to a user an electronic primary document with associated secondary documents. The secondary documents can have relative priorities and are based upon user preference data. An electronic inserter, bill processing server and interactive bill presentation server are used to make the primary and secondary documents available for viewing by a user via the user's web browser, as well as to allow the user to interrogate the system and to respond to the primary document, such as to pay an account due as stated in the primary document. The digital document delivery system and method also notifies the user of the existence of a primary and secondary documents for viewing.

Abstract: A process of designing a high frequency circuit in multiple domains, such as prototype and production domains, is described. The process begins by obtaining one or more parameters for each domain, such as physical parameters defining, for each layer of the substrate, the layer and the material in the layer, or electrical parameters defining, for each layer, transmission media on or within the layer. Once the parameters for the first and second domains have been obtained, the process proceeds to deriving, responsive to one or more of these parameters, interchangeable implementations in the first and second domains of the one or more circuit elements.

Abstract: Methods for formal verification of circuits and other finite-state systems may improve efficiency and capacity of popular binary decision diagram (BDD) based algorithms. A lazy pre-image computation method builds new transition relation partitions on-demand only for relevant next internal variables of a state predicate, and conjoins only next state relations for relevant next internal variables to a pre-image including the state predicate. A lazy backward reachability analysis method makes iterative use of the lazy pre-image computation method to compute the set of states reachable to a given set of states in zero or more transitions. A lazy equivalence checking method makes iterative use of the lazy pre-image computation method to compute conditions that necessarily must be satisfied to disprove equivalence. These methods may provide for symbolic model checking of circuits and other finite state systems previously too large to be completed successfully using BDD based algorithms.