Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A methodology for testing interconnect structures includes testing a number of short line interconnects having the same length and different reservoir sizes. By measuring and comparing the stress values on the interconnects, a relationship between reservoir area and jLcrit may be obtained. This information may then be used to more accurately assess the reliability of an interconnect and to design more reliable interconnects.

Abstract: Disclosed is a designed-circuit-verifying method for verifying an LSI or a wiring-substrate circuit with ease at the design stage of the circuit. An analysis based on simulation of a circuit allows electrical characteristics of a designed circuit to be detected at a design stage and compared with reference data. In accordance with a result of the comparison, an item to be corrected, the location of the item and other information on the item can be identified. In addition, since details of the correction can be displayed at an identified position on the designed circuit, the design of the circuit can be corrected. Thus, the design efficiency of the circuit can be improved.

Abstract: A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.

Abstract: To provide a resistor circuit with which a resistance ratio among voltage division resistors in a semiconductor integrated circuit can be realized with high accuracy. The resistor circuit of the present invention includes: a reference resistor portion; and a resistor portion including resistor elements and fuse connected in parallel with the resistor elements, respectively, for trimming the resistor elements. The resistor elements are arranged in order from the resistor element having a largest resistance value so as to be adjacent to the reference resistor portion in the periphery of the reference resistor portion. As a result, it is possible to obtain accurately the ratio between a resistance value of a reference resistor and a desired resistance value determined with the ratio from the resistance value of the reference resistor.

Abstract: The present invention provides Performance groups based Simulated Annealing (PGSA) for VLSI circuit placement. This method reduces the computation time required for VLSI circuit placement using Simulated Annealing by reducing the size of the placement problem by forming Performance groups while maintaining a high quality of the final placement solution. Performance groups are formed by picking circuits connected by a net and counting their local-net-count. These circuits are then grouped based on certain pre-determined conditions and placed suitably using simulated annealing based placement approach.

Abstract: An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Abstract: A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Abstract: In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device regions and into a plurality of routing regions each crossing a boundary between the plural device regions. A device group including one or more semiconductor devices among the plural semiconductor devices and a local interconnect for connecting the semiconductor devices included in the device group are disposed within the plural device regions. A global routing for connecting the device groups to each other is disposed within each of the plural routing regions.

Abstract: A method and apparatus for generating a configuration bitstream for a programmable logic device using logic ports associated with logic cores. Logic ports are associated with respective ones of a plurality of logic cores, and logical connections are made between selected ones of the ports of the logic cores. Source pins, wherein a pin represents an output resource of a programmable element of the programmable logic device, are associated with selected ones of the ports. A sink pin represents an input resource of a programmable element of the programmable logic device, and sink pins are associated with selected ones of the ports. In response to a route programming interface call that references a source port and a sink port, bits for the configuration bitstream are generated for routing resources to connect selected ones of the source pins to selected ones of the sink pins. Usage of logic ports assists in runtime reconfiguration of logic.

Abstract: Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states.

Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

Abstract: System and method for programmable removal of information from a computing system. One or more information removal options may be selected on a computing device. A purge script file based on the selected one or more information removal options is generated. A purge of information from a computing system is initiated by execution of the purge script file. The purge of information may also be automatically initiated by selection of one or more hotkeys. The purge of information may also be automatically initiated by detecting a preselected number of unsuccessful logon attempts to the at least one computing system and then automatically initiating the purge of information. A plurality purge script files may be generated where each generated purge script file is based on different preselected information removal options. The initiating of the purge of information may be performed by execution of a selected one of the plurality of purge script files. The purge script files define the information to be purged.

Abstract: The present invention relates to a technique for improving the handling of notification items related to the execution of process model instances and/or activity instances within a Workflow Management System (WFMS) or a computer system with comparable functionality. A notification group definition associates a notification group with at least one process model and/or at least one activity. The process model and/or the activity are associated with a notification specification referring to an addressee, for whom the WFMS creates and to whom the WFMS sends a notification item if an instance of the associated process model and/or an instance of the associated activity is not completed according to certain conditions. The WFMS is responsive to the notification group definition by sending a notification group item to the addressee as representative of one or many created notification items of associated process models and/or associated activities.

Abstract: A method and system for integrating plural disparate information sources into a single stream of information using middleware. Data received from real-time sources (e.g., stock quotes) is given priority for distribution over non-real-time sources (e.g., news sources). By coordinating between several servers, data can be distributed in a load-balanced fashion which also performs self-healing in the face of server errors.

Abstract: The system and method for graphic creation of a medical logical module in the Arden syntax file format allows a user to define a medical decision process in terms of flowcharts and outlines. The system and method provide for creation of a medical logical module for a computer in the Arden syntax file format. A graphic representation of a medical decision logic tree of a connected series of a plurality of nodes in a medical decision process is encoded, with each node having a logical path from the node, and each connected series of nodes containing at least one intermediate node and a concluding node. For each node, a conditional statement is encoded for each path from the node; a definition of a path for each intermediate node is encoded; and an outcome for each concluding node is encoded.

Abstract: An optimizing system, method and computer readable recording medium to increase the speed of parallel processing by allowing a mixture of automatic creation of parallel processes and OpenMP API processing and to prevent reduction in performance during parallel processing by controlling the generation of wasted threads when automatic parallel processing and OpenMP API call each other. The optimizing system, method and recording medium create object code that creates parallel processes from a source program coded in a specific programming language, wherein the program is performed using a plurality of threads. The optimizing system generates object code for a source program which is executed in parallel by generating a plurality of threads.

Abstract: A semiconductor test program debugging apparatus is disclosed to which data concerning a packet input to and output from the packet transfer memory device is supplied, and which extracts a part corresponding to the packet from data input to and output from the memory device with response to a test signal generated by a tester simulator and displays the details of the part.

Abstract: A program conversion apparatus including a machine-language storage unit and a conversion unit. The machine-language storage unit stores sets of two or more types of machine-language codes which correspond to components of a predetermined type included in instructions of a source program. The two or more types of machine-language codes in each set have different bit patterns. The conversion unit converts the instructions of the source program into the machine-language instructions. In this conversion, the conversion means converts each predetermined-type component selectively into one of the two or more types of machine-language codes so that the converted machine-language instructions have less digit-bit changes.

Abstract: In a method for converting a system call for an origin operating system into a system call for a destination operating system, an emulation routine is called. The emulation routine converts a reference structure comprising a reference value and at least one referenced element by converting at least the reference value, and it performs the system call for the destination operating system This method makes it possible to run application programs on a destination system without specific adaptation or retranslation, and even when the original operating system has not been ported to the destination system.

Abstract: A computer-based method sets up automatically a computer system configuration in association with a computer system upgrade process. In accordance with the system configuration, the upgrade process installs a required set of operative elements in order to provide for the reliable operation of the computer system. The operatively correct combination of hardware, system and application software components is accomplished by inter-component dependency checking and conflict resolving procedures utilizing specific inter-component dependency rules tables and component definition and inter-component relationship definition databases.

Abstract: A human engineer using a computer system can maintain numerous software services and packages installed on a number of servers through a single master server and a computer network. Each software service and package is represented in a package and service template datastore in a templatized form in which server-specific information is represented by placeholder data. To install a service or package on a destination server computer, data specific to the destination server is substituted for the corresponding placeholder data in program modules, configuration data files, and installation scripts and the program modules, configuration data files, and installation scripts are transported to the destination server where the installation scripts are executed.

Abstract: A system and method for identifying capacity consumption profiles in a client/server computer system, which include such applications as enterprise resource planning customer relationship planning and supply change management. These profiles may be used for improving the ability to forecast those computer requirements necessary to accommodate a user's future data processing requirements. Additionally, these profiles allow for the categorizing of different types of computer usage for a specific client/server solution in a particular industry, which can provide sizing guidance to new users of these client/server solutions. In the present method, selected available statistics and accounting information are consolidated by a context aware process followed by statistical data analysis. After the desired types of profiles are selected with their available client/server identification, the context of the work effort that is being measured is tracked.

Abstract: A method for assigning tasks for processing received from one or several client data processing nodes within a group of at least two server data processing nodes to one of the server data processing nodes, as well as a server data processing system, a client data processing node and a machine-readable storage medium for carrying out this process. A client data processing node that has a task to assign, first selects the server data processing node from the group that is the next server data processing node to be selected based on a predefined cyclical order. If the server data processing node that is selected first denies the processing of the task, the client data processing node randomly selects a different server data processing node for processing the task. Otherwise, the client data processing node assigns the task to the selected server data processing node.

Abstract: A uniform application programming interface (API) provides efficient generation and control of resource reservations so as to ensure a desired quality of service (QoS) for applications running on an operating system of a computer system. The uniform API is based on a hierarchical file system which associates resource reservations with references to shared objects, rather than with the objects themselves. The uniform API permits the use of a variety of different proportional share schedulers for controlling access to physical resources, e.g., CPU, memory, disk, network interfaces, etc. of the computer system. The hierarchical file system includes a separate directory for each independently-scheduled physical resource of the computer system. A parent of the resource reservation in the hierarchical file system is either a root node of the file system or another reservation for the same resource.

Abstract: A process of coordinating access to a shared resource by a plurality of execution units is provided. Channel control units are used to coordinate access to a shared resource. Each channel control unit reads semaphore values of a semaphore storage unit. In response to synchronization commands and semaphore values, the channel control unit manages the flow of execution instructions to the execution units in order to manage access to the shared resource.

Abstract: An on-vehicle information processing unit includes a central processing unit; a first device connected to the central processing unit; a device-dependent driver for driving only the first device; an operating-system-standard (OS-standard) driver enabling an application to drive devices different from the first device; a device-dependent application using the first device through the device-dependent driver; and an OS-dependent application for using the first device through the OS-standard driver. The central processing unit can include a switch for enabling the OS-dependent application only when using an Internet function, and for operating the device-dependent application in a normal mode.

Abstract: In a conditional access system, a system and method for descrambling a scrambled instance having a predetermined encryption cycle rate is claimed. The invention takes advantage of the inherent encryption period associated with a scrambled instance to control subscriber access to scrambled information.

Abstract: A system for delivering contents includes a center system which delivers the contents, a plurality of terminal systems which receive the contents from the center system and displays the contents, and communication lines connecting the center system to the plurality of terminal systems. The center system includes a delivery-schedule setting unit which sets a schedule of delivery, and a contents-delivery unit which delivers the contents to the terminal systems according to the schedule of delivery during a time period when a load on the terminal systems is lower than a predetermined level.

Abstract: A system and method provide a generalized reminder system in an interactive broadcast environment, that enables a viewer to quickly establish reminders for both broadcast events and non-broadcast events, and have such reminders displayed at an appropriate future time. The system includes a broadcast that broadcasts programs, such as television programs and commercial advertisements, and interactive applications associated with various such programs. The interactive applications include reminder interactive applications which have reminder data which describe a future time for displaying a reminder and a description of the event for which the reminder is desired. The broadcast programs and reminder interactive applications are received in broadcast receiver which displays the programs. A viewer viewing a program signals the broadcast receiver to establish a reminder for an event related to the program.

Abstract: A method and apparatus for reducing delay distortion of upstream transmissions in a cable television (CATV) distribution plant. Upstream transmission in a CATV distribution plant, i.e., from the customer premises toward the head-end, is made difficult by delay distortion caused by diplexing filters used in bi-directional amplifiers and other components in the CATV distribution plant. A database storing information relating to each cable modem (CM) in the CATV distribution plant is maintained, and the delay distortion for each upstream transmission is calculated using information queried from the database. Delay distortion in the upper portion of the upstream bandwidth in a CATV distribution plant is preferably minimized by assigning CMs having a transmission path that causes relatively minimal delay distortion to the upper portion of the upstream bandwidth.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.