Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

Abstract: A system and method for managing cachable entities (i.e., entities stored in a cache and/or entities which may be stored in a cache) in a data processing application. In one aspect, a method for managing cachable entities comprises the steps of analyzing program code to determine if there is at least one statement which affects a desirability of performing at least one cache transaction; and performing the at least one cache transaction if it is desired. In another aspect, a program analysis tool statically analyzes program code to locate points where object state changes occur, where objects are created and where objects are deleted, and then generates regularized dependencies at such points for and employing the dependencies to invalidate dependent cached queries. Query specific keys are generated to insert query results into and retrieve query results from a dependency managed cache.

Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.

Abstract: In a system and method for linking and unlinking code fragments stored in a code cache, a memory area is associated with a branch in a first code fragment that branches outside the cache. If the branch can be set to branch to a location in a second code fragment stored in the cache, branch reconstruction information is stored in the memory area associated with the branch, and the branch instruction is updated to branch to the location in the second code fragment, thereby linking the first code fragment to the second code fragment. If it is determined that the previously linked branch should be unlinked, the first and second code fragments at that branch are unlinked by reading the information stored in the associated memory area at the time of linking, and using that information to reset the branch to its state prior to the linking.

Abstract: The resources of a partitioned cache memory are dynamically allocated between two or more processors on a multi-processor unit (MPU). In one embodiment, the MPU includes first and second processors, and the cache memory includes first and second partitions. A cache access circuit selectively transfers data between the cache memory partitions to maximize cache resources. In one mode, both processors are active and may simultaneously execute separate instruction threads. In this mode, the cache access circuit allocates the first cache memory partition as dedicated cache memory for the first processor, and allocates the second cache memory partition as dedicated cache memory for the second processor. In another mode, one processor is active, and the other processor is inactive. In this mode, the cache access circuit allocates both the first and second cache memory partitions as cache memory for the active processor.

Abstract: A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

Abstract: A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the speculative load, and preventing use of the marked speculative load by the microprocessor if a miss occurs. A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, inserting the marked speculative load into a load miss queue, determining whether a miss occurs for the speculative load, and preventing the load miss queue from committing the marked speculative load to cache if a miss occurs.

Abstract: A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

Abstract: Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated with the store instruction is issued prior to a barrier operation associated with the first barrier instruction. A determination is made of when the store request completes before the first barrier instruction has issued. In response, only a single barrier operation is issued for both the first and second barrier instructions. The single barrier operation is issued after the store request has been issued and at the time the second barrier operation is scheduled to be issued.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Abstract: Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory.

Abstract: The present invention includes a microprocessor having a system bus for exchanging data with a computer system, and a private bus for exchanging data with a cache memory system. Since the processor exchanges data with the cache memory system through the private bus, cache memory operations thus do not require use of the system bus, allowing other portions of the computer system to continue to function through the system bus. Additionally, the cache memory and the processor are able to exchange data in a burst mode while the processor determines from the tag data when a read or write miss is occurring.

Abstract: An information processing system is provided that is capable of memory access suitable in any programming environment and which increases reliability by varying or restricting program access to memory areas. A number of data storage areas are established in memory that are equal to a number of declared object oriented array elements. Thereafter, memory is addressed using an index value of the indicated array element in the area where the data is stored. If, for example, an array object of a size corresponding to the total size of addresses in the memory is declared, the entire memory will be considered to be the data storage area. A program can then access a memory address by looking up a desired element.

Abstract: A data processing system includes an embedded controller (100) having a core (102), a system bus, nonvolatile memory (104), and random access memory (RAM) (106). The RAM (104) has a non-overlay region (108) and an overlay region (110). The overlay region (110) may be divided into a plurality of partitions. Partitions of the overlay region (110) may be used as general purpose memory when they are not being used as overlay regions.

Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.

Abstract: A data storage device and method for improving the performance of data storage devices examines a command queue and performs data transfers to memory within the device before prior commands have completed. A process running in the idle loop of the controller in the storage device checks the queue for write requests and if a cache space within a dual-port cache to hold the transfer data is available, the data transfer portion of the transfer is completed, while the device is still waiting for completion of prior commands in the queue, and data transfers are completing from the cache to the physical media for the prior command.

Abstract: A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Abstract: A storage management system, apparatus, and method to increase the storage capacity of data storage media. Applicants' method uses a data storage device comprising a fixed device architecture, where that data storage device is capable of operating in a first capacity mode or in a second capacity mode, and where that data storage device is capable of switching between the first capacity mode and the second capacity mode. In certain embodiments, the first capacity mode utilizes a 22 bit blockid format and the second capacity mode utilizes a 32 bit blockid format. In other embodiments, the first capacity mode utilizes a 32 bit blockid format and the second capacity mode utilizes a 22 bit blockid format. A computer code product comprising a data management system which includes an operating system and data storage device microcode, which supports the capability to switch between alternative information storage architectures, and thereby, increase the capacity utilization of data storage media.

Abstract: A data communication device which includes a flash memory, a primary buffer region in the flash memory which has time-sequential information stored therein from earliest to, an auxiliary buffer region in the flash memory which receives and stores primary-buffer storage information to be stored in the primary buffer region during a first condition of the data communication device when the information stored in the primary buffer region is not allowed to be updated, and an information-storage control unit which, when the primary-buffer storage information is stored in the auxiliary buffer region and during a second condition of the data communication device when updating of the information in the primary buffer region is allowed, reads information having a size not more than the storage capacity of the primary buffer region from the information stored in said primary buffer region and the auxiliary buffer region, and which re-stores the information that has been read in the primary buffer region.

Abstract: A method to partition a data storage and retrieval system into one or more logical libraries, where that data storage and retrieval system includes a library controller, one or more data storage drives and one or more control ports. A data storage and retrieval system which includes a computer useable medium having computer readable program code disposed therein to implement Applicants' method to partition the data storage and retrieval system into one or more logical libraries. A computer program product usable with a programmable computer processor having computer readable program code embodied therein for partitioning Applicants' data storage and retrieval system into one or more logical libraries.

Abstract: An input/output register programming system that uses a set transmission value. The input/output register programming system includes an address decoder, a transmission setting register, a partitioning device, an internal address generator and a transmission space. The address decoder decodes the write address to determine the type of input command. If the input command is a transmission setting register write command, the input data is written down to be used as a set transmission value. The set transmission value determines the target region address of the input command. If the input command is an input/output register write command, the target region address is output. The partitioning device divides the input data into a secondary address and stored data. The internal address generator combines the secondary address with the target region address to produce an internal address. The stored data are transmitted to the registers specified by the internal address.

Abstract: A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.

Abstract: A microprocessor having an internal memory for storing data to be process, a data pointer register for storing an address on the internal memory, a decoder 36 for decoding an instruction, a general-purpose register module 11 including data registers r0 and r1 for storing data read from an address on the internal memory stored in the data pointer register in accordance with a request to read data stored in the internal memory, and an ALU 13 for performing processing using data stored in the general-purpose register module 11 based on the result of decoding by the decoder 36 and writing the result of processing in the general-purpose register module 11.

Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.

Abstract: A system comprises: a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive a plurality of instructions for the first to third execution units and to output the instructions to the execution units; a memory store for storing at least one instruction for one of the execution units, the at least one instruction being received from the first-in-first-out memory, the first and second execution units being arranged to receive their instructions from the first-in-first-out memory and the third execution unit being arranged to receive the instructions from the memory store, wherein a given instruction for the third execution unit is available to the third execution unit at substantially the same time that the instruction would be available to the first or second execution unit if that instruction was for the first or second execution unit.

Abstract: A processor includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, a load queue and associated queue management logic. The load queue contains a plurality of entries that each include a reservation valid field, and each of the plurality of entries is associated with a respective one of a corresponding plurality of load instructions that includes at least one load-reserve instruction. In response to execution of the load-reserve instruction, the queue management logic detects whether a data hazard exists by reference to the load queue, and if so, initiates correction of the data hazard. In addition, the queue management logic records a reservation for the load-reserve instruction by setting the reservation valid field of an entry in the load queue associated with the load-reserve instruction.

Abstract: An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet to generate a result. The apparatus utilizes the speculative result to configure a speculative address operand that is provided to an address-dependent micro instruction. The apparatus includes speculative operand calculation logic and an update forwarding cache. The speculative operand calculation logic performs the arithmetic operation to generate the speculative result prior to when execute logic executes the preceding micro instruction to generate the result.

Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.

Abstract: A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.

Abstract: The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

Abstract: This invention provides for filtering instructions to obtain more precise event counts with a plurality of instructions having a counter enable bit, executing the instructions thereby causing a plurality of events, filtering the instructions, activating the counter enable bit if the instructions fall within the filter, which then determines whether an event counter coupled to the event is incremented.

Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.

Abstract: A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator.

Abstract: A system and method for converting 32 bit addresses into 64 bit addresses and enabling the 32 bit address to include a region index. The region index is stored in low order bits of the 32 bit address. In some architectures, namely the Intel IA-64 architecture, the low order bits are not used in entry point addresses because each entry point is on a 16 byte boundary. In the case of the IA-64 architecture, the low 4 bits of a 64 bit module entry point address are ignored. The region index in a 64 bit IA-64 address is stored in the high 3 bits of the address. Region index information is stored in the low order bits of the 32 bit address and copied to the high order bits for the corresponding 64 bit address. In this manner, the 32 bit address can include memory region index information without compromising the normal 4 gigabyte address space for a 32 bit address.

Abstract: A configuration system is disclosed that applies rules of precedence to evaluate parameters in the context of multiple sections within a configuration file and in the context of multiple configuration files. The system brings together multiple sections and multiple files into a unified whole. The precedential order of sections and files is set by a user and special section names can be used to override default precedential rules. If a parameter is set multiple times at different levels in the hierarchy of belonging, its final value reflects the value set at the level most closely concerned with the setting of the parameter. The value of a parameter can be set from an environmental variable or from the value of another parameter. If a parameter's value depends upon the value of another parameter, that second parameter is recursively evaluated using the same precedential rules.

Abstract: A method and apparatus for executing a power on self test includes executing a primary subset of POST tests during initial startup of a computer, and executing a secondary subset of non-essential POST tests transparent to a user at a later time. The secondary subset of POST tests may be performed after a period of computer inactivity.

Abstract: A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.

Abstract: A service replicating server replicates service per each network and shares data safely between networks such as an interoffice network and the internet. The LAN side server connected to the LAN and an internet side server connected to the internet share data at the shared disk which performs mutual exclusion using a bus having bus lock function and supplies a consistent service to each network by using the shared data.

Abstract: A secure packet processor includes a buffer, a cryptographic engine and an authentication engine. The buffer is adapted to receive a secure packet that includes encrypted data and indicates an authentication signature. The cryptographic engine is adapted to decrypt the encrypted data to produce an indication of second data. The authentication engine is adapted to use the encrypted data to validate the signature concurrently with the decryption of at least a portion of the decrypted data. The authentication engine and the cryptographic engines may also be adapted to concurrently validate and encrypt data of an unsecure packet.

Abstract: The invention is a system for digital watermarking that operates on a conventional digital video stream to etch, on hand, and read, on the other hand, digital watermarks in the stream that do not visibly interfere with the video content. A system according to the invention operates on digital data that has been transformed into the spatial-frequency domain, using inter-block differences between spatial-frequency coefficients to encode the bits of a digital watermark. Using the principles of the invention, it is possible to encode multiple watermark bits between two adjacent blocks, thus providing higher watermark data rates relative to underlying video content.

Abstract: A method for generating a signed manifest includes referencing an object. A metadata name is recorded. A digest algorithm is recorded. An integrity value that belongs to the object that corresponds to the metadata subject name is digested with the digest algorithm.

Abstract: A method for the execution of an encryption program for the encryption of data in a microprocessor-based portable data carrier is described, with the encryption program comprising several parallelisationable subprograms. According to the invention the serial order of execution of at least two subprograms is randomly permuted in the execution of the encryption program under the consideration of at least one random number.

Abstract: There is provided a microcomputer including: an external apparatus discrimination means for discriminating that an external apparatus is connected to said microcomputer via an IC card interface section, based on a discrimination signal to be transmitted by said external apparatus, when the external apparatus is placed in a communicatable status which allows communication by feeding a power supply, a clock signal and initializing an operation; and memory contents change means for receiving data including a CPU program, from the external apparatus and executing changing of the contents of a memory, thereby allowing modification of a CPU program stored in the microcomputer during manufacture.

Abstract: A distributed computer system and server architecture transmitting an electronic ticket over the system, such as the Internet, enabling a user to be authenticated and authorized for a requested operation. An “eticket” architecture (including identification information) is generated by, for example, an authentication server. The information in the eticket is hashed using, for example, a Message Digest Protocol, and a hash number is generated. The hash number is then encrypted by the authentication server using a private key, and the identification information in the eticket and the encrypted hash number are concatenated by the authentication server to generate a completed “eticket” architecture. The “eticket” may then be transmitted over the Internet (i.e., a non-secure environment) from server to server without having the information in the “eticket” altered, and without having to “reauthenticate” the user at each server.

Abstract: A method and system for updating anti-intrusion software is provided. In a preferred embodiment, a computer program product updates anti-intrusion software on a computer network which has an anti-intrusion monitor server. The anti-intrusion monitor server recognizes attacks on the computer network in accordance with attack pattern information contained in the anti-intrusion software. The computer program product includes computer code that installs modified attack pattern information onto a central anti-intrusion server, and computer code that transfers the modified attack pattern information from the central anti-intrusion server to the anti-intrusion monitor server using push technology. The result is that newly discovered attack patterns are capable of being rapidly communicated from the central anti-intrusion server to the computer network.

Abstract: An active monitor detects and classifies messages transmitted on a network. In one form, the monitor includes a routine for classifying TCP packet source addresses as being of an acceptable, unacceptable, or suspect type. Suspect source addresses may be further processed in accordance with a state machine having a number of conditionally linked states including a good address state, a new address state, and a bad address state.

Abstract: A stolen computer detection and protection method and system. The method and system detect a communication to at least a first data processing system from at least a second data processing system. In response to detection of the communication from the at least a second data processing system, determination is made as to whether the at least a second data processing system is stolen. If it is determined that the at least a second data processing system is stolen, the at least a second data processing system is disabled.

Abstract: A system and method are disclosed that regulate browsing of web content or content labels and that provide selective and multiple programmed settings and passwords for web content labels. In one embodiment, at least some of the web pages accessible to a web browser are assigned content labels. Programmed settings are established for the content labels that are to be password protected. A content password is assigned to each of the programmed settings. Access to web pages without any content labels is strictly denied by the web browser. Access to web pages with content labels that are not being regulated is allowed. Access to web pages with content labels that are password protected is regulated.

Abstract: Secure web-based messaging according to a “push” paradigm is augmented by specific, intended recipient authentication. In particular, a document can be sent to a specified, intended recipient through the Web using e-mail recipient notification, and the recipient is authenticated prior to delivering the document to the recipient. Such authentication prevents a cracker from snooping a delivery notification e-mail message and retrieving the document prior to retrieval by the true intended recipient. In addition, such authentication of the recipient is driven by the sender such that prior participation by the recipient in the messaging system according to the present invention is required.