Abstract: A wearable computer system includes a processing unit (102) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus (120). The processing unit has a single connector for implementing the serial bus, and peripherals each have two connectors for propagating the serial bus. The wearable computer system has only one unused connector at any one time, thereby reducing excess bulk and weight due to excessive unused connectors. When a peripheral interrupts the processing unit, the processing unit relinquishes the serial bus to the interrupting peripheral. Alternatively, peripherals are assigned time slots within which the peripherals can utilize the serial bus.

Abstract: The programmable controller composed of a main body unit and a plurality of input/output extension blocks is provided with type identifying means for identifying the number of input output points and present organization storing means. Upon receiving an organization update instruction signal, it can allocate input and output numbers in various ways by rewrite setting means in a system memory and can select a second allocation method with which existing input and output numbers are not changed or a first allocation method with which input and output numbers are completely changed anew. When input and output numbers are completely changed anew, it can automatically change input and output numbers accompanying an instruction in a program memory by instruction changing means in the system memory.

Abstract: The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual copy of the I/O facilities to be shared. The remote translation control entry table on the hosted partition is loaded with data from a hypervisor in response to requests made by the OS running in the hosted partition. The hypervisor, in response to requests from the OS running in the hosting partition, copies the data from the remote translation control entry into a standard translation control entry table on the hosting partition owning the physical I/O facilities that target the I/O page buffers of the hosted partition to perform the desired I/O operation. The I/O page buffers of the hosted partition are accessed by the hosting partition's I/O facilities using the data stored in the standard translation control entry table.

Abstract: A communication system having a controlled device (105), for which an abstract representation (AR) (107) is provided as interface on a controlling device (103). When the quality of the connection between the controlling device (103) and the controlled device (105) drops below a predetermined level, or if some similar criterion is met, the system selects a second controlling device (104) which is better suited for controlling the controlled device (105) and generates a migration event to indicate this. The first controlling device (103) transfers control over the controlled device (106) to the second controlling device when it receives said migration event. This can be done by uploading the AR (107) to the second controlling device (105), possibly supplemented with the current state of the AR (107) to perform a fully transparent transfer.

Abstract: The invention relates to an information-processing apparatus, an information-processing method, a memory card and a program storage medium. A memory card has VSS pins connected to the ground, a BS (Bus State) pin for receiving a bus-state signal, VCC pins for receiving a voltage of a power supply, an interrupt pin for outputting interrupt data, a clock pin for receiving a clock signal and reserved pins conforming to a USB standards. When the memory card is inserted into a personal computer, the reserved pins are connected to a USB-host-controller IC employed in the personal computer so that serial data conforming to the USB standards can be exchanged between the memory card and the personal computer. With this configuration, a desired function can be added to the memory card.

Abstract: The present invention captures streaming data and avoids continual retrieval. The invention only looks at data once, has a time dependency built into it, and data that is not consumed or relevant is discarded. The invention includes an engine processor that processes data according to stored information; stored rules that define engine operation, an input events module for receiving events which provides a plurality of events. Events are processed according to stored rules for generating a series of valid results when input events match the rules. Rule states that have been matched to an input event but have not produced a valid result are stored in state storage. The state of a rule as stored enables the engine to provide a valid result output upon a future reception of an input event necessary to complete the rule. Transaction log module monitors the operation of the engine for specified time period.

Abstract: A controller contains an I/O memory and uses a device detecting service to detect a device connected to it through a network and to obtain its device identifying data. A memory map setting service sets a device data area on the I/O memory according to the obtained device identifying data for exchanging data with the connected device and produces a memory map correlating the device data area with a variable data area on the I/O memory correlated to the device. The controller also includes a cyclic service and a data transmission service. The cyclic service transmits and receives data to and from the device periodically in the data linking format according to the memory map and by using the device data area on the I/O memory. The data transmission service transmits the data between the variable data area and the device data area.

Abstract: A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region. Requests for memory are mapped at least once, for example from virtual to physical page numbers. The I/O requests are conditionally remapped to pages in the first region as a function of how often they are involved in the I/O operations and would normally otherwise need to be copied. Remapping may also be made conditional on a function of availability of memory in the first region. In a preferred embodiment of the invention, the I/O requests are initiated by a subsystem within a virtual machine, which runs via an intermediate software layer such as a virtual machine monitor on an underlying hardware and software platform. A typical application of the invention is DMA.

Abstract: The invention provides systems, methods, and devices that automatically create and maintain a wireless connection to a remote computer network. In one embodiment, the method creates and maintains a persistent modem connection by searching for an unconnected modem, detecting an unconnected modem; and initiating a dial-up to a computer network.

Abstract: The present invention relates to a detection method used in a memory card adaptor and, more particularly, to a detection method used in an adaptor capable of inserting various kinds of memory cards. The present invention comprises mainly the steps of: a control device on an adaptor issuing an identification command to detect a memory card responsive to the identification command, and the control device issuing again a reset command to detect a reset-type memory card if there is no corresponding response; the control device continually awaiting a response signal if there is still no corresponding response; the control device entering a read/write mode corresponding to the memory card if a corresponding response is obtained after issuing the command; and the control device awaiting a read/write command of said master device. The present invention can effectively enhance detection and identification efficiency without the need of adding a hardware switching device.

Abstract: A method of transferring a block of data from a first to a second circular buffer of a computer system. The method comprises notifying the DMA controller of the source and destination addresses for the transfer, the sizes of the circular buffers, and the size of the data block to be transferred. At the DMA controller, respective base and rollover addresses of the circular buffers are identified. Data is read from the first circular buffer starting at the source address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached. Data is written to the second circular buffer starting at the destination address, continuing until the rollover address is reached, and continuing from said buffer base address until the end of the block is reached.

Abstract: A storage subsystem and a storage controller adapted to take advantage of high data transfer rates of fibre channels while offering enhanced reliability and availability and capable of connecting with a plurality of host computers having multiple different interfaces. A loop is provided to serve as a common loop channel having fibre channel interfaces. Host interface controllers (HIFC) connected to host computers having different interfaces permit conversion between the fibre channel interface and a different interface as needed. Control processors, shared by the host interface controllers, each reference FCAL (fibre channel arbitrated loop) management information to capture a frame having an address of the processor in question from among the frames passing through the loop. I/O processing is then carried out by the controller in accordance with a range of logical unit numbers (LUN) set in the captured frame.

Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.

Abstract: In a multi-path computer system, a host apparatus and devices are connected via a plurality of paths, recorded therein. From channel adapters of the devices, device information of said devices, area information corresponding to a plurality of accessible areas, channel-adapter number information in said devices, and/or component exchange-unit information in said device are obtained. Properness of the plurality of paths is determined from access path information and identification information comprising the device information and area information. Identification information is determined, concerning an error path, comprising the device information and channel-adapter number information, to the other multi-path control parts of its own apparatus or the multi-path control parts of the other apparatuses, when detecting the error path.

Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon completing a filter process and determining that the ring-buffer data stored in said ring-buffer memory space is no longer necessary after the filter-process is carried out.

Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.

Abstract: A correlation element 134 correlates a source device with a destination device according to an instruction given by the user. A decision element 122 determines whether or not a certain combination of device classes is operable as a composite device. In the case of the affirmative answer, a determination element 136 identifies the type of the composite device and specifies a user interface for operating the composite device. A data output element 132 then displays the specified user interface in a window on a monitor 170 at a specific timing. This arrangement effectively improves the operatability of the device control.

Abstract: A modified system causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64# signal low. This will synchronize reset and REQ64#, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.

Abstract: The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.

Abstract: A method and apparatus for establishing a personalized connection with a network from a variety of different terminals and/or ports connected with the network. Subscribers to the network can be provided with a unique subscriber ID that may be used by the network to identify the subscriber. Furthermore, based on the subscriber ID, the network or a network customizing device can access a subscriber profile in order to personalize a connection with the subscriber. Additionally, the subscriber profile can be used by the network service provider for billing purposes.

Abstract: An apparatus for connecting circuit modules is disclosed. The apparatus for connecting circuit modules that receives an input and an output signal at one circuit module and uses a transmitter/receiver to transmit data to and receive data from the second circuit module. Each transmitter/receiver is selectable between a bidirectional mode that transmits and simultaneously receives via two transmission lines, and a unidirectional mode that transmits on a first transmission line and receives from a second transmission line.

Abstract: The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.

Abstract: A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller.

Abstract: A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

Abstract: A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive and provide temporary storage for corresponding external interrupt signals, an interrupt priority determining circuit that can receive the external interrupt signals from the multistage interrupt reception registers, determine priorities of the external interrupt signals, and dispose of the external interrupt signals according to the priorities, and a logical operator that inverts signals generated by the corresponding multistage interrupt reception registers and provides a logical feedback signal to the multistage interrupt reception registers.

Abstract: Customer requirements for portable computers are grouped into logical functional groupings, which are further grouped into logical bandwidth levels. On the notebook side, all required signals for a specific logical functional grouping are combined into a single carrier with the necessary bandwidth for the signals within the logical bandwidth level. This combined signal is then passed through a docking connector. The individual signals are regenerated on the docking solution side of the connector. Logic on both the notebook and docking solution sides of the connector enables the respective devices to identify which carrier bandwidths are supported on both sides of the docking connector and settle on the greatest common denominator. Additionally, the signals combined into the carrier can be programmed, in which case the docking solution and the notebook negotiate the features that are and are not supported in each individual case.

Abstract: A method and apparatus provides a method and apparatus for treating a serial bus, such as an IEEE 1394 bus, as a connection-oriented network. In one embodiment, an application programming interface (API) permits different protocols (e.g., TCP/IP, IPX, and others) to connect to the 1394 bus and to make use of various 1394 features, such as isochronous packet transmission, without knowledge of hardware-specific idiosyncrasies. A call is made to set up a connection (a “virtual circuit”) over the serial bus, and, thereafter, a connection “handle” is used to communicate over the bus using the connection. Different types of connections can be provided, including a node-specific connection; a channel-specific connection; and a receiving connection (e.g., for incoming data). In one embodiment, a programming interface hides details of the connection set-up, and includes packet fragmentation and reassembly functions.

Abstract: An industrial PC-compatible computer system for telecommunications applications is described. The computer system includes a plurality of peripheral boards, each of which includes a peripheral processor. A computer telephony bus provides communications among the peripheral boards. The computer system also includes a plurality of system processors. A serial telecommunications bus arrangement provides communications between the plurality of peripheral boards and the plurality of system processors. The computer system arrangement providing for greater reliability in the event of a failure of a peripheral board, a system processor or of the communications therebetween.

Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

Abstract: A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.

Abstract: The present invention relates to a system and method to efficiently move data from one data bus to another data bus in a network switch. The method includes generating a packet cycle on a first data bus. The method also includes generating a control data cycle on a second data bus. The method further includes processing the packet cycle on the first data bus after processing the control data cycle on the second data bus.

Abstract: A method and apparatus is provided for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit includes a plurality of I/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the I/O circuits. A signal transmitted on the address selection data path selects one of a plurality of arrays from which to access data for each I/O circuit. When in a larger bus width configuration, each of the I/O circuits is connected to a data bus line. When in a smaller bus width configuration, a subset of the I/O circuits is connected to the data bus line and data from the plurality of memory arrays is output through the subset of I/O circuits, which selectively switch outputs between memory array inputs.

Abstract: The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or may not continue to run. The invention also allows changes to the association between cells, I/O and partitions. The partitions may be able to stay running, or may have to be shut down from the resulting changes. In the invention, multiple copies of the OS are running independently of each other, each in a partition that has its own cell boards with processors and memory and connected I/O. This provides isolation between different applications. Consequently, a fatal error in one partition would not affect the other partitions.

Abstract: A keyboard selectively operable to convey data to and from a host or personal computer (PC) through a universal serial bus (USB) port and/or a personal system/2 (PS/2) port. The keyboard is preferably connected to both the USB port and PS/2 port on the host or PC, if available. Preference is given to communicating data from the keyboard to the host or PC through the PS/2 port. However, if the PS/2 port is unavailable, not connected, or inoperative, the keyboard data are communicated to the host or PC through the USB port (assuming that it is available, operative, and connected). As soon as the PS/2 port on the host or PC is again connected to the keyboard, such data will again be communicated through the PS/2 port. In addition, the keyboard includes auxiliary USB ports to which USB-capable peripheral devices can be connected. USB data can then be communicated between the PC and the USB-capable peripheral devices via the keyboard and its connection to the USB port on the host or PC.

Abstract: An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to directly communicate with a RAMBUS RDRAM memory system, are translated for a memory system which does not comprise RAMBUS RDRAM. The interface device, or integrated circuit, is not located with the memory system. That is, the memory modules do not include the interface circuit. Instead, the interface device is located with the processor motherboard, or with the controller/bridge integrated circuit chip set, such that it is electrically located between a controller and main memory sockets.

Abstract: A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

Abstract: A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.

Abstract: Blocks and clusters are brought to correspondence thereby to erase blocks of memory area efficiently. A flash memory has its physical addresses partitioned from address 0h sequentially into blocks each having eight sectors. The data area of logical address starts at address 4Dh, which is set to the starting physical address 50h of the block which is close to the top of data area, and the data area is set sequentially to the following physical addresses. The remaining logical addresses 3D7Dh-3D7Fh are brought back to the top of physical address and set to physical addresses 0h-2h. Consequently, clusters (a cluster has 4 k bytes or 2 k bytes) of data sent from a host unit correspond to blocks of physical addresses, enabling block erasure of the flash memory, whereby the number of times of erasing operation at data writing can be reduced significantly.

Abstract: An electronic apparatus and method for updating data in a flash read only memory (ROM) in an electronic apparatus. The electronic apparatus, which may be an image forming apparatus having copying and printing functions, has a first board connected to an external device, and a second board connected to the first board. If flash ROM-updating data received from the external device is not data used for updating the flash ROM on the first board, this updating data is forwarded to the second board. On the basis of the updating data forwarded from the first board, the flash ROM of the second board is updated. The updated data may be forwarded to a third board if the data is not data for updating the flash ROM on the second board.

Abstract: The disclosed embodiments provide an efficient method and apparatus for reprogramming flash memory in a multiprocessor computer system. A bootstrap processor (BSP) partitions portions of an image to be programmed into the flash memory and may divide those portions amongst itself and one or-more application processors (APs) for reprogramming.

Abstract: A semiconductor memory device having a double data rate (DDR) mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for a reading operation with the lower bits of a specified memory address for a preceding writing operation, a second comparison logic circuit detecting if bits other than the lower bits match, and a third comparison logic circuit detecting that, when a match is obtained from the second comparison logic circuit, the lower bits of the specified memory address or a secondary memory address such as a burst address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation. The device may have a late write function and a register may be provided to latch single data rate (SDR)/DDR mode information.

Abstract: Techniques for efficient memory management that enable rapid longest prefix match lookups in memory. In general, the present invention is efficacious wherever maintenance of a good distribution of holes in a sorted list is required. This technique relies on a proactive hole management methodology to preserve a good distribution of holes in each memory region in such a way that one does not have to search for holes in order to insert or store a new entry into the list. In particular, all holes in a given region are kept in one or more contiguous sub-region. Keeping the holes contiguous requires a hole move every time there is a delete operation. The amortized cost of these operations is justified by the resulting simplification in later insert (store) and delete operations. For example, during an insert the new entry is placed at the end of the contiguous sub-region of used entries in the region.

Abstract: A method and apparatus are provided for hard disk drive command queue ordering. For each command in the hard disk drive command queue, an expected access time is calculated including a probability of success calculation. A command in the hard disk drive command queue having a minimum calculated expected access time is identified. Then the identified command having a minimum calculated expected access time is executed. For an estimated seek time of less than a time for one full revolution, a probability of a miss multiplied by a time of one extra revolution is calculated and the result is added to an estimated seek time to provide the expected access time. For an estimated seek time of greater than a time for one full revolution, a probability of a make multiplied by a time of one extra revolution is calculated and the result is subtracted from an estimated seek time to provide the expected access time.

Abstract: A volume provider unit in a computer system detects a logical block address of a read or write I/O accessing a logical volume of a storage device from a host. According to the logical block address fetched, a storage domain of the logical volume is dynamically expanded. Moreover, the storage domain of the logical volume is reduced or expanded according to an instruction of a logical volume capacity reduction or expansion from a host commander part to a volume server.

Abstract: The present invention relates to a disk drive 10 comprising a cache memory 14 and a cache control system having a tag memory having a plurality of tag records, and means for allocating a tag record for responding to a host command. The cache memory has a plurality of sequentially-ordered memory clusters 46 for caching disk data stored in sectors (not shown) on disks of a disk assembly 38. Conventionally the disk sectors are identified by logical block addresses (LBAs). The cache control system 12 along with the tag memory 22 and means for allocating tag records are embedded within the cache control system 12 and thereby configured only for use in defining variable length segments of the memory clusters 46. The segments are defined without regard to the sequential order of the memory clusters 46.

Abstract: According to one embodiment of the present invention a disc controller in a disc drive includes a cache memory and a control circuit. The control circuit is configured to identify an operating system of a host computer coupled to the disc drive, select a segmentation level for the cache memory based on the identified operating system, and store information in the cache memory according to the segmentation level. According to another embodiment of the present invention a cache memory in a disc drive is operated by identifying an operating system of a host computer coupled to the disc drive, selecting a segmentation level for the cache memory based on the identified operating system, and storing information in the cache memory according to the segmentation level. The operating system is identified by reading a partition type from a master boot record stored in a disc in the disc drive.

Abstract: A method and apparatus for managing a dynamic assignment of resources in a storage system. In one aspect, a storage system includes a plurality of storage devices, a plurality of controllers that each is coupled to at least one of the plurality of storage devices and controls access to the one of the plurality of storage devices, a memory that is globally accessible to each of the plurality of controllers; first means for creating in the memory a global table that stores information that specifies dynamic assignments of resources in the storage system, and second means for creating a local table in at least one of the plurality of controllers that includes all of the information stored in the global table. In another aspect, the storage system stores information written by a data processing system that accesses units of information in the storage system using a logical volume address, and the local and global tables are indexed by the logical volume address.