Abstract: It is intended to provide a field-effective-type semiconductor device that can let low ON-resistance and non-excessive short-circuit current go together by effectively using its channel width and prevents device from destruction. In a field-effective-type semiconductor device, a semiconductor region arranged between gate electrodes 106 has stripe-patterned structure consisting of an N+ emitter region 104 and a P emitter region. The P emitter region is constituted by P channel region 103 of low concentration and P+ emitter region 100 of high concentration. The N+ emitter region 104, the P channel region 103, and the P+ emitter region 100 are in contact with the emitter electrode 109. Thereby, a channel width X is limited to the extent that is enough for ON current under normal operation state. That is, low ON-resistance and not excessive short-circuit current can go together in the field-effective-type semiconductor device.

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, and removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract: A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.

Abstract: In a thin film transistor provided with a metallic layer with a light-shading property and a Si layer formed on an insulating layer, a dent for locally thinning the insulating layer is formed on a portion corresponding to a drain region. When the Si layer is recrystallized by means of a laser light irradiation, the dent serves as a crystalline nucleus formation region in order to recrystallize a particular portion earlier than other portions. Recrystallization of melted Si starts from a periphery of a bottom surface of the dent, hence a Si layer formed of a single crystal or uniformed crystal grains which serves as an active region of the TFT can be obtained.

Abstract: High Voltage Difference Amplifier With Spark Gap ESD Protection a spark gap device for protecting an integrated circuit. The spark gap device includes a first node for receiving an input signal and a second node to be protected. A first conductive layer is conductively interfaced to the first node and the second node and disposed therebetween. A second conductive layer is connected to a sink voltage and separated from the first conductive layer by an insulating layer of a predetermined thickness.

Abstract: A LSI has a plurality of separate power source systems, and an ESD protection circuit connected between ground lines of two of the power source systems. The protection circuit includes a pair of thyristors connected parallel to one another in opposite directions between the ground lines.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.

Abstract: A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the buried bit lines and between the gates, a plurality of word lines each disposed over a row of gates perpendicular to the buried bit lines, and a coding layer between the word lines and the gates.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: A gate electrode is formed on a substrate via a gate insulating film. The gate insulating film includes a high dielectric constant film containing a metal, oxygen and hydrogen, and a lower barrier film formed below the high dielectric constant film and containing a metal, oxygen, silicon and nitrogen.

Abstract: Disclosed herein is SPM cantilever having a support portion, a lever portion extended from the support portion and a probe portion formed at a free end of the lever portion, said probe portion having a generally plate-like form and the probe portion having an additionally sharpened terminal end portion. The terminal end portion has its length greater than the plate thickness thereof and is reduced in thickness toward a tip of the terminal end portion, and the tip is located inwardly of the planes extended from the front and back sides of a base portion of the plate-like probe portion.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package.

Abstract: An efficient spin injection into semiconductors. Previous spin injection devices suffered from very low efficiency (less than 2% at room temperature) into semiconductors. A spin injection device with a &dgr;-doped layer placed between a ferromagnetic layer and a semiconductor allows for very high efficient (close to 100%) spin injection to be achieved at room temperature.

Abstract: An electronic module includes an EL section; a first substrate on which the EL section is formed; a second substrate attached to the first substrate; an integrated circuit chip mounted on the second substrate; a plurality of first power supply interconnects formed on the first substrate, extending through a pair of regions located on both sides of the EL section; and a plurality of second power supply interconnects formed on the second substrate, extending through a pair of regions located on both sides of the integrated circuit chip.

Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

Abstract: An integrated circuit having functional circuitry within a core portion of the integrated circuit. Input circuits are disposed on a first layer within a peripheral portion of the integrated circuit, where the input circuits are electrically connected to the functional circuitry. Power and ground buss lines are disposed on a second layer within the peripheral portion of the integrated circuit, where the second layer overlies the first layer. The power and ground buss lines overlie the input circuits, and are electrically connected to the input circuits. Bonding pads are disposed on a third layer within the peripheral portion of the integrated circuit, where the third layer overlies the second layer. The bonding pads overlie the power and ground buss lines and the input circuits, and are electrically connected to the input circuits.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: A semiconductor component includes a RESURF transistor (100, 200, 300, 400, 500) that includes a first semiconductor region (110, 210, 310, 410, 510) having a first conductivity type and an electrically-floating semiconductor region (115, 215, 315, 415, 515, 545) having a second conductivity type located above the first semiconductor region. The RESURF transistor further includes a second semiconductor region (120, 220, 320, 420, 520) having the first conductivity type located above the electrically-floating semiconductor region, a third semiconductor region (130, 230) having the first conductivity type located above the second semiconductor region, and a fourth semiconductor region (140, 240, 340, 440, 540) having the second conductivity type located above the second semiconductor region.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region.

Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.

Abstract: A high Q inductive element with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk silicon. The support elements, which may have different configurations, such as walls or columns, provide mechanical stability to the inductive loops and reduce the parasitic capacitance and the losses to the substrate.

Abstract: A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: An integrated circuit (10) includes a thermal sensing device (20) and a power-switching device (12) such as an IGBT. The power device (12) is fabricated in a conventional manner on a semiconductor substrate, and the thermal sensing device (20) is fabricated on an electrical insulation layer (74) formed over the substrate. The thermal sensing device (20) may be provided in the form of a number of series-connected polysilicon diodes (D1-D3) positioned adjacent to the power device (12) such that the operating temperature of the thermal sensing device (20) is near that of the power device (12). In response to an input current IC, the thermal sensing device (20) produces an output voltage (VD) that is substantially linear with surface die temperature, and which reacts rapidly to changes in surface die temperature. The thermal sensing device (20) is completely electrically isolated from the power device, thereby eliminating any electrical interaction therebetween.

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract: A semiconductor wafer and a method for fabricating a semiconductor wafer having improved dicing lanes are provided. The dicing lanes include grooves formed by photolithography and etching processes. The wafer also includes a plating layer on a back side of the wafer to facilitate bonding of individual circuit chips to a suitable substrate and to effect efficient heat transfer between the chip and the substrate. Photolithography and etching processes are employed to etch horizontal and vertical lanes in the plating layer to facilitate breaking of the individual chips from the wafer. The horizontal and vertical lanes etched in the plating layer are coincident to the grooves etched in the substrate. The wafer can then be broken into individual circuit chips by applying stress to the back of the wafer, such that the wafer cleanly breaks along the horizontal and vertical dicing lanes and the etched grooves.

Abstract: The manufacturing method for an electronic circuit device comprises attaching an electronic circuit assembly including a circuit substrate with electronic circuit elements attached to a base, joining lead terminals integrally with the base via frames before molding the lead terminals composed of a different material from that of the base with mold resin, electrically connecting the lead terminals to the electronic circuit assembly, molding the electronic circuit assembly, lead terminals, and flange with mold resin in a batch partially excluding the flange and lead terminals installed on the base, and separating and removing the frames from the lead terminals and base after the molding with the mold resin.

Abstract: A micro leadframe package employing an oblique etching method is disclosed. The micro leadframe package includes a semiconductor chip, an oblique-etched micro leadframe (MLF) having a die pad on which the semiconductor chip is mounted via adhesive means, leads formed along outer sides of the die pad, and tie bars for supporting four corners of the die pad, wires for connecting the semiconductor chip with the leads of the MLF, and an epoxy molding compound (EMC) for encapsulating the semiconductor chip, the MLF, and the wires.

Abstract: A semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame includes a die pad and a plurality of leads properly spaced apart from the die pad, each lead being composed of an inner lead portion and an outer lead portion, wherein the inner lead portion is directed toward the die pad, and the outer lead portion has a terminal. At least a chip is mounted on the die pad, and a first encapsulant is formed for encapsulating the chip, die pad and inner lead portions. An injection-molded second encapsulant is formed for encapsulating the first encapsulant and outer lead portions, but exposing the terminals of the outer lead portions. The second encapsulant made by injection molding can prevent resin flash over the exposed terminals, thereby assuring electrical-connection quality of the semiconductor package.

Abstract: A housing preform consisting of a plate member formed to be bendable in which are formed electronic components and an interconnect electrically connecting the electronic components. The plate member is formed into a shape of the housing unfolded flat. The housing can be formed by folding the plate member. Due to this, it is possible to provide an electronic apparatus comprised of a housing in which electronic components are mounted.

Abstract: A multi-chip module is proposed, which is designed to pack two or more semiconductor chips in a stacked manner over a chip carrier in a single package. The multi-chip module is characterized by the use of adhesive with fillers to allow the topmost chip (i.e. the second chip) superimposed to the bottommost chip (i.e. the first chip) after the first chip electrically connected to the chip carrier. The thickness of the adhesive layer depends on the diameter of the fillers higher than loop height of the bonding wires that is positioned above the active surface of the first chip to prevent the bonding wires connected to the first chip to come in contact with the overlaid chip. Alternatively, stacked chips formed via the adhesive layer can take shorter processing time to be reduced cost and simplify processes than working procedures in the prior art.

Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.

Abstract: An objective of the present invention is to provide a ceramic substrate which does not generate any crack by a shock when the ceramic substrate is fitted to a supporting case or taken off therefrom or any crack resulting from a thermal stress, a thermal shock and the like when the ceramic substrate is heated after the fixation thereof to the supporting case, and which is capable of being prevented from being rotated. The present invention is a ceramic substrate having a conductor layer formed inside thereof or on the surface thereof, wherein a notch is formed.

Abstract: A thermal enhance semiconductor package with a universal heat spreader mainly comprises a carrier, a semiconductor chip and a universal heat spreader. The semiconductor chip is electrically connected to the carrier in a flip-chip fashion and the universal heat spreader is mounted on the back surface of the semiconductor chip. Therein the universal heat spreader has a plurality of through holes for upgrading the efficiency of heat transmission. Moreover, a heat transmission pin is provided in one of the through holes to increase the areas for heat dissipation so as to enhance the thermal performance of the package.

Abstract: A package structure to be mounted on was external printed circuit board includes a package board that is mounted with an exoergic circuit element, and a heat sink that radiates heat from the exoergic circuit element, wherein first pressure for connecting the heat sink to the package board is separated from second pressure for compressing the package board against the printed circuit board.

Abstract: A heat-sinking apparatus (62, 64, 66, and 68) containing a light-transparent pane (72) is configured in a way that enables the pane to be brought into contact with a device (40) such as a semiconductor device without significantly damaging the pane. A main spreader body (120) of a heat spreader (66) in the heat-sinking apparatus preferably consists largely of copper and is connected to the pane, preferably consisting largely of diamond, by way of a combination of metals that facilitates heat transfer from the pane to the heat spreader.

Abstract: A system-in-a-package device installs a second surface of an integrated passive devices (IPD) substrate onto a bearing substrate to achieve electric connection. At least an active device is then installed on a first surface of the IPD substrate by means of flip chip or wire bonding to achieve electric connection. Next, an encapsulant is formed to at least cover the active device or its contacts with the IPD substrate for protection. The system-in-a-package device uses conducting holes of the bearing substrate as contacts with the exterior. Thereby, more functions can be directly integrated into the same package to have the advantages of small package size, increased efficiency, and fast fabrication speed.

Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

Abstract: A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.

Abstract: A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls on either side of each die and/or the interposer provide interconnects for stacking packages and also provide interconnects for module mounting. Each die may be electrically coupled to the interposer using wire bonds, “flip-chip” techniques, or other techniques as appropriate. A redistribution layer may also be formed on the outer surface of a bumped die to create connections between the die circuitry, ball pads and/or wire bonding pads. Because the two die are coupled to each other on opposite faces of the interposer, each package is extremely space-efficient. Individual packages may be stacked together prior to encapsulation or molding to further improve the stability and manufacturability of the stacked package.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Abstract: The present invention provides gas layer formation material selected from the group consisting of acenaphthylene homopolymers; acenaphthylene copolymers; poly(arylene ether); polyamide; B-staged multifunctional acrylate/methacrylate; crosslinked styrene divinyl benzene polymers; and copolymers of styrene and divinyl benzene with maleimide or bis-maleimides. The formed gas layers are used in microchips and multichip modules.