Abstract: A method for transfecting T cells with a nucleic acid molecule comprising a gene such that the gene is expressed in the T cells is described. The T cells are stimulated and proliferating prior to introduction of the nucleic acid molecule.

Abstract: The invention relates to host cells for packing a recombinant adeno-associated virus (rAAV). Said cells contain at least one copy of a first auxiliary construct for expressing at least one AAV Rep protein, and at least one copy of another auxiliary construct for expressing at least one AAV Cap protein. The invention also relates to auxiliary constructs for expressing at least one AAV Rep protein and one AAV Cap protein in a host cell; vector constructs comprising at least one nucleic acid which is heterologous in relation to the AAV; a method for producing a host cell for packing a recombinant adeno-associated virus (rAAV); and the use of the host cell for producing an rAAV.

Abstract: This invention provides a recombinant adenovirus expression vector characterized by the partial or total deletion of the adenoviral protein IX DNA and having a gene encoding a foreign protein or a functional fragment or mutant thereof. Transformed host cells and a method of producing recombinant proteins and gene therapy also are included within the scope of this invention.

Abstract: The present invention relates to AAV expression vectors that allow the introduction and regulated expression of heterologous genes into mammalian tissues and cells. In certain embodiments, vectors of the present invention are ecdysone-inducible AAV expression vectors and AAV expression vectors encoding EcR and RXR. In this system, the heterologous gene is “turned off” until an inducer such as pon A is provided to the tissues or cells. The present invention also provides methods of using inducible AAV expression vectors.

Abstract: The present invention relates to methods and compositions for the production of viral vectors. In particular, the present invention provides methods and compositions for faster, higher titer and higher purity production of viral vectors (e.g. adenoviral vectors). In some embodiments, the present invention provides gutted and helper viruses with identical or similar termini. In other embodiments, the present invention provides terminal protein linked adenoviral DNA. In certain embodiments, the present invention provides template extended adenoviral DNA.

Abstract: Methods for the regeneration of cotton plants are disclosed. The use of selective light conditions, novel compositions of media, and solid support matrices during stages of development resulted in increased frequencies of embryogenesis, embryo maturation and embryo germination. The improved process resulted in higher production frequencies of transformation of cotton.

Abstract: A pH measurement system automatically measures the pH of samples in purge and trap sample concentrators, autosamplers or other sample delivery devices. The pH measurement system includes a pH sensor that is positioned in a pH sample reservoir. The pH sample reservoir may be automatically filled with sample from a sparge vessel, calibrated using liquid having known pH, or rinsed. A controller enables and disables the valves and pump to transmit the liquid to the pH sample reservoir.

Abstract: This invention provides a novel fluorescent particle including a core or carrier particle having on its surface a plurality of smaller polymeric particles or nanoparticles, which are stained with different fluorescent dyes. When excited by a light source they are capable of giving off multiple fluorescent emissions simultaneously, which is useful for multiplexed analysis of a plurality of analytes in a sample. The coupled complex particles carrying on their surface fluorescent nanoparticles, methods of preparing such polymer particles, and various applications and methods of using such particles are claimed.

Abstract: A microfluidic component having a microfluidic channel is joined to an array component having a flexible array substrate. In an embodiment, the array component includes a prefabricated flexible array that couples with the microfluidic component in modular fashion. The modular architecture provides for different combinations of microfluidic components and array components that can be used to create customized processing and analysis tools.

Abstract: A test strip is constructed to include a substrate, a first sample-collection pad adhered to one side of the substrate, the first sample-collection pad having a side notch forming with the substrate a blood sample receiving chamber, and a second sample-collection pad adhered to the outer surface of the first sample-collection pad in parallel to the substrate and defining a blood sample entrance accessible to the blood sample receiving chamber.

Abstract: The invention relates to the treatment of subjects for the purpose inhibiting vaso-occlusive events, including thrombosis and embolism, by administering agents which reduce the number of circulating platelets to low or below normal levels. Methods and pharmaceutical preparations comprising such agents are provided.

Abstract: A competitive immunoassay, dye and method for rapidly detecting the presence of one or more target ligands within a fluid sample suspected of containing such ligand or ligands. The immunoassay comprises a protein-binding membrane, a first absorbent pad, a second absorbent pad, and a third absorbent pad. The protein-binding membrane has at least two regions of antibodies bound thereto for detecting dissimilar ligands. The second absorbent pad has formed therein a colloidal gold tracer having one, and preferably two or more ligand analog protein complexes adhering thereto. To utilize the system, the immunoassay strip is placed within a fluid sample. To the extent the target ligand is absent, a visual indicator will be provided signaling such absence. To the extent the target ligand is present at or above a threshold level, no such visual signal will be produced.

Abstract: A method for fabricating a magnetoresistive device having at least one active region, which may be formed into a magnetic memory bit, sensor element and/or other device, is provided. In forming the magnetoresistive device, a magnetoresistive stack, such as a giant magnetoresistive stack, is formed over a substrate. In addition, a substantially antireflective cap layer formed from titanium nitride, aluminum nitride, and/or other substantially antireflective material, as opposed to the materials commonly used to form a cap layer, is formed over the magnetoresistive stack. The substantially antireflective cap layer is usable as an etch stop for later processing in forming the magnetic memory bit, sensor element and/or other device.

Abstract: A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method comprises depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.

Abstract: Magnetic tunnel junction devices can be fabricated using a two-step deposition process wherein respective portions of the magnetic tunnel junction stack are defined independently of one another.

Abstract: A method and apparatus performing process end point detection in a semiconductor substrate processing system by monitoring for an increase in a flow of backside gas above a predetermined limit.

Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n≧1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.

Abstract: A method for adjusting the thickness of a thin semiconductor material layer. The technique includes measuring the layer to establish a thickness profile, comparing the measured thickness profile with stored standard profiles, wherein each standard profile is stored in association with respective thickness adjustment specifications, selecting a stored standard profile to associate the layer with the respective thickness adjustment specification, and adjusting the thickness of the layer in accordance with the thickness adjustment specification. The invention also provides apparatus for adjusting the thickness of a thin semiconductor material layer.

Abstract: A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MEMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.

Abstract: A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.

Abstract: An etching signal layer which is formed by a sequential gas phase deposition with a layer thickness of less than 20 nanometers, and which is composed of a metal oxide or of an oxide of rare earths is provided between a substrate, which is located underneath it, and a process layer. The etching signal layer produces an etching signal, which is independent of the stack layer systems that are to be removed, and contains two or more materials that contain silicon, and can be removed quickly and with narrow process tolerances. One substrate surface of the substrate is protected irrespective of the topography. Etching methods based on the etching signal layer can be carried out precisely, and can be used in a variable manner.

Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders.

Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.

Abstract: Provided is a method of manufacturing a semiconductor device, which is adapted to prevent the deposition of a material on a laser light emitting edge, thereby enabling an improvement in longevity characteristics of a laser. A base having a laser chip mounted thereon is irradiated with an energy beam having a shorter wavelength than an oscillation wavelength of the laser chip. Photolysis and oxidation caused by the energy beam cause the removal of an adherent from the overall base or the deterioration thereof, and incidentally, the adherent is derived from an adhesive sheet used to attach the laser chip to the base, or the like. Preferably, laser light or ultraviolet light, for example, is used as the energy beam. Alternatively, the base having the laser chip mounted thereon may be irradiated with plasma so as to remove the adherent utilizing an ion cleaning effect of the plasma. After irradiation, a top is mounted to the base so as to shut off the laser chip from the outside.

Abstract: The integrated optical circuit of the present invention includes a substrate with a first cladding layer. A first core layer having one or more waveguiding elements is formed on the first cladding layer. A second cladding layer surrounds the waveguiding elements of the first core layer; the refractive index of the first and second cladding layers are selected to be less than the refractive index of the waveguiding element(s). Through simultaneous cladding material deposition and cladding material removal, the second cladding layer as deposited is substantially self-planarized, enabling further layers to be positioned on the second cladding layer without necessitating intermediate planarization. Further, the present invention permits planar waveguide cores having submicron core spacings to be covered by a subsequently-deposited cladding layer without cladding gaps, seams or other deleterious cladding defects.

Abstract: A reflective layer 10 is formed on a back surface 11b of a sapphire substrate 11. The reflective layer 10 includes an extension portion 10a which extends so as to cover almost all the sidewalls 21a of a light-emitting device in the vicinity of the sapphire substrate. Thus, since adhesion between the reflective layer 10 and the substrate is greatly enhanced in the vicinity of the periphery of the surface on which the reflective layer is formed (the substrate back surface 11b) by virtue of formation of the aforementioned extension portion 10a, exfoliation of the reflective layer 10 from the substrate is prevented. Therefore, even when a process in which the reflective layer 10 is attached onto an adhesive sheet to thereby secure the light-emitting device 100 on the sheet is employed, generation of a defective product having an exfoliated reflective layer can be prevented.

Abstract: On a sapphire base (701), a GaN layer (702) and a substrate separating layer (703) are sequentially deposited, and the GaN layer (702) and the substrate separating layer (703) are processed to have a plurality of ridge stripes (702a) and recess portions (702b). Subsequently, a GaN based semiconductor layer (706) is grown on a C surface (703c) of the substrate separating layer (703) exposed on top of ridge stripes (702a) as seed crystal. The C surface (703c) of the substrate separating layer (703) is irradiated with a laser beam (802) to remove the substrate separating layer (703), thereby separating the GaN based semiconductor layer (706) from the sapphire base (701).

Abstract: A method includes (a) putting a multielectrodic chip lithographed in a wafer that contains between 2 and 2000 individually polarisable electrodes, in contact with a solution or suspension that includes modified colloidal particles with a (bio)chemical recognition element; (b) applying to an electrode of the multielectrodic chip, a potential between −1 and +2V vs. Ag/AgCl saturated, for a period of time between 1 and 300 seconds; (c) washing the chip after this stage (b); and (d) repeat the steps (b) and (c) as many times as needed to deposit a (bio)chemical recognition element, same or different to the one or ones previously deposited, on each one of the electrodes of that chip. The method is applicable for the fabrication of multisensors, particularly in chips and arrays for analytical and diagnostic applications.

Abstract: A method is disclosed for encapsulating micromechanical elements or features on a substrate. In accordance with the method, a first substrate (111) is provided which has a patterned surface (113). A seed metallization (121) is then deposited onto the patterned surface, and a structural material layer (123), which preferably comprises copper, is electroplated onto the seed metallization. A solder (125), such as SnCu, is electroplated onto the metal layer, and the seed metallization, the structural material layer and the solder are removed from the first substrate as a cohesive structure (127), through the application of heat or by other suitable means, such that a negative replica of the patterned surface is imparted to the structure. The structure may then be placed on a second substrate (129) such that the solder is in contact with the second substrate, after which the solder is reflowed.

Abstract: Disclosed are methods of plasma etching through a substrate while preventing rapid leakage of heat transfer fluid during the etch process, protecting process chamber hardware underlying said substrate, and separating components within said substrate while maintaining said components in a position relative to other components within said substrate. The method involves application of a disposable protective barrier layer to the backside of the substrate prior to etching and then removing the barrier layer subsequent to etching.

Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.

Abstract: A thin-film opto-electronic device on a conductive silicon-containing substrate includes a sequence of layers. The layers include a layer of a porous medium preferably a porous silicon, on a substrate. The porous layer has both light diffusing and light reflecting properties. In addition, a non-porous layer is located on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer. The first region is of a first conductivity type acting as a light absorber and the second region has a conductivity of a second type, different from said first conductivity type. The sequence of layers is such that optical confinement is realised in the device.

Abstract: A method for joining a semiconductor integrated circuit (IC) chip in a flip chip configuration, via pillar bump, to solderable metal contact pads, leads or circuit lines on the ciruitized surface of a chip carrier, as well as the resulting chip package, are disclosed. The semiconductor device is attached to the substrate via no flow underfill under thermal compression bonding. Integration of this structure and assembly method enables to incorporate low coefficient of thermal expansion (CTE) no flow underfill and achieve high assembly yield, especially for lead free bumps. The present invention provides a solution for a flip chip package with fine pitch, high pin count and lead free requirements.

Abstract: A substrate includes a plurality of insulation layers forming a laminated structure and a built-in capacitor formed in the laminated structure, wherein the laminated structure includes a layer of baked organic polysilane.

Abstract: A method for separating dies on a wafer includes etching channels around the dies on a first side of the wafer, mounting the first side of the wafer to a quartz plate with an UV adhesive, and grinding a second side of the wafer until the channels are exposed on the second side of the wafer. At this point, the dies are separated but held together by the UV adhesive on the quartz plate. The method further includes mounting a second side of the wafer to a tack tape, exposing UV radiation through the quartz plate to the UV adhesive. At this point, the UV adhesive looses its adhesion so the dies are held together by the tack tape. The method further includes dismounting the quartz plate from the first side of the wafer and picking up the individual dies from the tack tape.

Abstract: A thermally decomposable sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The thermally decomposable sacrificial material may be removed without damaging or removing the dielectric layer. The thermally decomposable sacrificial material may be a combination of organic and inorganic materials, such as a hydrocarbon-siloxane polymer hybrid.

Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.

Abstract: The present invention relates to a semiconductor device in which a semiconductor element and a substrate are disposed face-to-face, the mixture of the thermoplastic resin and the thermosetting resin is provided between the semiconductor element having the electrode formed thereon and the substrate having the wiring pattern formed thereon, the mixture holding in contact the electrode of the semiconductor element and the wiring pattern of the substrate.

Abstract: Methods and systems of protecting substrates that are intended for use in fluidic devices are described. In accordance with one embodiment, sealant material is applied over one or more edges of at least one multi-chip module substrate that is intended for use in a fluidic device. At least one edge has an exposed electrical interconnect and the sealant material is applied over less than an entirety of the substrate and sufficiently to cover the exposed electrical interconnect. The sealant material is exposed to conditions effective to seal the one or more edges.

Abstract: A method of forming a polysilicon thin film transistor is disclosed in the present invention. The method includes forming a buffer layer on a transparent substrate, forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer into a polysilicon layer using a sequential lateral solidification (SLS) method, patterning the polysilicon layer to form a polysilicon active layer, performing a rapid thermal annealing (RTA) process to the polysilicon active layer under a H2 atmosphere, performing a rapid thermal oxidation (RTO) process to form a silicon-oxidized layer on the polysilicon active layer after the RTA process, and forming a metal layer over the transparent substrate to cover the silicon-oxidized layer.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A flexible metal foil substrate organic light emitting diode (OLED) display and a method for forming the same are provided. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, or Kovar, having a thickness in the range of 10 to 500 microns; planarizing the metal foil substrate surface; depositing an electrical isolation layer having a thickness in the range of 0.5 to 2 microns overlying the planarized metal foil substrate surface; depositing amorphous silicon having a thickness in the range of 25 to 150 nanometers (nm) overlying the electrical insulation layer; from the amorphous silicon, forming polycrystalline silicon overlying the electrical insulation layer; forming thin-film transistors (TFTs) in the polycrystalline silicon; and, forming an electronic circuit using the TFTs, such as an OLED display.

Abstract: A first contact hole (6) is formed penetrating a gate insulating film (5), on which a gate electrode (7g) is formed and simultaneously a first contact (7s, 7d) is formed in the first contact hole. A second contact hole (9) penetrating an interlayer insulating film (8) is formed, and a second contact (10) is formed in the second contact hole (9). A third contact hole (11) is formed penetrating a planarization film (26), and an electrode (40) is formed in the third contact hole (11). By using a plurality of contact holes for electrically connecting the electrode (40) and a semiconductor film (3), the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.

Abstract: [Object] To provide a method for forming a high-performance thin-film at low cost using a liquid material in safety, an apparatus for forming a thin-film, a method for manufacturing a semiconductor device, an electro-optical unit, and an electronic apparatus.

Abstract: In crystallizing an amorphous silicon film by illuminating it with linear pulse laser beams having a normal-distribution type beam profile or a similar beam profile, the linear pulse laser beams are applied in an overlapped manner. There can be obtained effects similar to those as obtained by a method in which the laser illumination power is gradually increased and then decreased in a step-like manner in plural scans.

Abstract: A method for manufacturing a semiconductor device having an n-type MIS transistor and a p-type MIS transistor comprises forming a first gate insulating film in a first area where the n-type MIS transistor is to be formed, depositing a first conductive film on the first gate insulating film in the first area, the first conductive film containing silicon, a metal element selected from tungsten and molybdenum and an impurity element selected from phosphorus and arsenic, forming a second gate insulating film in a second area where the p-type MIS transistor is to be formed, and forming a second conductive film on the second gate insulating film in the second area, the second conductive film having a work function higher than that of the first conductive film.

Abstract: A method for manufacturing a semiconductor device includes forming a barrier layer on an individual device formed on a semiconductor substrate and including a MOS transistor. An ozone process is performed on the barrier layer. A pre-metal dielectric (PMD) layer is then formed on the barrier layer.

Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Abstract: A method for fabricating a semiconductor device comprises the steps of: forming a polysilicon film 26 on a silicon substrate 10; removing a natural oxide film 28 on the surface of the polysilicon film 26; forming a homogeneous chemical oxide film 30 on the surface of the polsysilicon film 26 having the natural oxide film 28 removed; forming a silicon oxide film 32 to be used as a hard mask on the polysilicon film 26 with the chemical oxide film 30 formed on; and etching the polysilicon film 26 with the silicon oxide film 32 as a mask to form a gate electrode 16 of the polysilicon film 26.

Abstract: A phase changeable memory cell that includes a substrate, a bottom electrode, a phase changeable material layer pattern, and a top electrode. The bottom electrode is on the substrate. The phase changeable material layer pattern is on the bottom electrode. The top electrode is on the phase changeable material layer pattern, and has a tip that extends toward the bottom electrode.