Abstract: A gate electrode is formed of a laminate structure comprising a plurality of conductive layers such that the width along the channel of a lower first conductive layer is larger than that of an upper second conductive layer. The gate electrode is used as a mask during ion doping for forming an LDD. A mask pattern for forming the gate electrode is processed into an optimum shape in combination with dry etching so that the LDD overlapping with the gate electrode (Lov) is 1 &mgr;m or more, and preferably, 1.5 &mgr;m or more.

Abstract: Methods of fabricating a through-substrate interconnect for a microelectronics device, the device including a substrate having a frontside and a backside, are disclosed. Some embodiments of the methods include forming a circuit element on the frontside of the substrate, forming a trench in the backside of the substrate that extends to the circuit element, forming a layer of an insulating polymeric material in the trench, removing sufficient polymeric material from the layer of insulating polymeric material to at least partially expose the circuit element, and forming an electrically conductive interconnect layer in the trench, wherein the interconnect layer is in electrical communication with the circuit element.

Abstract: A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

Abstract: The disclosed invention relates to materials and processes for creating particle-enhanced bumps on electrical contact surfaces through stencil or screen printing processes. The materials are mixtures of conductive ink, conductive paste, or conductive adhesive and conductive hard particles (104). The process involves depositing the mixture (108) onto electrical contact surfaces by stencil printing, screen printing, or other dispensing techniques (110). In another embodiment, the ink, paste, or adhesive is first stenciled or screen printed and the particles are then applied on top of the ink, paste, or adhesive deposit. Once cured (114), the deposition provides a hard, electrical contact bump on the contact surface with a rough, conductive, sandpaper-like surface that can be easily connected to an opposing contact surface without any further surface preparation of either surface.

Abstract: A solder bump structure and laser repair process for memory device include forming a first dielectric layer on a bump pad of a semiconductor wafer. After that, the first dielectric layer is etched to form a contact hole and to expose portions of the bump pad. A second dielectric layer is then formed on a surface of the semiconductor wafer outside of the contact hole. An under bump metallurgy (UBM) process is performed to form a metal layer on a surface of the contact hole, and a solder bump is formed on the metal layer. Finally, the laser repair process for memory device is completed.

Abstract: A small semiconductor device which can be fabricated at the wafer level has high reliability of external terminals with respect to distortion caused by differential thermal expansion between a semiconductor element of the device and a printed circuit board and has superior electrical performance achieved through reduced static capacitance of interconnections. A thick stress-moderating layer with a low elastic modulus is interposed between the semiconductor element and interconnections and lands and improves the reliability of external terminals by absorbing distortion caused by the differential thermal expansion. The thick stress-moderating layer also reduces static capacitance between the interconnections and internal interconnections of the semiconductor element. Even around element electrodes, where the stress-moderating layer is not formed, static capacitance is reduced by an insulating film interposed between the interconnections and the semiconductor element.

Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.

Abstract: A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.

Abstract: A method for manufacturing a semiconductor device includes: (i) depositing a sacrificial layer made of an organic polymer such as benzocyclobutene on a substrate having a circuit formed thereon; (ii) etching the sacrificial layer except for a portion where air gaps are to be formed; (iii) depositing a low-dielectric layer over the substrate until the portion for air gaps is entirely enclosed in the low-dielectric layer; (iv) etching the low-dielectric layer to form via holes and trenches there through; (v) prior or subsequent to step (iv), removing the portion for air gaps; and (vi) depositing copper in the vias and trenches which are filled with the copper contacting a surface of the substrate.

Abstract: An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in different, mutually separate line planes. A read/write current can be impressed in respective selection lines for writing to each MRAM memory cell and for reading an information item written therein. In this magnetoresistive semiconductor memory configuration, selection lines that serve for reading a cell information item are in each case located in separate first and second line planes in direct contact with the memory cells. A third and a fourth line plane are spatially separated and electrically isolated from the first and second line planes and are occupied by write selection lines for writing a cell information item.

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract: A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to initially deposit a thin underlying, first component of the barrier layer, while an atomic layer deposition (ALD), procedure is then employed for deposition of an overlying second barrier layer component. The underlying, thin barrier layer component obtained via PVD procedures is comprised with the desired properties needed to interface the porous, low k layer, while the overlying barrier layer component obtained via ALD procedures exhibits excellent thickness uniformity.

Abstract: A barrier metal layer constituted of a TiN layer and a Ti layer is formed on a surface of an interlayer insulating film and on an inside surface of an interconnection recess formed in the interlayer insulating film while a substrate is maintained at a temperature of at least 200° C. and lower than 300° C. The interconnection recess is filled with a conductive layer and an extra part of the conductive layer that is deposited on the interlayer insulating film is removed through such a polishing process to form a conductive plug. In the process of forming the barrier metal layer, as the substrate is maintained at the temperature, the residual stress in the deposited barrier metal layer can be reduced. Accordingly, it is achieved to suppress peeling which occurs at the interface between the barrier metal layer and the interlayer insulating film in the polishing process.

Abstract: A first depressed portion is formed on an insulating film. A burying material is applied onto the first depressed portion and the insulating film to bury the first depressed portion. Chemical mechanical polishing of the burying material is performed until the insulating film is exposed, thereby leaving the burying material only in the first depressed portion. A resist having a pattern of a second depressed portion that overlaps the first depressed portion is formed on the insulating film in which the burying material has been buried. The burying material and the insulating film are etched to a predetermined depth using the resist as a mask to form the second depressed portion. The resist and the burying material left are removed after the step of etching. A conductive material is deposited in the first depressed portion and the second depressed portion.

Abstract: A layer of antireflective coating (ARC) material for use in photolithographic processing. In one embodiment the ARC material has the formula SiwOxHy:Cz, where w, x, y and z represent the atomic percentage of silicon, oxygen, hydrogen and carbon, respectively, in the material and where w is between 35 and 55, x is between 35 and 55, y is between 4 and 15, z is between 0 and 3 and the atomic percentage of nitrogen in the material is less than or equal to 1 atomic percent.

Abstract: A process for fabricating an integrated electrical circuit comprises the formation and then the removal of conducting inserts. Components of the electrical circuit are incorporated into insulating materials superposed on top of a substrate. The process makes it possible to provide an exclusion volume around certain components sensitive to electrostatic coupling, while giving each insulating material a planar surface at the end of a polishing step.

Abstract: A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.

Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air.

Abstract: In the present invention, a metal halide film is grown which is then reduced to the metal film rather than growing the metal film directly on the substrate surface. In certain embodiments, a metal halide film is grown from at two precursors: a halogen-containing precursor and a metal-containing precursor. The metal halide film is then exposed to a reducing agent to form the metal film. In certain preferred embodiments, the metal halide film is exposed to the reducing agent prior to the completion of the growing step.

Abstract: A method for forming a cobalt silicide layer employs a sequential treatment of a silicon substrate with a hydrofluoric acid material followed by a wet chemical oxidant material. A cobalt material layer is then formed upon the sequentially treated silicon substrate and the silicon substrate/cobalt material layer laminate is thermally annealed to form a cobalt silicide layer. Use of the wet chemical oxidant material for treating the silicon substrate provides the cobalt silicide layer with enhanced electrical properties.

Abstract: A method of manufacturing a semiconductor device includes the steps of: taking a semiconductor wafer (8); defining non-conductive region (11) and a conductive region (15) providing electrical contact means (10) at the conductive region; and separating the wafer into a plurality of dies. By using wafer scale fabrication, thousands of devices may be packaged simultaneously in single process steps without significant operator intervention compared to the conventional packaging processes. An insulating wafer (12) may be located over the semiconductor wafer and bonded thereto, the insulating wafer having a plurality of tapered apertures (13) therethrough which are aligned with conducting regions of the semiconductor wafer.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.

Abstract: The invention is directed to a fabrication method of copper interconnects using dual damascene processing. Using silicon to provide an active surface, palladium can be selectively deposited on silicon by immersion plating technique. After palladium deposition (about 1000 A thick), either a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus is deposited on palladium layer using electroless plating technique. This cobalt/phosphorus, cobalt nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier. Via and trench are filled up by copper from electroless copper plating method and CMP is used to remove excess copper and planarize/polish the copper/dielectric surface.

Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.

Abstract: A method for manufacturing structural elements provides a first part with a surface that is substantially copper and a second part with a surface of a metal. The surface of the first part is coated with a hard layer which is stable at a temperature of at least 80° C. and which, at this temperature, forms an oxygen diffusion barrier when exposed to ambient. The layer has a barrier effect similar to that of an aluminum oxide layer formed in a standard environment on aluminum. The surfaces are connected to each other by bonding with heating to at least 80° C.

Abstract: Processing a die that has an edge and a substrate upon which a layer of moisture permeable material is disposed. The moisture permeable material extends to the edge of the die. One embodiment comprises interrupting the layer of moisture permeable material to form a gap at a boundary near the edge, thereby to substantially block movement of moisture through the gap of the moisture permeable material.

Abstract: In determining an endpoint of etching a substrate, light that is directed toward the substrate is reflected from the substrate. A wavelength of the light is selected to locally maximize the intensity of the reflected light at an initial time point of the etching process. The reflected light is detected to determine an endpoint of the substrate etching process.

Abstract: Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.

Abstract: Provided herein is a system architecture of semiconductor manufacturing equipment, wherein degas chamber(s) are integrated to the conventional pass-through chamber location. Also provided herein is a system/method for depositing Cu barrier and seed layers on a semiconductor wafer. This system comprises a front opening unified pod(s), a single wafer loadlock chamber(s), a degas chamber(s), a preclean chamber(s), a Ta or TaN process chamber(s), and a Cu process chamber(s). The degas chamber is integrated to a pass-through chamber. Such system may achieve system throughput higher than 100 wafers per hour.

Abstract: A method for improving the etch behavior of sidewall spacers in the fabrication of a CMOS device is disclosed. The etch rate of the material of the sidewall spacers depends on the implantation conditions. Thus, the etch rates are different for N-type and P-type transistors. To remove the sidewall spacers properly, the etch rates are altered by an implantation of ions, thereby modifying the structure of the material of the sidewall spacers and increasing the etch rate of the material. The increased etch rate leads to a shorter process time in the spacer removal process. Thus, the surrounding regions are less affected by the removal process and the device reliability and performance is improved.

Abstract: In a semiconductor device having a semiconductor film crystallized by using a metal element, it is an object to provide a technique for reducing the crystal defects in a semiconductor film, and a technique for forming a semiconductor film with high crystallinity by effectively removing impurity metal elements.

Abstract: A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes 64 formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device.

Abstract: Particles adhering to the surface of a substrate are removed by physical action of injection of droplets or megasonic vibrations or by combination of the physical action and slight etching on the surface of the substrate. On the other hand, metal contaminants adhering to the surface of the substrate are altered to hydroxides with an alkaline solution and thereafter dissolved with an acid solution to be removed. Thus, it is possible to rapidly process the substrate while minimizing the quantity of etching on the surface of the substrate.

Abstract: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline, with a cap layer formed on the top of the wordline. A dielectric layer is formed on the substrate that is not covered by the wordline and the cap layer. A resist layer with a line/space pattern is formed on the dielectric layer and the cap layer, while the line/space pattern has a first extending direction different to a second extending direction of the cap layer. After removing the cap layer not covered by the resist layer, a code mask layer is formed over the substrate. An ion implantation step is performed to implant dopants into a predetermined code channel region by using the code mask layer, the dielectric layer and the remained cap layer as a mask.

Abstract: Methods of forming structures using metal sacrificial layers are provided. A nanoscopic void is formed in a structure having a substrate by defining a metal pattern on the substrate, covering the metal pattern with a material, and removing the metal, thereby creating the nanoscopic void where the metal previously existed.

Abstract: A magnetic clad bit line structure (274) for a magnetic memory element and its method of formation are disclosed. The magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding capping layer (272). The magnetic cladding sidewalls (262) are formed by sputtering a material within the trench (258) and selectively resputtering the material deposited at the bottom of the trench (258) onto the adjacent sidewalls of the trench (258).

Abstract: An improved method of patterning photoresist is described that is resistant to poisoning from nearby nitrogen containing layers. An inert resin is used to fill a via in a damascene stack. Then a second stack comprised of a barrier layer, a BARC, and a photoresist are formed on the damascene stack. The barrier layer is preferably an i-line or Deep UV photoresist comprising a polymer with hydroxy groups that can attract nitrogen containing compounds and prevent them from diffusing into the photoresist and causing scum during the patterning step. The photoresist pattern is etch transferred through underlying layers to form a trench in the damascene stack. Optionally, the resin is replaced by the barrier layer which fills the via and forms a planar layer on the damascene stack. The barrier layer is independent of exposure wavelength and can be readily implemented into manufacturing and is extendable to future technologies.

Abstract: The present invention provides a process for selectively thermally transferring insulators onto organic electroluminescent stacks or layers to electronically isolate adjacent devices upon deposition of electrode material. This can allow the formation of top electrodes for a plurality of organic electroluminescent devices on a substrate via one deposition step to form a single common top electrode or a plurality of electrodes patterned by shadowing due to the presence of the insulators.

Abstract: An improved method of forming a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A first part of the second hard masking layer and a first part of the first hard masking layer are etched to form an etched region within the hard mask that exposes a first portion of the dielectric layer. That etched region is filled with a sacrificial material. After etching through a second part of the second hard masking layer, the remainder of the sacrificial material is removed prior to subsequent processing.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: In a method for dry-etching a coating by use of reactive gas which is activated, a second insulating layer containing carbon atoms which is formed on a first insulating layer containing carbon atoms is ashed by use of a gas containing carbon atoms and at least one of oxygen atoms, nitrogen atoms and hydrogen atoms. By using the above gas, the second insulating layer containing carbon atoms which is formed on the first insulating layer which is an underlying layer can be efficiently ashed and removed without removing carbon atoms in the side surface of the grooves formed in the first insulating layer and etching the side surface thereof. Thus, the side surface of the groove formed in the first insulating layer will not be modified or deformed.

Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.

Abstract: One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the method including: (a) depositing a barrier layer over the field and inside surfaces of the at least one opening; (b) depositing a substantially non-conformal seed layer and a substantially conformal seed layer over the barrier layer, wherein the substantially non-conformal seed layer is deposited by a PVD technique and the substantially conformal seed layer is deposited by a CVD technique, and wherein the thickness of the substantially non-conformal seed layer is in the range of about 100 Å to about 3,000 Å on the field and the thickness of the substantially conformal seed layer is in the range of about 50 Å to about 500 Å on the field, the substantially non-conformal and the substantially conformal seed layers do n

Abstract: A process for annealing large-area multilayer bodies by supplying a quantity of energy at an annealing rate of at least 1° C./s. To suppress temperature inhomogeneities during the annealing, different partial quantities of the quantity of energy are supplied to the layers of the multilayer body with a local and temporal resolution. The multilayer body is annealed in a container which has a base and a cover made from glass-ceramic. The process is used to produce a thin-film solar module.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A post-etch residue cleaning composition for cleaning ashed or unashed aluminum/SiN/Si post-etch residue from small dimensions on semiconductor substrates. The cleaning composition contains supercritical CO2 (SCCO2), alcohol, fluoride source, an aluminum ion complexing agent and, optionally, corrosion inhibitor. Such cleaning composition overcomes the intrinsic deficiency of SCCO2 as a cleaning reagent, viz., the non-polar character of SCCO2 and its associated inability to solubilize species such as inorganic salts and polar organic compounds that are present in the post-etch residue and that must be removed from the semiconductor substrate for efficient cleaning. The cleaning composition enables damage-free, residue-free cleaning of substrates having ashed or unashed aluminum/SiN/Si post-etch residue thereon.