Abstract: A method and apparatus for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors, and shaped junctions that may be used as qubits for quantum computing.

Abstract: A driver transistor supplying a data write current to a write digit line is arranged to have its gate length direction along the same direction with a write digit line. Further, the write digit line has a reinforced portion arranged between an ordinary portion corresponding to a region where memory cells are arranged and a power supply interconnection, having interconnection cross sectional area greater than that of the ordinary portion. With this configuration, the chip area can be decreased as an increase of layout pitch of the memory cells dependent on the driver transistor size is prevented, and operational reliability can also be improved as a local increase of the current density on the write digit line is avoided.

Abstract: A nonvolatile semiconductor storage apparatus comprises: a first memory cell capable of storing a plurality of data values; a second memory cell capable of storing a plurality of data values; a resistance regulation section capable of regulating resistance, which regulates resistance such that a difference between a resistance value of a first connection line connected to the first memory cell and a resistance value of a second connection line connected to the second memory cell is reduced.

Abstract: There is provided a boosting circuit in which a boosting efficiency is enhanced without increasing a chip area, and a time required for reaching a desired boosting voltage different in a voltage level and current ability is shortened.

Abstract: Disclosed is a flash memory device and a program verification method thereof which can prevent a misjudgment as to whether flash memory cells are programmed or not. The flash memory device includes: a program verification voltage generator for variably generating program verification voltages used to verify whether the flash memory cells are programmed or not and a word line level selector for transferring the program verification voltages to word lines connected to control gates of the flash memory cells. The flash memory cells that are verified as uncertain as to whether the flash memory cells are programmed or not can be completely programmed since the program verification operation is carried out with program verification voltage levels that are changed according to the selective activations of the program verification control signals.

Abstract: A nonvolatile memory device of the present invention performs programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Abstract: The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased.

Abstract: A transition of an external enable signal generates a reset pulse to a counter to set the counter into a known state. The counter, clocked by the external clock signal, generates a clock signal that is decoded by a fuse decoder circuit. The fuse decoder circuit outputs a selection signal to a trim circuit. The trim circuit produces a voltage selection signal, such as a resistance value, that is indicated by the selection signal for use by an internal reference voltage generation circuit. The output of the internal reference voltage generation circuit is compared to the external reference voltage. The counter circuit continues counting until the internal reference voltage is equal to or greater than the external reference voltage. The counter is disabled and the final count that produced the proper internal reference voltage is stored in non-volatile memory cells for future use.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: There are provided an information recording apparatus for recording information so as to permit to carry out seamless reproduction, when switching a recording layer of an optical disk having a double-layer structure, which is in reproduction condition to another recording layer during reproduction; and an information record medium on which information can be recorded by the information recording apparatus.

Abstract: A semiconductor integrated circuit device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction, and a TMR device including a first magnetic layer, a nonmagnetic layer, and a second magnetic layer. The planar shape of the TMR device coincides with the planar shape of the crossing portion between the first wiring and the second wiring.

Abstract: An apparatus is provided for configuring data cells received in a telecommunications process in a continuous stream of data cells of fixed length and each comprising a header and a user data part. The apparatus comprises a processing unit, adapted and configured so that it is able to check data cells for the presence of empty cells, discard the data cells consisting of empty cells and then check the user data parts of the data cells less the empty cells—without the need to buffer the same—as to whether they belong together, and then to assemble the user data parts of the data cells belonging together into a frame. The apparatus may be integrated in, a modem and is also particularly suitable for data cells existing as ATM cells for receiving by an ATM system. The invention relates in addition to a correspondingly sequencing method for configuring data cells.

Abstract: The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system comprises one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values. The system comprises a reverse power plug orientation protection circuit coupled between the hard disk drive power plug receptacle and at least one of the one or more hard disk drive integrated circuit chips.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A sensing circuit comprises a charge integrating sense amplifier 4 serially coupled to a discriminator 6. The sensing circuit can be used to sense the logic status of the cells in a random access memory (RAM) system, including ferroelectric RAMs. The use of a charge integrating sense amplifier enables the effect of bit line capacitance intrinsic to RAM circuits to be overcome and also provides efficient charge to voltage conversion gain.

Abstract: A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

Abstract: In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.

Abstract: The invention includes a memory cell sensor. The memory cell sensor includes an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment of the invention includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.

Abstract: Capacitors are provided for changing the voltage level of data lines, respectively, in a data reading operation. A signal line electrically coupled to capacitors is provided. Capacitors charge data lines in accordance with the voltage level of signal line by capacitive coupling. Thus, data lines can be charged quickly to achieve a fast data reading operation.

Abstract: A portable information storage device 10 comprises a solid-state electronic memory (not shown), and a tubular enclosure 12 for the memory, the device having a neck 14 on which is mounted a connector 16 (e.g. a 62 GB military connector) for serial data communication with the memory, the enclosure having an access opening 18 closed by a closure member 20.

Abstract: A semiconductor device has a memory cell array composed of a plurality of electrically rewritable nonvolatile memory cells and output disabling means for disabling data held in the memory cell array from being outputted to the outside. The output disabling means disables the outputting of the data when the power supply is turned ON and removes the disabling of the outputting of the data if a specified operational procedure is performed to the memory cell array.

Abstract: A recording medium which has a high effective recording density and a high error correcting capability, and a recording apparatus and a reproducing apparatus for the same are provided. The recording apparatus comprises an encoding unit, which encodes input data by an encoding scheme including a run length limit encoding scheme to thereby generate encoded data and divide and output one data stream formed by said encoded data into a plurality of data blocks, and a data adding unit which adds data having the same value as the last one bit of encoded data of said precedent data block to the top of at least one of said data blocks. Using the recording apparatus, in each data recording area of a recording medium which comprises pre-pit areas and a plurality of data recording areas which are divided by said pre-pit areas, a data block which contains said added data is recorded.

Abstract: A semiconductor memory device is provided. A first insulating layer having a gate electrode is formed on a semiconductor substrate. A second insulating layer is formed on the first insulating layer, and the second insulating layer has bit lines covered with bit line isolation layers, buried contact plugs formed between the bit lines, and a first metal contact plug connected to the semiconductor substrate through the first insulating layer. A silicon nitride layer is formed on the second insulating layer. A third insulating layer is formed on the silicon nitride layer, and the third insulating layer has a second metal contact plug connected to the first metal contact plug through the silicon nitride layer. The second insulating layer includes a first landing stud connected to the gate electrode through the first insulting layer. The bit lines include a direct contact plug under one of the bit line. The first landing stud is simultaneously formed with the direct contact plug.

Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A mode control bit is used to adjust a mode of a memory device. The mode control bit is stored in a non-volatile memory location and selects between a data rate, low power consumption mode and a higher power, fast programming mode. In the low power consumption mode the mode control bit reduces the rate at which data bits are programmed into the memory device.

Abstract: A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Abstract: Disclosed are a semiconductor memory device and a layout method thereof.

Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.

Abstract: A method and apparatus is provided for controlling a data strobe. A latency of operation relating to a data operation of a device is determined. A delay lock loop signal is generated for the data operation of the device. The delay lock loop signal is compared to an external clock to determine a phase difference. A determination is made as to whether the delay lock loop signal is early based upon the phase difference. A signal is adjusted in response to the latency of operation is performed based upon the determination that the delay lock loop signal is early.

Abstract: A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. A second count is then generated, and represents a data bit having a first known logic state stored in the selected memory cell. A third count is then generated, and represents a data bit having a second known logic state stored in the selected memory cell. The logic state of the initial unknown data bit stored in the selected memory cell is then determined from the first, second, and third counts.

Abstract: A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

Abstract: A volumetric feed hopper is provided with a variable speed drive to vary the feed rate of the hopper. The hopper is further provided with adjustable legs with pivoting feet to enable the hopper to be installed a various heights and on uneven surfaces.

Abstract: The present invention provides an apparatus and method for mass transfer of gas or other fluids into a liquid and/or liquid suspension. The present invention is preferably used in conjunction with waste treatment processes and/or fermentation processes that are commonly carried out in a mixing vessel. In such an arrangement, the mass transfer process is utilized to contact air to liquid in a mixing vessel or aeration basin.

Abstract: Flowable materials, such as cement and sand, are mixed by placing the materials to be mixed in an elongate flexible resealable bag 10 having handles 12 at its opposite ends and alternately raising and lowering the handles 12 relative to one another to cause the materials to tumble alternately in opposite directions within the bag. The bag is fashioned to have a greater girth at its centre than near its ends.

Abstract: An enclosed implantable material mixing system is described herein. The system uses an enclosable vial or container into which bone cement mixture may be mixed by agitation. The bone cement mixture may be made of a combination of polymer and liquid monomer, but because of the method of agitation, e.g., shaking the vial and its contents, the ratio of the monomer-to-polymer is critical. A desirable weight ratio of the monomer-to-polymer is about 0.3 to about 1, and more preferably about 0.53 to about 0.63, and is more preferably about 0.57. The vial or container may also include a free-floating, or disassociated, agitator to aid with the mixing process. To prepare the composition, the vial and its contents may be capped and shaken until the mixture dissolves completely. The contents of the vial are then allowed to sit and undergo a solvation process at the end of which the mixture may be shaken again and then poured out for use.

Abstract: A device for holding and rotating cylindrical sample containers for use in analytical instrumentation. The device maintains the surface of material in the container at a constant location during rotation by using a series of fixed contact points. The drive wheel is tension to secure the sample container to the fixed supports and to automatically accommodate different size containers without adjustment.

Abstract: Slab gels held on trays are agitated in a staining or fixing solution by an apparatus that includes a tray carrier that holds a stack of slab gel trays, a tank that receives the tray carrier with sufficient excess room to allow the carrier to move back and forth within the tank, and a motor with a crankpin that is connected to the tray carrier in a reciprocating connection that translates the circular path of the crankpin into a linear path of movement of the tray carrier.

Abstract: An apparatus and method is disclosed for measuring ultrasound drilling mud velocity downhole in real time. One or more generated acoustical pulses are detected upon traversing two separate path lengths, and ultrasonic velocity is determined from differences in the pulses upon traversing their respective path lengths. Alternately, a single measurement can be made using an acoustic pulse traversing a specified path length. A transducer is discussed having a piezoelectric crystal, a backing material having matching impedance, and a facing material disposed between the crystal and the fluid having an impedance intermediate to crystal and fluid. A concave front face of the crystal increases sensitivity to off-axis signals. Improved signal resolution can be achieved using a controlled shape input pulse optimized for certain drilling conditions. A method of echo detection using wavelet analysis is preferred.

Abstract: A communication device is located within a well and includes a transducer that converts a first electrical signal into a first acoustic signal for transmission through the well and that converts second acoustic signal received from the well to a second electrical signal. The transducer is at least partially coated with an anechoic material in order to reduce the effects of acoustic signal impairments, such as echoes, flow and machine noise, and reverberations. The anechoic material has a thickness that is a fraction of a wavelength of the acoustic signals.

Abstract: In order to locate electromagnetic or acoustic signal sources of a sensor configuration (1a through 1c) fitted with at least two electric outputs; where the incidence-dependent transfer functions between the acoustic signals incident on the input(s) of the sensor configuration (1a through 1c) and the electric output signals are different, the ratio (7x through 7xx) of the output signal is formed and the result then is correlated with the previously determined ratio function (11).

Abstract: The device for adjusting a time indicator includes a gear train (1), the kinematic chain of which includes a sliding pinion (2) driven by a driving wheel set (3). The sliding pinion drives a driven wheel set (4) when the driving wheel set rotates in a first direction (A) and disconnects from said driven wheel set when said driving wheel set (3) rotates in a second direction (B), opposite to the first direction. The shaft (6) that the sliding pinion (2) includes is engaged in a groove (7) having first (9) and second (12) end portions, at least the first end portion (9) of which is directed radially (R) to the driven wheel set (4).

Abstract: A timekeeping apparatus having a hidden compartment. The compartment can contain permanent or removable psychological message and/or printed messages. The messages can be printed messages, digital messages, recordable audio messages and aromatic messages. The compartment can also contain such items has a mood sensing stone which changes color according to the wearer's mood, magnets or crystals.

Abstract: In one embodiment, the present invention provides an event recording system that has an event-capture module, an editing module, and a media recording module. The event-capture module captures an event signal, such as an audio signal from a sound event, and transforms the signal into a primary event file that is accessible as it is being formed. The editing module is communicatively connected to the event capture module. It accesses and parses the primary event file into one or more digital track files that can be recorded onto a recording media. Likewise, the media recording module is communicatively linked to the editing module for receiving the one or more digital track files from the editing module. The media recording module has a plurality of media recorders for simultaneously recording the one or more digital track files onto a plurality of recording media. This allows a plurality of recording media, with the entire event recorded upon each media, to be available shortly after the event has ended.