Patents Issued in June 24, 2004
  • Publication number: 20040119088
    Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: DENSO CORPORATION
    Inventors: Yutaka Fukuda, Naohiko Hirano, Chikage Noritake, Shoji Miura
  • Publication number: 20040119089
    Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. The annular flange preferably comprises a projection having a squared tab and circular distal end that is received by a receiving groove having a notch (to receive the squared tab) and a cavity (to receive the distal end).
    Type: Application
    Filed: October 7, 2003
    Publication date: June 24, 2004
    Applicant: International Rectifier Corporation
    Inventors: Mario Merlin, Aldo Torti
  • Publication number: 20040119090
    Abstract: A GaAs semiconductor device comprising a FET (field effect transistor), and a low dielectric constant passivation. The passivation protects the surface of the active area of the FET under the FET. The FET is a high electron mobility transistor or a pseudomorphic high electron mobility transistor. The passivation is formed by spin coating and made of a low dielectric constant compound. The low dielectric constant compound is Benzocyclobutene. Advantages are a simple manufacturing process, fewer surface defects, and improved device performance. Therefore, a superior device is provided at a reduced production cost.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventors: Hsien-Chin Chiu, Shih-Cheng Yang, Yi-Jen Chan, Tsung-Jung Yeh
  • Publication number: 20040119091
    Abstract: A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 24, 2004
    Applicant: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Jun Sakakibara, Yoshitaka Noda, Hitoshi Yamaguchi
  • Publication number: 20040119092
    Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.
    Type: Application
    Filed: August 13, 2003
    Publication date: June 24, 2004
    Applicant: HITACHI, LTD.
    Inventors: Hidekatsu Onose, Atsuo Watanabe
  • Publication number: 20040119093
    Abstract: A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for blocking or eliminating the slow photon-generated carriers in the region where the drift field is low.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: International Business Machines Corporation
    Inventors: Guy Moshe Cohen, Qiqing C. Ouyang, Jeremy Daniel Schaub
  • Publication number: 20040119094
    Abstract: In a circuit designed to output a varying output voltage, the substrate of the semi-conductor component is connected to a regulator, in particular a switch, connected to a lower potential than the potential of the substrate of the circuit. The circuit can for example he used in a Subscriber Line interface Circuit (SLIC).
    Type: Application
    Filed: November 21, 2003
    Publication date: June 24, 2004
    Inventors: Henrik Hellberg, Anders Emericks, Hakan Sjodin
  • Publication number: 20040119095
    Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 24, 2004
    Inventors: Mark E. Tuttle, James G. Deak
  • Publication number: 20040119096
    Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 24, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Ravi Iyer, Randhir P. S. Thakur, Howard E. Rhodes
  • Publication number: 20040119097
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 24, 2004
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Publication number: 20040119098
    Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: eASIC Corporation
    Inventors: Zvi Or-Bach, Laurance Cooke
  • Publication number: 20040119099
    Abstract: A semiconductor device for demodulating a received signal in a satisfactory manner when the frequency of the received signal deviates. The semiconductor device is used in a receiver having a reference oscillator. The semiconductor device includes a local oscillator, a PLL controller, and a comparator. The local oscillator generates a local signal having a local frequency. The PLL controller controls the local frequency in accordance with a reference signal of the reference oscillator. The comparator compares the frequency of the received signal with the frequency of the reference signal or the phase of the received signal with the phase of the reference signal to generate an error signal for correcting the local frequency in accordance with the comparison.
    Type: Application
    Filed: July 24, 2003
    Publication date: June 24, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Kazuhiro Tomita
  • Publication number: 20040119100
    Abstract: A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Applicant: International Business Machines Corporation
    Inventors: Edward J. Nowak, BethAnn Rainey
  • Publication number: 20040119101
    Abstract: A method for improving performance of a transistor oriented in <110> orientation is described. Contacts on either side of the gate are misaligned with respect to one another. The placement of the contacts changes the stress pattern so that the direction of a large part of the tensile strain is diverted from the direction of the current flow.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Gerhard Schrom, Mark A. Armstrong, Mohamed A. Arafa
  • Publication number: 20040119102
    Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Kevin K. Chan, Guy M. Cohen, Meikei Ieong, Ronnen A. Roy, Paul Solomon, Min Yang
  • Publication number: 20040119103
    Abstract: A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical N− channel region disposed between an N+ source region and an N− drift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the N+ region and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.
    Type: Application
    Filed: August 22, 2003
    Publication date: June 24, 2004
    Applicant: International Rectifier Corporation
    Inventor: Naresh Thapar
  • Publication number: 20040119104
    Abstract: The invention provides an image sensor that has an array of photosensors and an array of micro-lenses with each micro-lens confronting more than one of the photosensors and concentrating light striking each micro-lens onto less than all of the confronted photosensors so that selected photosensors receive a greater exposure than other photosensors.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Applicant: Eastman Kodak Company
    Inventors: Richard P. Szajewski, Lyn M. Irving
  • Publication number: 20040119105
    Abstract: A ferroelectric memory cell that is more compact and uses less power includes a word line connected to a gate of a transistor. A ferroelectric capacitor has a first plate connected to a drain of the transistor. A bit line is connected to a source of the transistor and runs perpendicular to the word line. A plate line forms a second plate of the ferroelectric capacitor. The plate line runs parallel to the bit line.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Inventor: Dennis Robert Wilson
  • Publication number: 20040119106
    Abstract: A split gate structure is disclosed for improved programming and erasing efficiency. A semiconductor region extending to the surface of a substrate has isolation regions surrounding parallel active regions. Source/drain regions in the semiconductor region are equally spaced along the active regions and are electrically connected by source/drain connecting regions, denoted source/drain towers, disposed over said source/drain regions and running perpendicular to the active regions. A multiplicity of structures denoted floating gate towers, parallel to the source/drain towers are situated between each pair of said source/drain towers. A floating gate tower having first insulating layers, disposed over the semiconductor region within the active regions crossed by the floating gate tower, separating floating gates, which exist only over active regions crossed by the floating gate tower, from the semiconductor region.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventor: Chia-Ta Hsieh
  • Publication number: 20040119107
    Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 24, 2004
    Inventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
  • Publication number: 20040119108
    Abstract: A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventor: Kent Kuohua Chang
  • Publication number: 20040119109
    Abstract: A non-volatile memory device and a fabrication method thereof, wherein a charge trapping layer, which is a memory unit, is formed at opposite ends of a gate of a cell, i.e., adjacent to source and drain junction regions, such that portions of the charge trapping layer adjacent to the source and drain junction regions are formed to be thicker than other portions of the charge trapping layer. Therefore, regions adjacent to junction regions function as electron storage regions and hole filing regions.
    Type: Application
    Filed: July 24, 2003
    Publication date: June 24, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Sung-Taeg Kang
  • Publication number: 20040119110
    Abstract: A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.
    Type: Application
    Filed: September 23, 2003
    Publication date: June 24, 2004
    Applicant: Samsung Electronics Co., Inc.
    Inventor: Sung-Chul Park
  • Publication number: 20040119111
    Abstract: A non-volatile semiconductor memory device comprising at least: a first electrode containing silicon atoms; and a second electrode formed on the first electrode through an insulating film, wherein the insulating film is formed of at least two layers of: a lower silicon nitride film on the first electrode side obtained by nitriding the first electrode; and an upper silicon nitride film formed on the lower silicon nitride film according to a chemical vapor deposition method, and at least a part of the lower silicon nitride film contains a rare gas element at an area density of 1010 cm−2 or more.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicants: Tadahiro OMI, SHARP KABUSHIKI KAISHA
    Inventors: Tadahiro Omi, Naoki Ueda
  • Publication number: 20040119112
    Abstract: A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. Auxillary low voltage transistors which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then the other side.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventor: Bohumil Lojek
  • Publication number: 20040119113
    Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Thomas K. Simacek, Thomas W. Kotowski, Jack L. Glenn, Alireza F. Borzabadi
  • Publication number: 20040119114
    Abstract: An n-channel field effect transistor (FET) with a switchable negative differential resistance (SNDR) characteristic is disclosed. The n-channel SNDR FET is configured as a depletion mode device, and biased so that it operates essentially as a p-channel device. Because the device is n-channel, speed is improved, and processing complexity is reduced when designing and manufacturing large scale circuits. The device achieves a performance comparable to CMOS, and thus is suitable as a replacement for a p-channel pull-up devices in logic gates (including in inverters) and memory cells.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventor: Tsu-Jae King
  • Publication number: 20040119115
    Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Kevin K. Chan, Hussein I. Hanafi, Paul M. Solomon
  • Publication number: 20040119116
    Abstract: A pull-up transistor array for a high voltage output circuit is provided. The transistor array includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate and N double diffused MOS transistors (DMOS transistors) laterally arranged on the epitaxial layer. One of source/drains of the DMOS transistors is formed at each of transistors, and the N DMOS transistors share another source/drain. Accordingly, the pull-up transistor array may output a signal of a high voltage and high current, and may high-integrate a device because a device isolation region is not required between the DMOS transistors.
    Type: Application
    Filed: July 23, 2003
    Publication date: June 24, 2004
    Inventors: Jae-Il Byeon, Il-Hun Shon
  • Publication number: 20040119117
    Abstract: An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P+ source region 100 and N+ source region 104 are in contact with a source electrode.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: Toyoda Jidosha Kabushiki Kaisha
    Inventor: Tomoyoshi Kushida
  • Publication number: 20040119118
    Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.
    Type: Application
    Filed: April 24, 2003
    Publication date: June 24, 2004
    Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Publication number: 20040119119
    Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.
    Type: Application
    Filed: November 7, 2003
    Publication date: June 24, 2004
    Applicant: Industrial Technology Research Institute, a corporation of Taiwan
    Inventors: Chyh-Yih Chang, Ming-Dou Ker
  • Publication number: 20040119120
    Abstract: In a conventional N-channel MOSFET for an open-drain circuit, when a positive static electric charge is applied to its drain, there is no route by way of which to discharge the static electric charge, resulting in a rather low static withstand voltage. To overcome this, according to the invention, an open-drain N-channel MOSFET has a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers. When a positive static electric charge is applied to the drain, a parasitic transistor appears that forms a route by way of which the static electric charge is discharged.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 24, 2004
    Applicant: Rohm Co., LTD.
    Inventors: Hidetoshi Nishikawa, Masahiko Sonoda
  • Publication number: 20040119121
    Abstract: A semiconductor device including a resistive conductive layer and a method of manufacturing the semiconductor device.
    Type: Application
    Filed: September 26, 2003
    Publication date: June 24, 2004
    Inventor: Hironobu Kariyazono
  • Publication number: 20040119122
    Abstract: An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker, Luca Fasoli
  • Publication number: 20040119123
    Abstract: The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled trench. As compared to a conventional MOSFET, the gas insulated gate device provides reduced capacitance between the gate and the source/drain region, improved device reliability and durability, and improved isolation from interference caused by nearby electric fields. The present invention includes the steps of forming a doped source region and drain region on a substrate, forming a gate, forming a gaseous gate insulating trench and forming terminals upon the gate, the source region and the drain region. A plurality of the devices on a single substrate may be combined to form an integrated circuit.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventor: Mark E. Murray
  • Publication number: 20040119124
    Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm−2 or more in at least a part of the silicon oxynitride film.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicants: Tadahiro OMI, SHARP KABUSHIKI KAISHA
    Inventors: Tadahiro Omi, Naoki Ueda
  • Publication number: 20040119125
    Abstract: A method for creating a MEMS structure is provided. In accordance with the method, an article is provided which comprises a substrate (101) and a single crystal semiconductor layer (105), and having a sacrificial layer (103) comprising a first dielectric material which is disposed between the substrate and the semiconductor layer. An opening (107) is created which extends through the semiconductor layer (105) and the sacrificial layer (103) and which exposes a portion of the substrate (101). An anchor portion (109) comprising a second dielectric material is then formed in the opening (107). Next, the semiconductor layer (105) is epitaxially grown to a suitable device thickness, thereby forming a device layer (111).
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Motorola Inc.
    Inventors: Bishnu Gogoi, Raymond M. Roop
  • Publication number: 20040119126
    Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Li-Shu Chen, Howard N. Fudem, Donald E. Crockett, Philip C. Smith
  • Publication number: 20040119127
    Abstract: To provide an active electronic device which is formed from a carbon nanotube and which excels in high frequency operation and an electronic apparatus using the active electronic device. Provided are the active electronic device including: a carbon nanotube (1); a first electrode (S) connected to one end of the carbon nanotube; a second electrode (D) connected to the other end of the carbon nanotube; and a third electrode (G) facing the carbon nanotube (1) to irradiate the carbon nanotube (1) with electromagnetic waves, in which the amount of current flowing into the carbon nanotube (1) is changed by electromagnetic waves, at least high frequency electromagnetic waves, radiated from the third electrode onto the carbon nanotube (1), and the electronic apparatus using the active electronic device.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 24, 2004
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Kazunori Anazawa, Chikara Manabe, Hiroyuki Watanabe, Hirotsugu Kashimura, Masaaki Shimizu
  • Publication number: 20040119128
    Abstract: A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Joseph F. Shepard
  • Publication number: 20040119129
    Abstract: A unipolar photodiode and methods of making and using employ a Schottky contact as a cathode contact. The Schottky cathode contact is created directly on a carrier traveling or collector layer of the unipolar photodiode resulting in a simpler overall structure to use and make. The unipolar photodiode comprises a light absorption layer, the collector layer adjacent to the light absorption layer, the Schottky cathode contact in direct contact with the collector layer, and an anode contact either directly or indirectly interfaced to the light absorption layer. The light absorption layer has a doping concentration that is greater than a doping concentration of the collector layer. The light absorption layer has a band gap energy that is less than that of the collector layer. The light absorption layer and the collector layer may be of the same or opposite conduction type.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Inventor: Kirk S. Giboney
  • Publication number: 20040119130
    Abstract: A PIN diode includes a first p-area, an n-area, and in between an intermediate area on a first surface of a substrate, wherein a doping concentration of the intermediate area is lower than a doping concentration of the p-area and lower than a doping concentration of the n-area. Further, the PIN diode includes a first electrically conductive member, which is arranged on a side of the p-area, which faces away from the intermediate area, and a second electrically conductive member, which is arranged on a side of the n-area, which faces away from the intermediate area. The PIN diode is preferably separated from the substrate by an insulating layer, covered by a further insulating layer on the surface, which faces away from the substrate, and laterally surrounded by a trench filled with an insulating material, such that it is essentially fully insulated and encapsulated.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 24, 2004
    Inventors: Raimund Peichl, Philipp Seng
  • Publication number: 20040119131
    Abstract: The invention described herein relates to physical vapor deposition targets comprising both Ti and Zr. The targets can comprise a uniform texture across the target surface and throughout the thickness; and can further have an increased mechanical strength compared to high purity titanium and tantalum. The sputtering targets can be utilized to sputter deposit a thin film; and such film can be utilized as a copper barrier layer.
    Type: Application
    Filed: November 12, 2002
    Publication date: June 24, 2004
    Inventor: Stephen P. Turner
  • Publication number: 20040119132
    Abstract: A dielectric separation type semiconductor device of high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first semiconductor layer (2) of first conductivity type disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a second semiconductor layer (4) of first conductivity type on the first semiconductor layer (2), a third semiconductor layer (5) of second conductivity type surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.
    Type: Application
    Filed: July 7, 2003
    Publication date: June 24, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hajime Akiyama, Naoki Yasuda
  • Publication number: 20040119133
    Abstract: A semiconductor device which enables an improvement of a current driving capability of a MOS transistor sufficiently is attained.
    Type: Application
    Filed: April 4, 2003
    Publication date: June 24, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20040119134
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Publication number: 20040119135
    Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.
    Type: Application
    Filed: May 23, 2003
    Publication date: June 24, 2004
    Inventors: Ralf van Bentum, Stephan Kruegel, Gert Burbach
  • Publication number: 20040119136
    Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Qiqing Ouyang
  • Publication number: 20040119137
    Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 24, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Roberto Modica