Patents Issued in June 24, 2004
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Publication number: 20040119138Abstract: A method of forming a metal fuse in a semiconductor device. In one embodiment, a specific additional mask is applied to form the metal fuse to reduce the thickness of the fuse. The method also includes forming a fuse window opening that is very shallow in the semiconductor device. The shallower opening allows for better control and removal of the remaining passivation left over the fuse during a fuse burning laser process. The thinner fuse and the thinner remaining passivation reduce the amount of laser energy required to vaporize the oxide and to cut the fuse. The location of the fuse also greatly enlarges the laser energy window that can be utilized to make laser repairs. The larger energy window results in a higher laser repair success ratio even if some deviation in the fabrication process occurs.Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsiang Yang, Chun-Ming Su
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Publication number: 20040119139Abstract: A semiconductor device includes first to third functional areas parted each other by a boundary region on a semiconductor substrate. A memory block is formed in the first functional area and includes memory cells and a redundancy memory cell substituted for one memory cell. A functional circuit block is formed in the second functional area and connected with the memory block via an interconnection line. A program interconnection block is formed in the third functional area so that it does not overlap with the interconnection line and includes a program interconnection section which forms a program forming a signal path so that a defective memory cell is substituted by the redundancy memory cell. A data transfer section extends over from the program interconnection block to the memory block and transfers program information relevant to the program of the program interconnection section to the memory block.Type: ApplicationFiled: March 19, 2003Publication date: June 24, 2004Inventors: Takehiko Hojo, Kaoru Tokushige
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Publication number: 20040119140Abstract: An input matching parallel inductor 114 which utilizes a spiral inductor, and an input matching parallel capacitor 115 which utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion 125, form an input matching parallel capacitor 115 inside an input matching circuit via-hole 121 being formed by applying a method of surface via-hole to the front surface of a GaAs substrate 124. A choke inductor 119 which utilizes a spiral inductor, and a bypass capacitor 120 which utilizes an MIM capacitor, both being constituting elements of a drain voltage feeding circuit 107, form a bypass capacitor 120 inside a drain voltage feeding circuit via-hole 123 formed by applying a method of surface via-hole to the front surface of the GaAs substrate 124. A drain voltage terminal 136 is extended by a drawing wire 135 from between the spiral inductor and the drain voltage feeding circuit via-hole 123.Type: ApplicationFiled: December 9, 2003Publication date: June 24, 2004Inventor: Masaaki Nishijima
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Publication number: 20040119141Abstract: The present invention relates to a biochip for capacitive stimulation and/or detection of biological tissue. The biochip includes a support structure, at least one stimulation and/or sensor device, which is arranged in or on the support structure, and at least one dielectric layer, one layer surface of which is arranged on the stimulation and/or sensor device and the opposite layer surface forms a stimulation and/or sensor surface for the capacitive stimulation and/or detection of biological tissue. The dielectric layer includes (Tix, Zr1-x)O2, with 0.99≧x≧0.5, or a TiO2 and ZrO2 layer arrangement.Type: ApplicationFiled: November 3, 2003Publication date: June 24, 2004Applicant: Infineon Technologies AGInventors: Dipl.-Ing Matthias Schreiter, Reinhard Gabl, Martin Jenkner, Dipl.-Ing. Bjorn Eversmann, Franz Hofmann
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Publication number: 20040119142Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).Type: ApplicationFiled: September 26, 2003Publication date: June 24, 2004Inventors: Alessandro Grossi, Roberto Bez, Giorgio Servalli
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Publication number: 20040119143Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventor: Maurice S. Karpman
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Publication number: 20040119144Abstract: An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Intel CorporationInventors: David Gregory Figueroa, Dong Zhong, Yuan-Liang Li, Jiangqi He, Cengiz Ahmet Palanduz
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Publication number: 20040119145Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.Type: ApplicationFiled: September 13, 2001Publication date: June 24, 2004Applicant: TECH SEMICONDUCOR SINGAPORE PTE. LTD.Inventors: Jian Sun, Hing Ho Au, Yew Hoong Phang
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Publication number: 20040119146Abstract: A semiconductor device including: an inner lead having a sloping section sloping upward and outward; a die pad; a semiconductor chip having an electrode and bonded to the die pad; a wire electrically connecting the inner lead to the electrode; a sealing section sealing the inner lead, the semiconductor chip, and the wire; and an outer lead extending outward from the sealing section.Type: ApplicationFiled: September 17, 2003Publication date: June 24, 2004Applicant: SEIKO EPSON CORPORATIONInventor: Hiroshi Masuya
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Publication number: 20040119147Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Intel CorporationInventors: Weston Roth, Damion T. Searls, James D. Jackson
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Publication number: 20040119148Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.Type: ApplicationFiled: October 1, 2003Publication date: June 24, 2004Inventor: Martin Standing
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Publication number: 20040119149Abstract: A system for packaging an integrated circuit amplifier bonds the integrated circuit to metallization lines in a substrate surface with solder balls, the contacts of the integrated circuit being on a top surface and the opposite surface of the integrated circuit being adjacent to a set of vias for conducting heat away from the circuit into the ambient; the material for the material disposed about the integrated circuit being deposited in powder form and later solidified.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Applicant: Nokia CorporationInventors: Hawk Yin Pang, Kenichi Hashizume
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Publication number: 20040119150Abstract: A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Lih-Tyng Hwang, James E. Drye, Shun Meen Kuo
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Publication number: 20040119151Abstract: A device having pre-applied underfill is disclosed. The device comprises an integrated circuit package with a thermally reversible adhesive underfill pad attached to the package. A method for applying the underfill involves applying the underfill to scribe lines on packaged integrated circuit devices on a manufacturing die. The manufacturing die is then sawn to produce individual integrated circuit packages with pads of pre-applied underfill.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Applicant: Intel CorporationInventor: Richard Bernard Foehringer
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Publication number: 20040119152Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.Type: ApplicationFiled: October 8, 2003Publication date: June 24, 2004Applicant: ChipPAC, Inc.Inventors: Marcos Karnezos, Flynn Carson
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Publication number: 20040119153Abstract: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a ball grid array package. Also, a method for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.Type: ApplicationFiled: October 8, 2003Publication date: June 24, 2004Applicant: ChipPAC, Inc.Inventor: Marcos Karnezos
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Publication number: 20040119154Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventor: Michael Briere
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Publication number: 20040119155Abstract: A metal wiring board includes a metal plate as a substrate. The metal plate is stamped in a predetermined wiring pattern including wiring portions and terminal portions. The metal plate has soldering areas prepared for electrical connection and non-soldering areas coated with solder resist on its surface.Type: ApplicationFiled: December 9, 2003Publication date: June 24, 2004Inventors: Takeyoshi Hisada, Hirofumi Mokuya
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Publication number: 20040119156Abstract: An electronic circuit assembly having a fiducial on a lower layer substrate. The fiducial is viewed through a through hole that is aligned with the fiducial and extends through an upper layer substrate that is adjacent the lower layer substrate. The fiducial and the through hole provide a high contrast between the fiducial and the surrounding substrate permitting viewing and recognition of substrate orientation by a computer vision system.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Stephen J. Wagner, Barbara B. Myrvaagnes
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Publication number: 20040119157Abstract: A densely packed electronic assemblage has a substrate medium for supporting at least one heat generating component and means for reducing the temperature of the at least one heat generating component. A heat sink cooperates with the at least one heat removing element for reducing heat of the heat generating component by absorbing heat from the at least one heat generating component.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Eastman Kodak CompanyInventor: Tina P. Barcley
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Publication number: 20040119158Abstract: A circuit assembly having an insulating base, heat-conducting plate and circuit containing die is disclosed. The die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base. The insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate. The die includes an integrated circuit therein and is mounted such that the heat-conducting plate is disposed between the die and the insulating plate. The insulating base preferably includes signal conducting channels for providing electrical connections to the die, the heat-conducting plate having an opening therein for making the connections between the die and the conducting channels. The assembly may also include a heat-spreading cover in thermal contact with the heat-conducting base plate, the heat-spreading cover overlying the die. The heat-conducting channels are preferably filled with solder, and include a solder protrusion extending from the heat-conducting channels.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Koay Hean Tatt, Tan Gin Ghee
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Publication number: 20040119159Abstract: The semiconductor device includes an input/output circuit, a functional module, an electrostatic discharge protection circuit and bumps. The input/output circuit is formed close to an edge of the semiconductor chip. The functional module is formed on the semiconductor chip located on a central side with regard to the input/output circuit. The electrostatic discharge protection circuit is formed in the functional module of the semiconductor chip and serves to protect a circuit located in a downstream thereof, from being destructed by electrostatic discharge. The bumps are arranged on one of major surfaces of the semiconductor chip located close to the functional module, and they are connected to the functional module via the electrostatic discharge protection circuit.Type: ApplicationFiled: October 23, 2003Publication date: June 24, 2004Inventor: Makoto Takahashi
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Publication number: 20040119160Abstract: A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components, wherein this segregation of components allows for hermetically sealing the active components with a cover while leaving accessible the passive components, and wherein the passive components are secured using a reflow soldering technique and are removable and replaceable so as to make the multi-chip module substantially programmable with regard to the passive components.Type: ApplicationFiled: October 30, 2003Publication date: June 24, 2004Inventors: David Kautz, Howard Morgenstern, Roy J. Blazek
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Publication number: 20040119161Abstract: The present invention provides an economical package for housing semiconductor chip that allows a semiconductor chip to operate normally and stably over long periods by efficiently transferring heat generated during the operation of the semiconductor chip to the package mount substrate.Type: ApplicationFiled: December 2, 2003Publication date: June 24, 2004Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., A.L.M.T. CORP.Inventors: Hirohisa Saito, Takashi Tsuno, Chihiro Kawai, Shinya Nishida, Motoyoshi Tanaka
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Publication number: 20040119162Abstract: To provide a semiconductor device that is capable of reduction in thickness and high-density mounting, and that is simple in manufacturing process and convenient for use. A wiring substrate is formed with a plurality of opening portions. In each of the opening portions, a lower chip formed by a wafer-level chip size package (WCSP) is received, and an upper chip is placed on the lower chip. The composite including them is sealed by a sealing body such as epoxy resin. Internal connection terminals of each lower chip are electrically connected to pads of the corresponding upper chip via wirings, through holes and bonding posts of the wiring substrate, and wires.Type: ApplicationFiled: November 28, 2003Publication date: June 24, 2004Inventor: Yoshimi Egawa
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Publication number: 20040119163Abstract: A method for making a semiconductor device using carbon nitride as an etch stop diffusion barrier and/or a hard mask is described. An interconnect structure is made by at least: forming an etch stop diffusion layer, depositing an interlayer dielectric, etching necessary vias and trenches, forming a barrier layer, forming copper alloy, and planarizing. The use of a hard mask in the method is optional. The etch stop diffusion layer, the optional hard mask, or both comprised by carbon nitride.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Lawrence Wong, Jihperng Leu, Grant Kloster, Andrew W. Ott, Patrick Morrow
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Publication number: 20040119164Abstract: There is disclosed a semiconductor device comprising a substrate, a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value, a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value, a wire which is provided in a recess for the wire, which is formed passing through the second insulating film and extending into the first insulating film, and a dummy wire provided in a recess for the dummy wire, which is formed passing through the second insulating film and extending into the first insulating film, and is located in a predetermined area spaced from an area where the wire is provided.Type: ApplicationFiled: August 14, 2003Publication date: June 24, 2004Inventors: Nobuyuki Kurashima, Gaku Minamihaba, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano
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Publication number: 20040119165Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.Type: ApplicationFiled: October 14, 2003Publication date: June 24, 2004Inventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Paul Ou Yang
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Publication number: 20040119166Abstract: There are included the steps of preparing a wiring substrate having a wiring pattern on a surface, bonding a connection terminal of electronic chip, which has a predetermined element and the connection terminal on one surface, to the wiring pattern of the wiring substrate by a flip-chip bonding, forming an insulating film on the wiring substrate to have a film thickness that covers the electronic chip, or a film thickness that exposes at least another surface of the electronic chip, and reducing a thickness of the electronic chip by grinding another surface of the electronic chip and the insulating film.Type: ApplicationFiled: November 3, 2003Publication date: June 24, 2004Inventor: Masahiro Sunohara
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Publication number: 20040119167Abstract: A semiconductor device of the present invention has an active region whose width varies. Gate electrodes cross over narrowest portions of the active region. Therefore, the device is not prone to producing leakage current even when the line width of the gate electrodes is small.Type: ApplicationFiled: December 8, 2003Publication date: June 24, 2004Inventor: Jong-Wook Suk
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Publication number: 20040119168Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Inventors: Susan H. Downey, Sheila F. Chopin, Peter R. Harper, Sohrab Safai, Tu-Anh Tran, Alan H. Woosley
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Publication number: 20040119169Abstract: This invention provides a method for forming a three dimensional integrated circuit stacked structure (5), as well as a stacked structure formed in accordance with the method. The method includes placing a first integrated (1) circuit atop a second integrated circuit (2), and electrically connecting the first and the second integrated circuits at connection points (20). At least some of the connection points correspond to electrically conductive through-hole structures (12) made through a silicon substrate (14) of the first integrated circuit. The first one of the integrated circuits contains circuitry operating at frequencies equal to or greater than about 1 GHz, and the silicon substrate has a resistivity of at least about 100 ohms-cm. The result is that the electrical performance is not degraded, as the RF signal insertion loss at the through-hole interconnections is significantly reduced.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Nokia CorporationInventor: Takeshi Hanawa
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Publication number: 20040119170Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer.Type: ApplicationFiled: July 22, 2003Publication date: June 24, 2004Inventors: Myeong-Cheol Kim, Chang-Jin Kang, Kyeong-Koo Chi, Seung-Young Son
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Publication number: 20040119171Abstract: A flip-chip substrate for bonding with a chip is provided. The chip has an active surface with a plurality of bonding pads and each bonding pad has a bump thereon. The flip-chip substrate has a plurality of contact pads that correspond in positions with the bonding pads on the chip such that the chip pads are aligned to their corresponding contact pads at the melting point of the bump material.Type: ApplicationFiled: September 16, 2003Publication date: June 24, 2004Inventors: Yu-Wen Chen, Ming-Lun Ho, Chun-Yang Lee
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Publication number: 20040119172Abstract: A packaged IC including insulated wire for electrically connecting conductive structures of the packaged IC. In some embodiments, the packaged IC includes an IC die attached to a package substrate, where bond pads of the IC die are electrically connected to bond fingers of the substrate with insulated wire. The insulated wire has a conductive core and an insulator coating. In some examples, the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core such as, e.g., silicon nitride or silicon oxide. In one example, the insulator coating is applied to a conductive core by a chemical vapor deposition (CVD) process such as a plasma enhanced chemical vapor deposition (PECVD).Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Inventors: Susan H. Downey, Peter R. Harper
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Publication number: 20040119173Abstract: A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.Type: ApplicationFiled: December 9, 2003Publication date: June 24, 2004Inventors: Todd O. Bolken, Cary J. Baerlocher, David J. Corisis, Chad A. Cobbley
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Publication number: 20040119174Abstract: A method for manufacturing ophthalmic lenses using reusable thermoplastic molds is provided. The invention permits the production of a full prescriptive range of lenses while reducing the number of mold inserts required. Further, the method of the invention may be used in a method for the delivery of customized ophthalmic lenses to a lens wearer.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Gregory J. Hofmann, Thomas R. Rooney, Victor Lust, Ture Kindt-Larsen, Christian Elbek, Christopher Wildsmith
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Publication number: 20040119175Abstract: Apparatus and method incorporating a trephine for cutting an IOL optic from an IOL blank in a rotational cutting movement.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Bryan M. Reed, James O'Callaghan, William J. Appleton, Larry C. Hovey, Tadeusz Urbanowicz, Lamese Snow, Philippe Subrin, Bradley J. Adams
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Publication number: 20040119176Abstract: A method of manufacturing an ophthalmic lens, involves contacting the lens with an aqueous solution comprising a surfactant to remove debris from the lens, prior to inspecting and packaging the lens. The aqueous solution may further comprise a buffering agent and/or sodium chloride. Preferred surfactants include polyoxyethylene-polyoxypropylene block copolymer, nonionic surfactants, such as a poloxamer or a poloxamine. The methods may also be employed for additional biomedical devices, such as ophthalmic implants.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Bausch & Lomb IncorporatedInventors: Erning Xia, Erik M. Indra, William J. Appleton, Sanjay Rastogi, Kevin Hall, Mahendra P. Nandu, Dominic V. Ruscio
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Publication number: 20040119177Abstract: Apparatus and method for cutting an IOL optic from an IOL blank whereby the resultant IOL optic has a square edge and the cutting is performed in a combined linear and rotational cutting movement. In another aspect, an IOL optic is provided which includes a square edge and helically shaped striations formed therein to help reduce glare.Type: ApplicationFiled: June 26, 2003Publication date: June 24, 2004Inventors: Bryan M. Reed, James O'Callaghan, William J. Appleton, Larry C. Hovey, Tadeusz Urbanowicz, Lamese Snow, Philippe Subrin, Bradley J. Adams
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Publication number: 20040119178Abstract: A method of producing a polarizing plate, including the step of laminating a pair of curled protective sheets onto opposite surf aces of a polarizer respectively so that respective curling directions of the pair of curled protective sheets are reverse to each other, wherein the laminating index of the pair of protective sheets is selected to be not higher than 60 in order to restrain the polarizing plate from being curled.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: NITTO DENKO CORPORATIONInventor: Makoto Kuwamura
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Publication number: 20040119179Abstract: The invention concerns a method for making very fine particles containing at least an active principle inserted in a host molecule and a device for implementing said method. The method is characterized in that it consists in forming a solution of the active principle in a first liquid solvent and of a product formed by the host molecules in a second liquid solvent, then in contacting the resulting solutions with a supercritical pressure fluid, so as to precipitate the host molecules which are dissolved therein.Type: ApplicationFiled: February 17, 2004Publication date: June 24, 2004Inventors: Michel Perrut, Jennifer Jung, Fabrice Leboeuf, Isabelle Fabing
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Publication number: 20040119180Abstract: The invention relates to a method of producing a dental prosthesis, comprising the steps:Type: ApplicationFiled: February 3, 2004Publication date: June 24, 2004Inventors: Sybille Frank, Holger Hauptmann, Stefan Moscheler, Robert Schnagl, Daniel Suttor
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Publication number: 20040119181Abstract: The invention concerns a method for controlling coalescence of particles forming a structure subjected to a treatment designed to establish crosslinking between said particles. The method consists in recording at least a physical quantity, whereof the evolution is continuously measurable and whereto the particle crosslinking is correlated, and in stopping the treatment when said physical quantity reaches a value corresponding the desired coalescence. The invention is characterized in that it consists in measuring as said physical quantity the shrinking of said structure. The invention also concerns a method and a device for making a structure of mutually crosslinked particles using said control method and a method for obtaining a product with interconnected pores, in particular for bone substitution, using such a structure.Type: ApplicationFiled: September 30, 2003Publication date: June 24, 2004Inventors: Michel Descamps, Pierre Hardouin, Jianxi Lu, Francine Monchau
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Publication number: 20040119182Abstract: A method and apparatus for proportioning flow and controlling pressure to a gate of an injection mold. The invention decouples the control surface from the gate closure to reduce the required actuation force. Methods for estimating the pressure and flow rate entering the injection mold are included.Type: ApplicationFiled: November 4, 2003Publication date: June 24, 2004Inventor: David O. Kazmer
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Publication number: 20040119183Abstract: A velocity-pressure switching and pressure holding device and system for electrically-operated injection molding machines. The switching between closed-loop position control and closed-loop pressure control of a servo motor of an injection molding machine is quickly and smoothly achieved by a switchable loop switch to ensure the optimal control of the velocity-pressure switching during injection filling and pressure holding. Furthermore an adjustable observation value and a speed reducing set up for the injection axle before switching are provided to allow users to perform minor adjustments on the velocity-pressure switching during the slow down of the injection axle. The present invention easily and precisely achieves the optimal velocity-pressure switching parameters to facilitate better pressure holding ability to increase the quality of the plastic products.Type: ApplicationFiled: April 25, 2003Publication date: June 24, 2004Inventors: Hsing Chang Liu, Yu-Wei Chien
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Publication number: 20040119184Abstract: A method for forming a headliner assembly includes forming a main body blank having a periphery in a shape corresponding to a desired shape of the headliner assembly. A mold has a lower mold part with a correspondingly shaped surface with a recess. The method includes pouring foam into the recess in an open mold, then closing the mold to join the foam to the main body. The recess or the main body can carry an accessory, and the foam may surround the accessory. Preferably, a pouring robot serves a plurality of mold parts so that curing time and mold assembly time do not prolong the production of foam enhanced headliners.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: LEAR CORPORATIONInventors: Bari William Brown, George Bernard Byma
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Publication number: 20040119185Abstract: A method for manufacturing opened-cell plastic foams includes a plurality of steps including a step of mixing ethylene vinyl acetate copolymer (EVA) or polyethylene resins (PE), a preset percentage of a blowing agent and a vulcanizing agent, pigment, aids agent, and hollow porcelain balls or hollow micro grains evenly, a step of placing the mixed material in a mold to proceed batch-foaming once or twice. And a step of opening the mold for instant foaming process can let a solid shell of the mixed material with porous chamber structure produce ruptured holes so that the finished product of plastic foams may have good airiness and soft flexibility.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventor: Ching Hsi Chen
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Publication number: 20040119186Abstract: A method for recycling and reusing corrugated paper comprising the steps of: pulverizing the waste corrugated paper into a plurality of scraps; adding viscose to mix with the scraps; agitating viscose and the scraps so that a surface of each scrap is stuck with a thin layer of viscose; filling the scraps with viscose into a model; compressing the scraps for solidifying the scraps so as to form a shaped product; and drying the shaped product. The size of the corrugated paper is less than 10 cm. The viscose is water-solvable viscose. The compressing pressure is larger than 15 tons. In agitating step, recycling short fiber for waste paper can be added.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventor: Shih-Hui Lee
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Publication number: 20040119187Abstract: A composition of matter suitable for spinning polyaniline fiber, a method for spinning electrically conductive polyaniline fiber, a method for exchanging dopants in polyaniline fibers, and methods for dedoping and redoping polyaniline fibers are described.Type: ApplicationFiled: September 26, 2003Publication date: June 24, 2004Inventors: Benjamin R. Mattes, Phillip N. Adams, Dali Yang, Lori A. Brown, Andrei G. Fadeev, Ian D. Norris