Patents Issued in July 6, 2004
  • Patent number: 6759653
    Abstract: A scanning type microscope that captures substance information of the surface of a specimen by the tip end of a nanotube probe needle fastened to a cantilever, in which an organic gas is decomposed by a focused ion beam in a focused ion beam apparatus, and the nanotube is bonded to the cantilever with a deposit of the decomposed component thus produced. With this probe, the quality of the nanotube probe needle can be improved by removing an unnecessary deposit adhering to the nanotube tip end portion using a ion beam, by cutting an unnecessary part of the nanotube in order to control length of the probe needle and by injecting ions into the tip end portion of the nanotube.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: July 6, 2004
    Assignees: Yoshikazu Nakayama, Daiken Chemical Co., Ltd., Seiko Instruments Inc.
    Inventors: Yoshikazu Nakayama, Seiji Akita, Akio Harada, Takashi Okawa, Yuichi Takano, Masatoshi Yasutake, Yoshiharu Shirakawabe
  • Patent number: 6759654
    Abstract: One embodiment disclosed relates to a method for inspecting or reviewing a magnetized specimen using an automated inspection apparatus. The method includes generating a beam of incident electrons using an electron source, biasing the specimen with respect to the electron source such that the incident electrons decelerate as a surface of the specimen is approached, and illuminating a portion of the specimen at a tilt with the beam of incident electrons. The specimen is moved under the incident beam of electrons using a movable stage of the inspection apparatus. Scattered electrons are detected to form image data of the specimen showing distinct contrast between regions of different magnetization. The movement of the specimen under the beam of incident electrons may be continuous, and data for multiple image pixels may be acquired in parallel using a time delay integrating detector.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: July 6, 2004
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Marian Mankos, David A. Soltz, Harald F. Hess
  • Patent number: 6759655
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa
  • Patent number: 6759656
    Abstract: An electron microscope equipped with an electron biprism is provided with second and third objective lenses placed between a sample and the electron biprism such that the sample is not affected by the magnetic fields produced by the objective lenses. The magnification of a TEM image of the sample at the focal point H is controllably varied by appropriately controlling the excitations of the objective lenses. The spacing of carrier fringes is adjusted by controllably varying the voltage applied to a line electrode of the biprism.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 6, 2004
    Assignee: Jeol Ltd.
    Inventor: Takeshi Tomita
  • Patent number: 6759657
    Abstract: A low noise, high sensitivity and wide dynamic range uncooled type infrared sensor can effectively reduce the influence of fluctuations of the gate of the amplifier transistor.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: July 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Iida, Keitaro Shigenaka
  • Patent number: 6759658
    Abstract: The invention relates to an X-ray detector which includes at least one conversion unit (1) for converting absorbed X-ray quanta into electric charge signals, at least one evaluation unit (10) for amplifying and further processing the charge signals, and at least one data processing unit (11) for the acquisition, further processing and output of data. The charge signals are first amplified by an input amplifier (2) in the evaluation unit (10) after which they are evaluated in parallel in a counting channel (5) as well as in an integrator channel (7). The charge signals are then counted in the counting channel and the overall charge is integrated in the integrator channel as a measure of the energy delivered in the conversion unit (1). Because of the parallel presentation of the counting results and the integration results, more weight can be attached thereto in their respective range of the quantum flow that is optimum from a measuring point of view, so that the dynamic range of the X-ray detector is enlarged.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: July 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Michael Overdick, Walter Ruetten, Thomas Zaengel
  • Patent number: 6759659
    Abstract: A thermal imaging system for detecting cracks and defects in a structure. An ultrasonic transducer is coupled to the structure through a malleable coupler. Ultrasonic energy from the transducer causes the defects to heat up, which is detected by a thermal camera. A control unit is employed to provide timing and control for the operation of the ultrasonic transducer and the camera.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: July 6, 2004
    Assignee: Wayne State University
    Inventors: Robert L. Thomas, Lawrence D. Favro, Xiaoyan Han, Zhong Ouyang, Hua Sui, Gang Sun
  • Patent number: 6759660
    Abstract: A composite active-matrix substrate includes: a plurality of active-matrix substrates which are disposed adjacent to one another; a base substrate which is disposed to oppose a bottom surface of the active-matrix substrates; a sealant which is disposed in the form of a frame between the active-matrix substrate and the base substrate; a first filler which fills a spacing surrounded by the active-matrix substrate, the base substrate, and the sealant; and a second filler which fills a gap between edges of the active-matrix substrates. The sealant prevents the first filler from seeping out. In this way, seeping of an adhesive filler can be prevented in the arrangement where a plurality of active-matrix substrates are fixed on the base substrate using the adhesive filler. An electromagnetic wave capturing device according to the present invention uses such a composite active-matrix substrate.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: July 6, 2004
    Assignees: Shimadzu Corporation, Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Osamu Teranuma
  • Patent number: 6759661
    Abstract: An apparatus emits radiation on curable adhesives to bond things together under different ambient conditions. An insulating housing has a cylindrical section and a disc-shaped section defining an interior. A plurality of batteries and an LED array are separated in the interior by an insulating spacer to prevent shorting of batteries. A switch relay in the interior connects power from the batteries to the LED array when a switching mechanism on the outside of the housing is displaced. This displacement closes the switch relay and connects power to the LED array that emits high-intensity radiation. A cover connected to the cylindrical-shaped section seals the interior from ambient and transmits the high-intensity radiation to cure an adhesive. A modular envelope of transparent disc, adhesive, and removable foil can be releasable connected to the housing to secure mounting structure to a surface.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: July 6, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ray Baggett, Billy Courson, Pete Sagasti
  • Patent number: 6759662
    Abstract: An optical detection system comprising an electromagnetic radiation source, a source radiation focusing and collimating means, a photodetector, an emitted radiation focusing means and a source radiation blocking panel. The radiation source is used to direct source radiation onto a sample which is disposed in a sample platform. The source radiation focusing and collimating means is disposed between the radiation source and the sample for focusing and collimating the source radiation onto the sample. The photodetector is adapted for receiving radiation emitted from the sample which has been focused by the emitted radiation focusing means. The source radiation blocking panel, disposed between the source radiation focusing and collimating means and the sample, is unique in that it is capable of reducing light scattering and interference, such that a clear signal from each individual sample can be obtained by the photodetector.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: July 6, 2004
    Assignee: CE Resources Pte. Ltd.
    Inventor: Sam Fong Yau Li
  • Patent number: 6759663
    Abstract: The present invention provides devices and methods for detection of particles, such as biological cells, in samples using a photosensitive waveguide. The photosensitive waveguide changes its transmissivity in a detectable manner in response to controlling radiation emitted from the particles. In preferred embodiments, the waveguide is two-dimensional and the position of the particles as well as their presence is obtained by scanning the waveguide in two non-parallel directions. The provided devices are preferably used to locate labeled cells. The present invention also includes control systems and methods for detecting and locating cells using the devices provided.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 6, 2004
    Assignee: Ikonisys, Inc.
    Inventors: Petros Tsipouras, Triantafyllos Tafas
  • Patent number: 6759664
    Abstract: The present invention is an apparatus for curing an article that is passing through the apparatus, wherein the article is being cured by ultraviolet radiation curing. The present invention most commonly applies to the field of fiber optics, and the manufacture of optical fibers and fiber optic cables or ribbons. The present invention comprises a hollow tubular UV light emitting device (bulb) and a UV transparent tube where the bulb is disposed around the tube creating a space between the tube and the bulb. The article to be cured passes through the center of the tube along with an inert gas, where the inert gas is either cooled or heated depending on the application of the apparatus. A UV transparent cooling medium is passed through the space between the tube and the bulb to provide cooling for the apparatus, preventing heat damage from the bulb.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: July 6, 2004
    Assignee: Alcatel
    Inventors: Justin Thompson, Olivier Schuepbach
  • Patent number: 6759665
    Abstract: An apparatus and method for providing a low energy, high current ion beam for ion implantation applications are disclosed. The apparatus includes a mass analysis magnet mounted in a passageway along the path of an ion beam, and a magnetic device adapted to provide a multi-cusped magnetic field in the passageway, which may include a plurality of magnets mounted along at least a portion of the passageway. The magnets may cooperatively interact to provide a multi-cusped magnetic field along at least a portion of the passageway. The multi-cusped magnetic field may be superimposed on the dipole field at a specified field strength in a region of the mass analyzer passageway for a given low energy ion beam. The invention thus provides enhancement of beam plasma within a mass analyzer dipole magnetic field for low energy ion beams without the introduction of externally generated plasma.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 6, 2004
    Assignee: Axcelis Technologies, Inc.
    Inventors: Victor M. Benveniste, William F. DiVergilio, John Z. Ye
  • Patent number: 6759666
    Abstract: A plurality of circuit patterns are written by a small number of charged particle beams with a high dimension controllability without using a mask. A desired charge quantity is irradiated on a desired point on a sample by performing irradiation on a charged particle beam section in a superposing manner in order to obtain a predetermined exposure intensity by the charged particle beams constituting a plurality of charged particle beam groups. In addition, the charged particle beams are used, in which current quantities of a plurality of the charged particle beams are made to have a weighted gradation, the desired charged quantity is irradiated, and thus a desired exposure dimension is obtained.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: July 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Koji Nagata, Haruo Yoda, Hidetoshi Satoh, Hiroyuki Takahashi
  • Patent number: 6759667
    Abstract: An object of the present invention is to provide a photocoupling device which can supply sufficient light to a light receiving element by increasing brightness on the input section side at a low input current, and provide a method of manufacturing, with which such a photocoupling device can be assembled without adding an extra process. A photocoupling device of the invention includes an input section having two light emitting elements and lead terminals for supplying a drive current to the light emitting elements, and an output section having a light receiving element opposed to light emitting faces of the light emitting elements and lead terminals for supplying a drive current to the light receiving element, wherein the two light emitting elements are connected in series.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: July 6, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiki Yasuda
  • Patent number: 6759668
    Abstract: The present invention is directed to a photoconductive switch module. The photoconductive switch module comprises a first substrate having light-emitting elements, a second substrate having photoconductive switch elements, whose number is equal to that of the light-emitting elements. The light-emitting elements face the photoconductive switch elements so that the photoconductive switch elements are turned on/off in accordance with lighting/distinction of the light-emitting elements. The photoconductive switch module further comprises a third substrate arranged between the first substrate and the second substrate. The third substrate has through holes, whose number is equal to that of the light-emitting elements. Drive light emitted from a light-emitting element is trapped within a through hole to travel to a photoconductive switch element. The first substrate and the third substrate are connected to each other by heating and pressure contacting of first metal members.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 6, 2004
    Assignee: Olympus Corporation
    Inventors: Daisuke Matsuo, Tomoyuki Hatakeyama
  • Patent number: 6759669
    Abstract: A measurement device includes a laser or other light source for producing a light beam, and optics that split the light beam into a plurality of differentiable beam portions, such as a plurality of polarized beams. The optics also direct the differentiable beam portions toward a target to be measured. The measurement device also includes a detection component, such as a plurality of position sensitive detectors, positioned to intercept images created by simultaneous incidence of the differentiable beam portions on the target. The data collected by the detection component is used to calculate measurement data related to the target. When used with a head suspension target, displacement of various regions of the head suspension may be measured relative to a reference region, such as the mounting region of the head suspension.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: July 6, 2004
    Assignee: Hutchinson Technology Incorporated
    Inventors: Roger W. Schmitz, Senthil Balasubramaniam, Roger S. Posusta
  • Patent number: 6759670
    Abstract: A method is used for dynamic manipulation and/or for adjustment of a module or a component in an optical system, in particular in a microlithographic projection exposure objective for manufacture of semiconductors. The module or component is displaced by at least two actuators, which have detectors for determining at least their relative path displacements. A position of the module or component is determined by at least two sensors, the sensors and the actuators, with their detectors communicating with one another in the manner of a control loop. At least one impulse is exerted on the module or component by the actuators. The timing of the impulse can be deliberately varied, to which end the displacement of the actuators is carried out with a time-variant velocity profile dictated as a function of a determined position snactual of the module or component. A position snactual of the module or component is re-determined after the velocity profile, has been executed.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: July 6, 2004
    Inventor: Karl-Eugen Aubele
  • Patent number: 6759671
    Abstract: Measurements on a sheet (12), for example measurement of the movement of the sheet in a printer, can be performed by directing a measuring beam (8) towards the sheet and utilizing the effects of self-mixing in a diode laser (2) and Doppler shift in the measuring beam caused by the movement. The measuring method and a dedicated, cheap and compact, sheet sensor (1) may be used for determining different parameters and in different sheet processing apparatus.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: July 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Martin Dieter Liess, Gillian Antoinette Mimnagh-Kelleher
  • Patent number: 6759672
    Abstract: A system for and method of reading out a storage phosphor screen (or a storage phosphor sheet or an imaging plate) sensitive to radiation is used to perform radiography by optically stimulating the storage phosphor screen to induce luminescence and acquire a digital image of a subject. A semiconductor light source array is used as a stimulating light source to which an optical fiber array consisting of a bundle of optical fibers having diverse forms is connected; a starting of the semiconductor light source array is controlled with an electric pulse; and a semiconductor light source array starting pulse for generating a stimulating light is interlocked with a photomultiplier tube for collecting a luminescence light signal induced from the storage phosphor screen by the stimulating light to represent the collected luminescence light as a distribution of a two-dimensional position and thereby acquire the digital image of the subject from the storage phosphor screen.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: July 6, 2004
    Assignee: Korea Advanced Institute of Science & Technology
    Inventors: Sang-Yoon Lee, Kun Jai Lee
  • Patent number: 6759673
    Abstract: A radiation image readout apparatus scans an excitation light in a main scanning direction and a sub scanning direction over a stimulable phosphor sheet, on which radiation energy has been stored, and detects the stimulated emission emitted thereupon; wherein, various types of phosphor sheets can be read out at a high resolution and high sensitivity. The excitation light energy level for obtaining an adequate sensitivity for each type of phosphor sheet is obtained. A controller controls the intensity of the excitation light emitted from the light source and the speed of the scanning mechanism, that is, the readout speed, whereby the excitation light projected onto a phosphor sheet of which the diffusion rate has been controlled by the inclusion therein of an navy blue colorant is of a greater energy level than the excitation light projected onto the white stimulable phosphor sheet not containing the navy blue colorant.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: July 6, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Taizo Akimoto, Masashi Hakamata
  • Patent number: 6759674
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of a first material at a first depth, where the first material impedes the diffusion of a base dopant. The first material also causes a change in band gap at the first depth in the base. According to this exemplary embodiment, the base further includes a concentration of a second material, where the concentration of second material increases at the first depth so as to counteract the change in band gap.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: July 6, 2004
    Assignee: Newport Fab, LLC
    Inventors: Greg D. U'Ren, Klaus F. Schuegraf, Marco Racanelli
  • Patent number: 6759675
    Abstract: An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: July 6, 2004
    Assignee: Motorola, Inc.
    Inventors: Sebastian Csutak, Wei E. Wu
  • Patent number: 6759676
    Abstract: In a multiply-complexed one-dimensional structure having a hierarchical structure in which a linear structure as an element of a one-dimensional structure having a finite curvature is made of a thinner one-dimensional structure having a finite curvature, at least two layers of one-dimensional unit structures are bonded in at least one site. For example, in a multiply-twisted helix having a hierarchical structure in which a linear structure as an element of a spiral structure is made of a thinner spiral structure, at least two layers of the unit spiral structures are bonded in at least one site. Alternatively, in a multiply-looped ring structure having a hierarchical structure in which a linear structure as an element of a ring structure is made of a thinner ring structure, at least two layers of ring unit structures are bonded in at least one site.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: July 6, 2004
    Assignee: Sony Corporation
    Inventors: Ryuichi Ugajin, Shintaro Hirata, Masakazu Ukita
  • Patent number: 6759677
    Abstract: Disclosed is a semiconductor device having a driver circuit operable at high speed and a method for manufacturing same. An active matrix liquid crystal display device uses a polysilicon film for its TFT active layer constituting a pixel matrix circuit because of low off current characteristics. On the other hand, a TFT active layer constituting driver circuits and a signal processing circuit uses a poly silicon germanium film because of high speed operation characteristics.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Fukunaga
  • Patent number: 6759678
    Abstract: A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hideomi Suzawa, Koji Ono, Tatsuya Arao
  • Patent number: 6759679
    Abstract: A poly-silicon layer of a thin film transistor (TFT) having an active channel region, wherein a probability P that a maximum number of a primary grain boundary exists on the active channel region is not 0.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 6, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Ki-Yong Lee
  • Patent number: 6759680
    Abstract: A semiconductor device with a substrate having an insulating surface, a first signal line extending over the substrate, a first thin film transistor having a channel region with crystalline silicon formed over the substrate and a gate of the first thin film transistor is connected to the first signal line, a second signal line extending across the first signal line, a second thin film transistor having a channel region comprising crystalline silicon formed over the substrate and a signal applied to a gate of the second thin film transistor from the second signal line through at least the first thin film transistor, a voltage supply line formed over the substrate, a pixel electrode formed over the substrate and the pixel electrode is supplied with a voltage from the voltage supply line through at least the second thin film transistor, and a driving circuit formed over the substrate for driving at least one of the first and second thin film transistors, the driving circuit having a third thin film transistor wh
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 6759681
    Abstract: An object of the present invention is to provide an EL display device having a high operation performance and reliability. The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing electric current. Morever, the LDD region 33 of the current control TFT 202 is formed so as to overlap a portion of the gate electrode 35 to make a structure which imposes importance on prevention of hot carrier injection and reduction of OFF current value.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kunitaka Yamamoto, Toshimitsu Konuma
  • Patent number: 6759682
    Abstract: An electro-luminescence panel that is adaptive for maximizing a capacitance of a storage capacitor. A plurality of electro-luminescence cells are arranged at crossings between gate lines and data lines in the panel. An electro-luminescence cell driving circuit drives the electro-luminescence cells. In the driving circuit, a power supply supplies power to the electro-luminescence cells. A first thin film transistor is connected between the power supply and the electro-luminescence cell. A second thin film transistor is connected between the data line and a gate electrode of the first thin film transistor to serve a switch of the electro-luminescence cell. A storage capacitor is connected between the gate electrode of the first thin film transistor and a pre-stage gate line. Accordingly, a capacitance value of the storage capacitor is maximized with the aid of the pre-stage gate line upon formation of the storage capacitor, thereby preventing flicker caused by a kickback phenomenon.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 6, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Sung Joon Bae
  • Patent number: 6759683
    Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-SiC is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: July 6, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Melanie W. Cole, Pooran C. Joshi
  • Patent number: 6759684
    Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: July 6, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
  • Patent number: 6759685
    Abstract: The present invention discloses a high-brightness light emitting diode (LED), which primarily includes a LED epitaxial layer with a reflective layer and a Si substrate with an adhesive layer. The LED epitaxial layer is bonded with the Si substrate by attaching the reflective layer and the adhesive layer. An n-type ohmic contact electrode and a p-type ohmic contact electrode are deposed on the front side of the LED. In the present invention, the reflective layer, the adhesive layer and the ohmic contact electrodes preferably perform single function, so that the most appropriate materials can be applied. Therefore, the LED of the present invention can exhibit excellent brightness.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 6, 2004
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Tung-Hsing Wu, Shao-Hua Huang, Chih-Ru Chung, Juin-Jer Yang
  • Patent number: 6759686
    Abstract: A light emitting diode (LED), and a method for producing the same. The LED includes a substrate that may be made of silicon, a first conductive layer on one side, and a porous insulating layer on the opposite side. The insulating layer defines microcavities therein, the microcavities having sharp tips on their inner surfaces. The microcavities have gas inside. A second conductive layer is disposed over the insulating layer. When an electrical potential is applied between the conductive layers, the gas-filled microcavities act as plasma discharge lamps, emitting light. The light may be in the ultraviolet portion of the spectrum. The method includes etching a substrate to produce a porous insulating layer on one side, depositing a first conductive layer on the opposite side, and depositing a second conductive layer over the insulating layer. The microcavities in the insulating layer are then filled with gas.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: July 6, 2004
    Inventors: Kok Wai Cheah, Wai Kwok Wong, Hoi Lam Tam
  • Patent number: 6759687
    Abstract: A scheme (systems and methods) for passively aligning one or more optical devices with a corresponding number of optical lenses in an accurate and efficient manner is described. By this approach, the invention avoids the often labor-intensive and costly steps required by conventional active alignment techniques that attempt to align the optical devices to the optical fibers. In one aspect, an optoelectronic device includes an optical device system, an optical lens system and a plurality of solder bumps disposed therebetween. The optical device system includes an optical device substrate supporting one or more optical devices and a solderable metallization pattern having a spatial arrangement with respect to the one or more optical devices. The optical lens system includes one or more optical lenses and a device bonding surface supporting a solderable metallization pattern having a spatial arrangement with respect to the one or more optical lenses.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 6, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: David B. Miller, Hing-Wah Chan, Tanya J. Snyder
  • Patent number: 6759688
    Abstract: A monolithic surface mount optoelectronic device includes a transparent epoxy layer and a glass layer, which cover the active surface of a light emitting diode junction. The diode junction preferably outputs a characteristic wavelength of about 450 nm (blue light). The junction is fabricated by growing a P+ layer, gallium nitride layer, and a silicon gallium nitride buffer layer on a silicon substrate. The buffer layer, which is preferably non-conductive, is made conductive by the addition of a metallic shorting ring connecting the gallium nitride layer through a via in the silicon substrate to one of two surface mount contacts. A conductive beam connects the P+ layer to the remaining surface mount contact through another via in the silicon substrate. An isolation trench separates the vias in the substrate.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: July 6, 2004
    Assignee: Microsemi Microwave Products, Inc.
    Inventors: Robert J. Preston, James Hayner
  • Patent number: 6759689
    Abstract: A metal layer 3, a light emitting layer section 4 and a first electrode 5 are formed in the order on a first main surface 7 side of a conductive substrate 2 and a current is supplied to the light emitting layer section 4 through the first electrode 5 and the conductive substrate 2. By using reflection on the metal layer 3, not only can good external quantum efficiency be realized, but electrodes or terminals can also be formed on both sides of the light emitting element. Thus, provided is a light emitting element excellent in external quantum efficiency thereof and in addition, not only simple in structure of a terminal lead thereof but excellent in convenience.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: July 6, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Keizo Adomi, Masanobu Takahashi, Nobuhiko Noto
  • Patent number: 6759690
    Abstract: A II-VI semiconductor device includes a stack of II-VI semiconductor layers electrically connected to a top electrical contact. A GaAs substrate is provided which supports the stack of II-VI semiconductor layers and is positioned opposite to the top electrical contacts. A BeTe buffer layer is provided between the GaAs substrate and the stack of II-VI semiconductor layers. The BeTe buffer layer reduces stacking fault defects at the interface between the GaAs substrate and the stack of II-VI semiconductor layers.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: July 6, 2004
    Assignee: 3M Innovative Properties Company
    Inventor: Thomas J. Miller
  • Patent number: 6759691
    Abstract: An ESD protection circuit having a high triggering threshold. The ESD protection circuit comprises a semiconductor-controlled rectifier (SCR) and a bipolar-junction-transistor (BJT). The SCR comprises an anode, an anode gate, a cathode gate and a cathode. The anode is coupled to a first pad. The cathode gate and the cathode are coupled to a second pad. The BJT transistor is parasitic under a metal-on-semiconductor (MOS) transistor and has a collector and an emitter. Either the collector or the emitter is coupled to the anode gate, and the other is coupled only to the second pad. Current generated at the anode is shared by the BJT transistor. A larger current is required to trigger the SCR in the ESD protection circuit of the present invention and result in a latch-up. Thus, latch-up caused by accidental noise is prevented during normal power operations.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: July 6, 2004
    Assignee: Winbond Electronics Corp.
    Inventor: Wei-Fan Chen
  • Patent number: 6759692
    Abstract: A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: July 6, 2004
    Assignee: IXYS Corporation
    Inventor: Sam Seiichiro Ochi
  • Patent number: 6759693
    Abstract: A permeable base transistor (PBT) having a base layer including metallic nanotubes embedded in a semiconductor crystal material is disclosed. The nanotube base layer separates emitter and collector layers of the semiconductor material.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 6, 2004
    Assignee: Nantero, Inc.
    Inventors: Bernhard Vögeli, Thomas Rueckes, Brent M. Segal
  • Patent number: 6759694
    Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: July 6, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Hsu, Jin-Wei Shi, Zing-Way Pei, Fon Yuan, Chee-Wee Liu
  • Patent number: 6759695
    Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: July 6, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Yanjun Ma, Douglas James Tweet, David Russell Evans
  • Patent number: 6759696
    Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material. The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs. The invention also relates to a semiconductor device comprising such a bipolar transistor.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: July 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Hendrik Gezienus Albert Huizing, Jan Willem Slotboom, Doede Terpstra, Johan Hendrik Klootwijk, Eyup Aksen
  • Patent number: 6759697
    Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: July 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
  • Patent number: 6759698
    Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: July 6, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Genichi Tanaka
  • Patent number: 6759699
    Abstract: A new digital follower device is achieved. The digital follower device comprises an n-channel vertical FET device and a p-channel vertical FET device. Each vertical FET device comprises a bulk region in a semiconductor substrate. The bulk region comprises a first doping type. A STI region is in the bulk region. A drain region is on a first side of the STI region. The drain region overlies the bulk region. The drain region comprises the first doping type. A gate region is on a second side of the STI region. The gate region comprises the first doping type. A voltage on the gate region controls a vertical channel in the bulk region. A buried region is between the gate region and the bulk region. The buried region comprises a second doping type. The n-channel FET device drain and the p-channel FET device drain are connected together. The n-channel FET device, gate and the p-channel FET device gate are connected together.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: July 6, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Min-Hwa Chi
  • Patent number: 6759700
    Abstract: A high-sensitive optical sensor is provided. In the optical sensor in which MOS transistors and a semiconductor light-receiving element are integrated, the light-receiving element includes a PN junction, and charges generated by the irradiation with light are accumulated at the PN junction, the PN junction of the light-receiving element is isolated from well regions of the MOS transistors.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: July 6, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Toshihiko Omi
  • Patent number: 6759701
    Abstract: MOS transistors A and B form a transistor circuit (an inverter in this case). A MOS transistor D is one for interrupting leakage current that has a channel length longer than those of the MOS transistors A and B. Under the action of an enable terminal (Enable), the MOS transistor D conducts only while the circuit is operated, and does not conduct and thereby interrupts leakage current while the circuit is in a standby state. A MOS transistor C does not produce effect while the circuit is operated, and makes the potential of an output terminal (Output) a high potential or a low potential (not intermediate potential) only while the circuit is in the standby state. Therefore, the circuit controls unnecessary through-transistor current of a standby type circuit in a succeeding stage, which current is conventionally caused at an intermediate potential during standby.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: July 6, 2004
    Assignee: Sony Corporation
    Inventor: Kazutoshi Shimizume
  • Patent number: 6759702
    Abstract: A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Carl J. Radens, Ramachandra Divakaruni, Jack A. Mandelman