Abstract: A robotic domain reflectometry test system (and corresponding method) comprising: domain reflectometry instrumentation; a robotic arm; and a passive, high frequency probe assembly comprising a signal probe and a ground probe having a fixed, non-adjustable pitch, the probe assembly being electrically connected to the domain reflectometry instrumentation, and being moved, electrically connected to, and retracted from test points on an electrical component to be tested by the robotic arm.

Abstract: A test apparatus comprises an input for receiving a test signal from a test signal source, wherein a signal line with a predefined characteristic wave impedance can be connected to the input. The test apparatus further comprises branching means with a first and a plurality of second terminals, the first terminal being connected to the input. The test apparatus further comprises a plurality of distribution lines, wherein each distribution line is connected to one of the plurality of second terminals of branching means, wherein one of the devices under test can be connected to each distribution line at the output side, each distribution line having a characteristic wave impedance, which is substantially equal to the product of the predefined characteristic wave impedance of the signal line and the number of distribution lines. Thus, a signal matching is given at the branching point, so that no amplitude or signal rise time distortions of the excitation signals occur at the inputs of the devices under test.

Abstract: In a device for the monitoring and the prognosis of the failure probability of inductive proximity sensors (1) for the monitoring of the position of movable switch rails or rail components, in which the proximity sensor (1) has at least one coil (5) that is supplied by an oscillator (7), and the sensor current flowing by means of variable attenuation is measured and then fed to an evaluation circuit, characteristic lines (18, 22) of the sensor (1) are stored for the course of the sensor currents in dependency of the distance of the movable switch rails or rail components, i.e. the mechanical attenuation in an electric not additionally attenuated condition, and in an electric additionally attenuated condition. The measurement currents (22) corresponding to a mechanical attenuation condition (18), as well as to respective additionally electric attenuated condition are cyclic scanned.

Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.

Abstract: An integrated circuit die test probe has a non-flat tip. In one embodiment, the tip has an elongated pyramid shape that provides a cutting action while probing solder covered conductive pads. The tip shape helps maintain a uniform tip to pad resistance during testing by penetrating the solder layer and avoiding solder residue build up. The test probes significantly reduce the need for cleaning the probe tips to remove residue.

Abstract: A resilient and rugged probe, used to measure an on-wafer signal. The probe has a metal probe tip, a resilient soft multi-layered dielectric substrate, a planar transmission structure and a fixed end. The probe tip is connected to the planar transmission structure. The planar transmission structure is attached to and supported by the resilient soft multi-layered dielectric substrate and then connected to the fixed end.

Abstract: A fixture is used to secure a substrate and to allow movement of a pin relative ot the fixture. The substrate fixture includes a holding table adapted to receive the substrate and a probe pin assembly underneath the table. The substrate is mounted on a table which can move in one-dimension, while the probe pin is moveable relative to the table in another dimension perpendicular to movement of the table. Moving the substrate retaining table and the pin retainer allows for alignment of the probe pin with a backside terminal of a trace conductor of the substrate. The assembly also has vertical height translational mechanism for contacting the probe pin with the backside terminal. Furthermore, the frontside terminal of the trace conductor is accessible to an external probe. A testing device can be connected to the external probe and the probe pin to measure the electrical continuity of the trace conductor.

Abstract: A probe card includes a flexible membrane, a plurality of probes attached to the flexible membrane, and a layer of foam connected to the flexible membrane so that when the probes are moved into the flexible membrane, the layer of foam is also deflected to produce a counteracting force at the probes. A plurality of push rods are used to transfer the force at the contacts to the foam layer. The foam layer is attached to a rigid plate or push plate. A guide plate includes openings through which the push rods pass. The guide plate supports the push rods along their length and reduces the spacing between the push rods at the flexible member when compared to the spacing of the push rods at the foam layer.

Abstract: A method is disclosed of monitoring an environmental condition associated with a container with a set of electronic components including attaching a moisture recorder to the container, the moisture recorder comprising a sensing element responsive to atmospheric moisture content, a memory storage device, and a processor electrically coupled to the sensing element and the memory storage device, the processor being configured to periodically receive information from the sensing element indicative of atmospheric moisture content and to store data in the memory storage device based on the received information.

Abstract: The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Abstract: A system and method for testing an integrated circuit (IC) by transient signal analysis includes a comparison circuit that is configured to generate a comparison signal from an IC transient signal and a reference signal. Circuitry operationally coupled to the comparison circuit manipulates the comparison signal to generate a first output waveform area indicative of an absolute area of positive and negative portions within the comparison signal. The comparison circuit and the circuitry may include seven operational-amplifiers (op-amps) or ten op-amps. As a further processing sequence, a second output waveform area that is indicative of an absolute area of positive and negative portions within a second comparison signal is generated. In one embodiment, a first value representing the first waveform area and a second value representing the second waveform area are plotted to determine if the plotted X-Y coordinate falls within a predefined standard for determining the pass/fail status of the IC.

Abstract: In one embodiment, a test interface for testing integrated circuits includes an array of dice. A removable electrical connection (e.g., an interposer) may be coupled between the array of dice and a wafer containing multiple dice to be tested. The removable electrical connection allows electrical signals to be transmitted between the array of dice and the wafer. The test interface may be used in conjunction with a tester.

Abstract: Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

Abstract: A probe frame assembly of an inspection apparatus for a liquid crystal display is capable of inspecting more than six LCD panels patterned on a glass substrate. In the assembly, at least two probe frame bodies are provided above the upper surface of a chuck such that they can accommodate a range of numbers of liquid crystal display panels, and simultaneously apply test pattern signals to shorting bars provided on one or more liquid crystal display panels.

Abstract: A circuit and method that maintains the impedance matching characteristics of a common output driver while compensating for the high-frequency signal attenuation inherent in printed circuit board traces and other integrated circuit signal transmission media are disclosed. The circuit includes a pre-emphasis driver configured in parallel with a standard output driver. The pre-emphasis driver is a tri-statable device which mirrors a received logic input when in an “on” state and provides a high output impedance with no signal content when in an “off” state. The pre-emphasis driver is controlled by a pre-emphasis control signal configured such that the pre-emphasis driver can inject high-frequency signal components into a transmission line for a portion of a clock cycle.

Abstract: A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

Abstract: The present invention provides an improved input/output (I/O) circuit that comprises a pair of buffers, a voltage reference circuit that provides first and second reference voltages to the buffers respectively, and a detection circuit. The detection circuit detects whether a supply voltage is below a switching voltage, which is a pre-selected value between operating ranges of two pre-defined supply voltages, e.g., 3.3V and 5V, respectively. If the supply voltage is below the switching voltage, the detection circuit controls the voltage reference circuit to set the first and second reference voltages to first and second predetermined values, e.g., a ground level and the supply voltage, respectively. In this way, the large signal swings of the signals output by the buffers can be substantially maintained. Therefore, high speed operations can be achieved.

Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.

Abstract: Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.

Abstract: The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.

Abstract: A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.

Abstract: Voltage comparator circuit capable of precisely comparing voltages to ground and power supply potentials, without level converter or plurality of power supplies. First and second MOS transistors, with gates commonly connected and drains are connected to a first power supply potential with the same gate width and length. Third MOS transistor with opposite conductive type than first and second, with drain connected to second power supply potential connected to source of first. A fourth MOS transistor with opposite conductive type to the first and second, with a drain connected to the second power supply potential, with same gate width and length as the third. The drain and gate of the first are connected, and a comparative reference potential applies to the gate of the third. Input signal is given to gate of the fourth, and output signal is derived from the drain of the second.

Abstract: A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

Abstract: An integrated circuit driver includes an output stage having source drain paths of PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET.

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A variable delay circuit includes a first delay circuit having a plurality of first delay stages connected in cascade. The first delay circuit receives an input signal at the initial stage of the first delay stages. A second delay circuit has a plurality of second delay stages identical to the first delay stages. The second delay circuit is connected in cascade and receives a first timing signal at the initial stage of the second delay stages. A detecting circuit receives a second timing signal asynchronous to the first timing signal, and detects, of delayed timing signals outputted from each of the second delay stages, a delayed timing signal having a transition edge near a transition edge of the second timing signal. A selecting circuit selects a delayed signal outputted from the first delay stage corresponding to the second delay stage outputting the delayed timing signal detected by the detecting circuit.

Abstract: A clock analyzer includes an input port for receiving a reference clock signal from an external source, a plurality of functionally identical delay cells for delaying the reference clock signal and generating a plurality of delayed clock signals, each delayed clock signal being delayed by a unique number of delay cells, and at least one comparator for comparing the reference clock signal to the plurality of delayed clock signals and choosing a selected clock signal from the plurality of delayed clock signals that at least partially overlaps the reference clock signal.

Abstract: A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset signal; and a plurality of buffers respectively transmitting a reference clock signal and output clock signals of the plurality of frequency-dividing circuits to an internal circuit of the semiconductor integrated circuit device. Therefore, a plurality of clock signals having different frequencies with aligned edges can be generated without the need for separately providing an external pin for inputting the reset signal or a circuit for generating the reset signal.

Abstract: A mixer circuit includes a local frequency multiplication unit including a pair of transistors having bases receiving local oscillation waves inverted in phase. A reference transistor is differentially connected with the pair of transistors. The pair of transistors and the reference transistor have their emitters connected to a collector of a modulated wave input transistor having a base receiving a modulated wave signal and an emitter connected to a constant current source, and have their collectors connected to a load. The commonly connected collectors of the pair of transistors and the collector of the reference transistor output modulation signals inverted in phase. The sum of currents flowing through the pair of transistors and the reference transistor equals the constant current of the constant current source flowing through the modulated wave input transistor, and the mixer circuit has a gain.

Abstract: A high-voltage switching circuit comprising: a switch having ON and OFF states and having a parasitic gate capacitance and a control circuit for turning the switch on and off. The switch comprises a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively, and biased at a bias voltage level. The control circuit comprises: a programming transistor having its drain connected to the shared gate terminal of the switch, its source connected to receive a programming voltage, and its gate connected to receive a programming transistor gate voltage; first circuitry for causing a first transition from a first level to a second (lower) level of the programming voltage; and second circuitry for causing a second transition from a first level to a second level of the programming transistor gate voltage.

Abstract: A multiplexer circuit is disclosed for switching a selected one of a plurality of current inputs carried by respective input lines (2;101) to a common output. The circuit comprises, for each input line, a diode clamp (5;104) and isolation means (10;109) provided between each input line and the common terminal The diode clamp (5;104) is operable in a first mode in which voltages are applied to the clamp terminals such that the diodes (8,9;107,108) of the diode clamp are forward biased and hold the input line (2;101) at a first voltage which prevents the passage of current from the input line to the common output, and a second mode in which the voltages are applied to the clamp terminals such that the diodes of the diode clamp are reverse biased and the passage of the current from the input line to the common output is allowed. Only two connections, for the diode clamp, are needed to control the switching of the current input, and the switch introduces no current offset to the output.

Abstract: An integrated semiconductor module having at least one terminal for connection to a data bus and having at least one low-pass filter that is connected downstream of the terminal in order to limit the data rate during normal operation. A circuit arrangement is provided for bridging the low-pass filter in order to be able to test the module at a higher data rate.

Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.

Abstract: The present invention overcomes the disadvantages of the prior art and provides a new temperature compensation trimming technique. Temperature compensated output is provided in a logarithmic voltage output device by the steps of: measuring the resistance of a first resistor, a second resistor, and a third resistor at a first temperature; measuring again the resistances of the first resistor, second resistor, and third resistor at a second temperature; and trimming the drift of the third resistor according to a calculated temperature compensation trim.

Abstract: A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.

Abstract: A method and circuit for controlling fuse blow including sending signals to a plurality of fuse latches, sending fuse select signals to a blow control circuit to determine if a fuse should be blown or not, activating a delay timer after a fuse is blown to control after-blow time. After the delay timer has expired, issuing a Stop signal that causes the blow control circuit to shut off a blow device. This process continues until successful blow completion of all to-be-blown fuses.

Abstract: A data latch circuit includes anti-fuse elements for storing remedy information therein as to replacement of defective memory cells by redundant memory cells. For programming the anti-fuse elements to a logic level “1” in a programming mode, control signals CTL1 and CTL2 are set at a low level and a high level, respectively, and programming control signals PGMA and PGMB are set at a high level and a low level, respectively. A voltage selection node Nvs delivers a programming voltage Vpp, lowering an output terminal RCB to effect dielectric breakdown of anti-fuse element 25, which assumes a low resistance. In a normal operation mode, programming voltages PUMA and PGMB are set at a low level and a high level, respectively, and both control signals CTL1 and CTL2 are set at a low level Voltage output node Nvs delivers the normal operating voltage, raising output terminal RC to a high level to thereby deliver the stored logic level “1”.

Abstract: A semiconductor integrated circuit, including an internal circuit, a transition state voltage step-down circuit generating an internal power supply voltage supplied to the internal circuit from an external power supply voltage only for a fixed time period after the internal circuit is changed from a standby state to an active state, and a steady state voltage step-down circuit generating the internal power supply voltage from the external power supply voltage for the duration that the internal circuit is in either the standby state or the active state.

Abstract: A controllable apparatus for providing a compensated RF signal including an input port for coupling with an RF signal source, such as a multifrequency CATV signal, and an output port for coupling to an associated electronic device. The controllable apparatus generates new second and third order products from the multifrequency RF signal which are the same magnitude, but opposite in phase to the nonlinear products generated by the electronic device. Since both the original multifrequency RF input signal and the new generated products from the distortion control circuit are coupled to the electronic device, the nonlinear products from the distortion control circuit and the electronic device will be canceled and the output of the electronic device will comprise only the multifrequency RF signal. The controllable apparatus includes an RF circuit path and a controllable nonlinear compensator transversely connected to the RF circuit path. A control bias input allows selective control of the nonlinear compensator.

Abstract: Embodiments of a dual input differential amplifier are described. The dual input differential amplifier includes multiple input devices forming at least two sets of differential inputs for an operational amplifier, and multiple switches within the operational amplifier, each switch being coupled to a corresponding input device to switch an active input set of the at least two sets in order to enable a reduction in residual charge associated with switching at an output of the corresponding switch.

Abstract: A method for compensating for the pulse area error of a Class-D power amplifier is achieved; especially it compensates the variations in the supply voltage and similar dependencies. A Class-D Amplifier typically gets pulse coded digital input (PCM) and may comprise a Sigma Delta Modulator to generate the signals driving the power output stage, typically an H-Bridge. A fundamental idea of this invention is to measure the real area of the output pulses, where the area is defined as the pulse duration multiplied by the pulse voltage amplitude, and to compare it with the ideal nominal pulse area. The pulse area error is calculated and then subtracted from said amplifier's input data. Key element of this invention is the “Pulse Area Compensation Function”, which calculates said real pulse area (voltage amplitude multiplied by time), compares said real pulse area with said ideal pulse area and feeds the difference into the input of said Sigma Delta Modulator.

Abstract: A preamplifier includes a detector to detect an input optical power level and convert the detected input optical power level into an input current. The preamplifier also includes a transimpedance amplifier that provides a gain for the input current received from the detector. A dummy transimpedance amplifier is provided to supply a reference voltage. The dummy transimpedance amplifier has a structure similar to that of the transimpedance amplifier. A unity gain buffer is used to reduce the output impedance of the reference voltage and to output a bias voltage to both the transimpedance amplifier and the dummy transimpedance amplifier. This bias voltage can make the gate-controlled MOSFET working in its triode region, and the load resistance of the core amplifier can be easily controlled such that the gain and bandwidth of the core amplifier can be widely controlled. This results in the preamplifier having a high stability while its feedback resistor is controlled to achieve wide dynamic range.

Abstract: A dynamic sensor regulator that provides a mechanism for introducing desirable tonal artifacts in component-based guitar amplifier systems by inducing voltage fluctuations into the power supply of a preamplifier. The dynamic sensor regulator comprises a regulator circuit, connected to an amplifier that is connected to a converter circuit that is connected to a variable control circuit. The amplifier includes a floating bias circuit that dynamically adjusts the bias state of an output driving amplifier in response to signal fluctuations of the regulator output signal. A transformer is connected to the amplifier output and once the transformer's saturation point has been reached, the saturation of the transformer increases proportionally with the amplifier's input signal while the regulated output signal remains constant, emulating amplifier overload and saturation.

Abstract: An automatic gain control (AGC) circuit for an RF amplifier (or other type of signal-processing module) has a single, switched, RF detector that selectively detects the instantaneous power level of either the sampled RF input signal or the sampled (and optionally attenuated) RF output signal. A processor uses the detected input and output power levels to generate control signals for a variable (e.g., voltage-controlled) attenuator that attenuates the RF input signal prior to being applied to the input of the RF amplifier. The processor is designed (e.g., programmed) to control the variable attenuator to maintain a constant gain between the input and output terminals of the AGC circuit. In addition to this closed-loop mode of operation, the AGC circuit may also have a temperature sensor, where the processor controls the variable attenuator in an open-loop mode of operation based on the temperature of the RF amplifier.