Abstract: A capacitor has a coupled of electrodes with a dielectric placed therebetween. At least one of the electrodes is made of copper, and barriers for preventing the diffusion of copper into the dielectric are provided between the dielectric and the copper electrodes, respectively.

Abstract: A method for fabricating a semiconductor device, and a semiconductor device, having storage node contact plugs whereby by a first interlayer dielectric layer (ILD) film having a greater etch rate is formed on a surface of a structure, and then a second ILD film having a smaller etch rate is formed on the first ILD film. After storage node contact holes having narrow width are formed by dry etching the ILD films, the width is increased by wet etching the ILD films. Since the first ILD film has a greater etch rate and is etched faster than the second ILD film, the lower width of each of the storage node contact holes is increased relatively more than the upper width. Insulating layer spacers are then formed on the internal walls of the storage node contact holes, and storage node contact plugs are formed by burying a conductive material therein.

Abstract: The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.

Abstract: In a nonvolatile semiconductor memory device, an interpoly dielectric film composed of a nitrogen-introduced CVD SiO2 film is used as the gate oxide films of MOS transistors an a low voltage region of a peripheral circuit region. Gate oxide films of MOS transistors in high voltage region of the peripheral circuit region are composed of a laminate of the SiO2 film and a nitrogen-introduced CVD SiO2 film. This arrangement improves transistor characteristics and reliability of gate oxide films of the peripheral circuit MOS transistors. It is also possible to realize miniaturization and low voltage operation Further, simplification of the production process is made possible.

Abstract: Methods and devices are disclosed which provide for memory devices having reduced memory cell square feature sizes. Such square feature sizes can permit large memory devices, on the order of a gigabyte or large, to be fabricated on one chip or die. The methods and devices disclosed, along with variations of them, utilize three dimensions as opposed to other memory devices which are fabricated in only two dimensions. Thus, the methods and devices disclosed, along with variations, contains substantially horizontal and vertical components.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate 1, a plurality of memory cells 1a on the semiconductor substrate including transistors having floating gate electrodes and control gate electrodes. Source lines 30 are formed in a self-alignment manner with respect to a control gate electrodes. The surface of the semiconductor substrate 1 has such a periodical unevenness along the source lines 30 which has a diffusion layer 30a that an impurity is distributed along the surface of the semiconductor substrate 1 and a buried diffusion layer 30b that an impurity is distributed at a position deeper than said diffusion layer 30a. The buried diffusion layer 30b connects a plurality of portions of the diffusion layers 30a under the bottom surface 5b of the recess portion 5 to each other.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material.

Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract: A III nitride buffer film including at least Al element and having a screw-type dislocation density of 1×108/cm2 or less is formed on a base made from a sapphire single crystal, etc., to fabricate an epitaxial base substrate. Then, a III nitride underfilm is formed on the III nitride buffer film, to fabricate an epitaxial substrate.

Abstract: An input/output protection device of lateral, bipolar type quickly responds to an excess voltage pulse and/or an excess current pulse of, for example, electrostatic discharge. In a region of a first conduction type (a fourth diffusion layer) of a semiconductor substrate, a first diffusion layer of a second conduction type opposite to the first conduction type is fabricated, the layer being connected to an input/output terminal. A second diffusion layer of the second conduction type is fabricated to be connected to electrode wiring at a fixed potential. A third diffusion layer of the second conduction type is manufactured at a bottom of the second diffusion layer and is connected to the second diffusion layer. The first diffusion layer is circularly enclosed with the third diffusion layer.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A semiconductor package is provided that includes an electrical connection and support means having a front face and a recess in the front face. The semiconductor package also includes a semiconductor component having a front face including a sensor and a rear face which presses on the bottom of the recess of the electrical connection and support means. Further included in the semiconductor package is a positioning and locking means for locking the semiconductor component onto the electrical connection and support means. The positioning and locking means is engaged in a space which separates the periphery of the semiconductor component from the periphery of the recess and keeps the semiconductor component pressed against the bottom of the recess. Thus, there is provided a semiconductor package having efficiently oriented components.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.

Abstract: Transfer gate (TG) holding trenches are defined in a first interlayer insulating film 44 formed on a silicon substrate 10. TG 33 including side walls 34 are formed in their corresponding trenches. Contact holes are defined in portions adjacent to the TG 33 in a self-aligned manner on the condition that the first interlayer insulating film 44 is selectively removed. Contact plugs 50 are formed in their corresponding contact holes. Bit lines 60 respectively conducted over or to the contact plugs 50 and capacitors are formed over these.

Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Abstract: A light emitting semiconductor package (250) has a semiconductor chip (252) with a surface with one or more light emitting devices (254) formed on or in the surface. A cap (256) is bonded to the surface of the chip (252) to encapsulate the devices (254). The cap has one or more regions (258) transparent to light emitted by the light emitting devices (254). The cap has been bonded to the semiconductor chip (252) at the wafer stage prior to separation of the wafer into individual packages.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: The present invention has an object to provide a photoreceptor array with an excellent device property and no short fault between adjacent photoreceptors and to provide a method of manufacturing such the photoreceptor array with a high yield. On a transparent substrate (31), a transparent electrode (32) and a p-type amorphous silicon layer (33) are formed. An insulating layer (41) is deposited thereon to form a trench (42). In the trench (42), an i-type amorphous silicon layer (34), an n-type amorphous silicon layer (35) and an n-side electrode (36) are buried in turn to form the photoreceptor array.

Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.

Abstract: In the method of fabricating an inductor, at least first and second conductive segments are formed in a semiconductor layer spaced apart in a first direction. A first dielectric layer is formed over a portion of the semiconductor layer along the first direction such that the first dielectric layer crosses the first and second conductive segments. A conductive core is formed on the first dielectric layer, and a second dielectric layer is formed over the semiconductor layer. First and second contact holes are formed in the second dielectric layer such that the first contact hole exposes a portion of the first conductive segment on a first side of the first dielectric layer and the second contact hole exposes a portion of the second conductive segment on a second side of the first dielectric layer.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.

Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: A semiconductor integrated circuit for driving an LCD. The circuit has a shift register circuit portion (3) and a driver circuit portion (7). All the stages of the shift register circuit portion are formed adjacently to the outer fringe of a chip (30). All the stages of the driver circuit portion are formed along the central line (L1) of the chip. Signal electrodes (81-8n) for individual bits are formed in a belt-like region (33) extending in the X-direction along the central line (L1) and adjacently to the driver circuit portion. Output electrodes are arranged in a zigzag fashion. Since the output electrodes overlap with each other in the Y-direction, the width of the chip can be suppressed. Power supply voltages (VH, V0, V2, V3, V5) are applied to the driver circuit portion (7) through leads (36-40). These leads are connected so as to form a closed loop making one revolution around the output electrodes (81-8N) located in the center of the chip.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: The present invention provides a miniature device that comprises a grounded layer, an insulative layer overlying the grounded layer and a conductive layer overlying the insulative layer wherein the insulative spacing between the conductive and grounded layers is increased so as to inhibit electrical shorting between the conductive layer and grounded layers. A method of making miniature devices is also provided.

Abstract: A plurality of semiconductor chips is each arranged over a first conductor. Each of semiconductor chips has a first main electrode, a second main electrode and a control electrode. A second conductor is electrically connected to the second main electrode and has columns each having an upper surface arranged over each of the semiconductor chips and equal to the number of the semiconductor chips. A circuit board has openings penetrated by the columns and equal to the number of the semiconductor chips and has a first insulating film, a third conductive film arranged on a back surface of the first insulating film and electrically connected to the second conductor, and a fourth conductive film arranged on a surface of the first insulating film and electrically connected to the control electrode.

Abstract: A semiconductor device (20) comprising a substrate (1) is provided with a first semiconductor element (3) on a first side (2), of the substrate and with a security coating (14) comprising a matrix, a first filler and a second filler. The second filler is an absorber of radiation of a wavelength of between 800 and 1400 nm and the refractive index of the first filler differs at least 0.3 from that of the matrix. As a result, the security coating inhibits transmission of radiation with a wavelength of between 400 and 1400 nm to a very large extent. The semiconductor device (20) can be incorporated in a smartcard.

Abstract: Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.

Abstract: A substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: A composite ceramic board comprising an insulating board of insulating layers of alumina ceramics and dielectric layers of ceramics having a dielectric constant smaller than that of said insulating layers which are fired as a unitary structure, and metallized wirings of a low-resistance conductor such as of Au, Ag, Cu or Pl formed on the surfaces and inside thereof, and a method of producing the same. The composite ceramic board not only has a large strength and a high thermal conductivity but also exhibits excellent high-frequency characteristics and is suited for use as a high-frequency wiring board. The invention further provides an optical/electronic-mounted circuit substrate using the above board, and a mounted board having the circuit substrate of the invention connected to an electronic circuit formed on a mother board.

Abstract: A matched set of integrated circuit chips (34, 38) includes a chip (34) from a first wafer (22) and a chip (38) from a second wafer (24). The chips (34, 38) of the first and second wafers (22, 24) are tested together as part of a wafer-interposer assembly (10). The matched set comprises a first chip assembly diced from the wafer-interposer assembly (10) having one of the chips (34) from the first wafer (22) and a second chip assembly diced from the wafer-interposer assembly (10) having one of the chips (38) from the second wafer (24). A substrate is electrically coupled to the first and second chip assemblies, the first and second chip assemblies being selected for the matched set based upon sorting of the chips (34, 38) of the first and second wafers (22, 24) as a result of the testing.

Abstract: A method for making a bond-wire interconnect to pass signals between different substrates is described. According to this process, a first compensated bond wire interconnect is made to connect two substrates of a first type at an operating frequency, the first interconnect comprising a bond-wire of a fixed length and a first pair of compensation structures formed from a lowpass filter prototype. A second compensated bond wire interconnect is made to connect two substrates of a second type at the operating frequency, the second interconnect having a bond-wire of the fixed length and a second pair of compensation structures formed from the lowpass filter prototype. A bond-wire of the fixed length, one compensation structure from the first pair, and one compensation structure from the second pair, are combined to make a third compensated bond wire interconnect to connect a substrate of the first type with a substrate of the second type at the operating frequency.

Abstract: A thick film millimeter wave transceiver module includes a base plate and a multi-layer substrate board having a plurality of layers of low temperature transfer tape received on the base plate. The different layers can vary. They can include a DC signals layer having signal tracks in connection; a ground layer having ground connections; a device layer having capacitors and resistors embedded therein; and a top layer having cut-outs for receiving MMIC chips therein. A solder preform layer is located between the device layer and the top layer for securing any MMIC chips. A channelization plate is received over the multi-layer substrate board and a channel is formed to receive MMIC chips and provide isolation between transmit and receive signals.

Abstract: The electronic circuit unit of the present invention includes first and second insulating substrates on respective surfaces of which wiring patterns are formed, and thick-film passive elements formed on the surfaces of the first and second insulating substrates in a state in which they are connected to the wiring patterns, wherein the first and second insulating substrates are disposed vertically opposite to each other, and the wiring patterns provided on the first and second insulating substrates are connected through metallic bumps provided between the first and second insulating substrates.

Abstract: A type of semiconductor device and its manufacturing method, which can further miniaturize semiconductor devices and reduce design restrictions by minimizing the fillet around the semiconductor chip. The semiconductor package is constituted by fixing semiconductor chip 100 on insulating substrate 102 via die paste 104. Semiconductor chip 100 has top surface 112, where an electronic circuit is formed, and a bottom surface 114 adhered to insulating substrate 102. The bottom surface 114 is formed smaller than top surface 112. By forming bottom surface 114 smaller than top surface 112, the amount of the fillet spread out around semiconductor chip 100 can be reduced.

Abstract: A method for forming a semiconductor device including a die attach surface having a first pedestal and a first semiconductor die having a first surface formed with a first cavity for mounting the first semiconductor die on the first pedestal. Further provision is made for the formation of a dielectric cavity in the semiconductor die, the first pedestal or both. The cavity allows for fields produced by electronic components disposed on the upper surface of the semiconductor die to penetrate into the dielectric cavity. Inclusion of a second pedestal on a common die attach surface and a second semiconductor die having second cavity for mounting provides for substantially coplanar precision alignment or the first and second semiconductor die.

Abstract: A semiconductor device includes a first insulating layer having a through hole; a first interconnection having a first conductive layer, a first barrier layer, and a first main interconnection; and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, a problem wherein copper in the first main interconnection transfers from a connection portion thereof to the second interconnection due to electromigration, so that a void is formed at the connected portion resulting in the first interconnection being disconnected from the second interconnection, can be prevented.

Abstract: A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a first conductive material in a first insulating film on a semiconductor substrate and a protrusion formed of a second conductive material in a second insulating film formed on the first insulating film, connected to the upper surface of the body, formed to have a width less than that of the body, and having a planarized upper surface.

Abstract: The circuit structure of the present invention has a plurality of conductive path layers and at least one interlayer isolating layer formed between the plurality of conductive path layers. Each of the plurality of conductive path layers has at least one conductive path capable of transmitting light or electricity therethrough. Each of a plurality of input/output (I/O) sections is connected to any one of the plurality of conductive paths. Each of the plurality of conductive path layers has a first laminated structure that includes a plurality of first conductive layers and at least one first isolating layer formed therebetween. The interlayer isolating layer has a second laminated structure that includes a plurality of second isolating layers and at least one second conductive layer formed therebetween.

Abstract: A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

Abstract: The invention includes a method of electroless deposition of nickel over an aluminum-containing material. A mass is formed over the aluminum-containing material, with the mass predominantly comprising a metal other than aluminum. The mass is exposed to palladium, and subsequently nickel is electroless deposited over the mass. The invention also includes a method of electroless deposition of nickel over aluminum-containing materials and copper-containing materials. The aluminum-containing materials and copper-containing materials are both exposed to palladium-containing solutions prior to electroless deposition of nickel over the aluminum-containing materials and copper-containing materials. Additionally, the invention includes a method of forming a solder bump over an aluminum-containing material.

Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.