Abstract: A fluid control valve, in which the usual metal stem guide bushings have been eliminated, includes a valve bonnet and a packing nut threadably engaging the valve bonnet. A valve stem passes through the valve bonnet and the packing nut in a clearance fit so that there is no engagement therebetween. A single packing set is included, having a middle virgin PTFE sealing ring, a carbon or glass filled PTFE male packing ring on one side and a carbon or glass filled PTFE female ring on the other side. Belleville disk springs may be provided intermediate the packing nut and the packing set, for supplying live loading to the packing. The packing provides sufficient stem guidance, interference fit with the valve stem to enable the usual upper and lower metal guide bushings to be eliminated.

Abstract: A ball valve includes a tubular element having an annular flange extended in the middle portion, and having a valve chamber formed in one end to receive two gaskets and a ball valve member, and having a barrel. A shank is rotatably received in the barrel and coupled to the ball valve member, to rotate the ball valve member relative to the tubular element. A duct includes a peripheral swelling extended from one end and engaged into the valve chamber of the tubular element, and secured to the tubular element with a welding member, for allowing the ball valve member and the gaskets to be easily assembled into the tubular element.

Abstract: An improved rod connector assembly and method for mechanically fastening two rods together. Generally planar mating surfaces of a first rod assembly and a second rod assembly are compressively coupled by a rod union. The compressive load by the rod union is derived from a tapered surface that provides an interference fit to a corresponding tapered surface on the first rod assembly. Clearance diameters provided within the rod union accommodate axial misalignment of the first rod assembly and the second rod assembly. The second rod assembly includes an adjustable rod adapter to provide coupling to rods of various lengths. The first rod assembly includes an internal cavity to receive a portion of the second rod that may protrude from the adjustable rod adapter. Shaped mating surfaces of the rod adapters are received in a corresponding shaped cavity of the union to prevent rotation of the adapters.

Abstract: The invention relates to linear carboxy-functional organosiloxane compounds of the general formula (I) 1

Abstract: The invention relates to the use of a printable polymerisable liquid crystal material as printable system for the preparation of polymers and pigments, to printable polymerisable liquid crystal materials and pigments and polymers prepared thereof, and to the use of the printable materials, pigments and polymers in optical, electrooptical, semiconductor and electronic applications and as birefringent and optically variable markings for decorative, security, authentification or identification applications.

Abstract: A liquid crystal display device having a pair of substrates, a liquid crystal layer filled between the pair of substrates and a plurality of pixel electrodes and common electrodes formed on one of the pair of substrates for supplying an electric field to the liquid crystal layer. The liquid crystal display device is configured so that a response time between a lowest brightness level and a highest brightness level is less than 16.7 ms, and the liquid crystal layer contains a range of 40% or more weight percentage to 100% or less weight percentage of a constituent component with a dielectric anisotropy of &Dgr;&egr;≧1.

Abstract: A liquid crystal composition having a negative dielectric anisotropy, containing at least one compound selected from the group of compounds represented by Formulas (1-1), (1-2), (1-3) and (1-4) as a first component: 1

Abstract: A radiographic image conversion panel including a support, and at least one photostimulable phosphor layer formed on the support by a vapor phase deposition method (vapor phase growth). The panel is manufactured according to deposition, and a temperature of the support at the time of deposition is controlled at 50° C. to 150° C.

Abstract: An &agr;-sialon-based oxynitride phosphor characterized in that the content of &agr;-sialon represented by the general formula: MxS12−(m+n)Al(m+n)OnN16−n:Lny (wherein M is at least one metal selected from among Li, Ca, Mg, Y or lanthanide metals excluding La and Ce, Ln is at least one lanthanide metal selected from among Ce, Pr and La or at least one lanthanide metal selected from among Eu, Dy, Er, Tb and Yb, 0.3≦x+y<1.5, 0<y<0.7, 0.3≦m<4.5, 0<n<2.

Abstract: There is provided a green oxide phosphor for emitting a visible ray, having a general composition formula of Mg1−(x+y)Al2O4:Eux2+, My2+. In the green oxide phosphor, Eu+2 is doped into a crystal of Mg1−(x+y)Al2O4 as an activator; and Mn+2 is added as a co-dopant.

Abstract: The invention relates to a conductive paste containing a glass frit, a paste-forming medium, conductive particles made of silver and particles containing non-precious metal, in order to produce a conductive coating on glass, ceramics or enameled steel, a method for producing said coating and articles coated therewith. According to the invention, the conductive particles containing non-precious metal correspond to up to 80 wt. % of all conductive particles, and are essentially made up of iron, cobalt, nickel, copper, zinc or an alloy containing at least one of these elements, especially nickel, and have an average particle size d50 ranging from 0.1-15 &mgr;m and a specific surface ranging from 0.5-10 m2/g. The glass frits begin to soften at 350° C.-600° C. and have a hemisphere temperature of 450° C.-700° C.

Abstract: The present invention relates to a powder (1) comprising electrically conducting and magnetic particles (2). An electrically conducting, magnetic powder (1) can for example, be used to transfer an electrical signal and/or an electric voltage and/or an electric current between at least two electrical contacts in an electrical component, especially in a potentiometer.

Abstract: A pry bar has generally octagonal cross-section handle with a grip portion having four rounded surfaces formed of a soft elastomeric material and four alternating surfaces formed of hard thermoplastic material. The elastomeric material rounded surfaces are formed with pluralities of small orifices. The handle is formed with an inner hard thermoplastic core and molded over outer elastomeric cover. A metal impact cap is fixed secured in the handle proximate end.

Abstract: A winch for cargo tie-down straps to tie down straps comprising a winch frame having

Abstract: Method and apparatus for elevating an object by a member secured to the object for the elevation thereof; and a mechanism for operating the elevation member, which can be positioned beneath the object, such as a vehicle, where the elevation member is a source of fluid pressure, which can be gaseous or hydraulic and is connected to the member for elevating the vehicle or a portion thereof such as a wheel.

Abstract: A fence panel that includes a self-contained connector system which can be used to interconnect, in assembling an animal enclosure, up to four of the panels quickly and easily without the need for additional posts, connectors, or other apparatus.

Abstract: A small craft hand rail or grab rail has a wood dowel rail, preferably teak, and the rail is supported less than two dowel diameters from the deck by pylons of polymeric plastic preferably of higher modulus than the dowel so that the dowel can be readily removed for replacement or repair. Each pylon has a semicircular groove to receive the rail and is secured to the deck independently of the rail.

Abstract: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder.

Abstract: Particle localization by geometrical nanostructures allows for the fabrication of artificial atoms and molecules suitable for use as building blocks for molecular electronic devices. Artificial lattices made from the artificial atoms and molecules can be used to create artificial networks or arrays. These can be formed by depositing strips of homogeneous semiconductor material on an insulator substrate and etching away unwanted material to form specific lattice shapes, such as by using photolithographic methods or other techniques. The artificial atoms and molecules can be used to form field effect transistors, power and signal amplifiers, artificial electrical conductors, and artificial two-dimensional electronic superconductors. The artificial molecules of the invention can also be employed in constant magnetic fields and probed by electromagnetic fields to produce magnetic memory elements.

Abstract: The present invention provides a substrate for a photoelectric conversion device contributing to enhance further the effect of trapping light into a photoelectric conversion layer. The substrate includes a first undercoating film containing at least one selected from tin oxide, titanium oxide, indium oxide and zinc oxide as a main component, a second undercoating film and a conductive film formed in this order on a glass sheet containing an alkali component. Concavities are formed in the surface of the second undercoating film, and the area ratio of the concavities is in the range of 20% to 50%.

Abstract: A superconductor integrated circuit (1) includes an anodization ring (35) disposed around a perimeter of a tunnel junction region (27) for preventing a short-circuit between an outside contact (41) and the base electrode layer (18). The tunnel junction region (27) includes a junction contact (31) with a diameter of approximately 1.00 &mgr;m or less defined by a top surface of the counter electrode layer (24). The base electrode layer (18) includes an electrode isolation region (36) disposed approximately 0.8 &mgr;m in horizontal distance from the junction contact (31) for providing device isolation.

Abstract: An OLED includes a wide gap inert host material doped with two dopants. One of the dopants is an emissive phosphorescent material that can transport either electrons or holes. The other dopant is a charge carrying material that can transport whichever of the electrons and holes that is not transported by the phosphorescent dopant. The materials are selected so that the lowest triplet energy level of the host material and the lowest triplet energy level of the charge carrying dopant material are each at a higher energy level than the lowest triplet state energy level of the phosphorescent dopant material. The device is capable, in particular, of efficiently emitting light in the blue region of the visible spectrum.

Abstract: A field effect transistor in sandwiched configuration having organic semiconductor, comprising: a substrate (1), a gate electrode (2) formed on the surface of the substrate (1), a gate insulation layer (3) formed on the substrate (1) and the gate insulation layer (2), which is characterized in that, further comprising: an active layer (4) formed on the gate insulation layer (3) but leaving a part of the gate insulation layer (3) to be exposed, a source and drain electrodes (5) formed on a part of the gate insulation layer (3) and a part of the active layer (4), and an active layer (6) formed on the exposed part of the gate insulation layer (3), the active layer (4), the source electrode and the drain electrode (5).

Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included that surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard avoids electrical communication between the probe and areas outside of the object area of the semiconductor wafer.

Abstract: A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.

Abstract: A first semiconductor layer that makes a capacitance coupling with a gate electrode of a thin film transistor through a gate insulating layer and a second semiconductor layer that makes a capacitance coupling with a storage capacitor line of a storage capacitor through the gate insulating layer are formed separately. Also, the first semiconductor layer and the second semiconductor layer are connected by a metal wiring. The gate electrode of the thin film transistor makes capacitance coupling with the first semiconductor layer and the storage capacitor line of the storage capacitor makes capacitance coupling with the second semiconductor layer independently. Voltage are induced in the first semiconductor layer and the second semiconductor layer independently. Since there will be no big discrepancy in voltage in the gate insulating layer, the dielectric break down and the leakage can be prevented.

Abstract: An optical device includes a semiconductor substrate having an opening, a support member disposed on the substrate, and a movable portion disposed on the opening of the substrate. The movable portion is supported by the support member so that the movable portion is movable. The device has a large scanning angle. Further, the device can scan widely at any frequency.

Abstract: To provide a transistor having sufficient dielectric strength, including a gate insulating film which can be formed by easy processes, and not requiring a high-temperature crystallizing process, a method of manufacturing the transistor, and an electro-optical device, a semiconductor device, and an electronic apparatus including the transistor, a transistor includes at least a monocrystalline semiconductor layer and a gate insulating film provided on the monocrystalline semiconductor layer. The gate insulating film has a thermal oxide film formed on the monocrystalline semiconductor layer, and at least one vapor-deposited insulating film formed on the thermal oxide film.

Abstract: A thin film transistor is provided including a transparent insulating substrate, a lower light shielding film disposed above the transparent insulating substrate, a base interlayer film disposed above the lower light shielding film, a semiconductor film disposed above the base interlayer film, wherein the semiconductor film is formed of polycrystalline silicon. A thin film transistor further comprises roughness formed at an interface between the base interlayer and the semiconductor film, a gate insulating film above the semiconductor film, and a gate electrode above the gate insulating film.

Abstract: A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are present in the ranges of less than 10° or 58°-62°.

Abstract: The invention relates to an image sensor device comprising a substrate, formed in CMOS technology, in particular, with an integrated semiconductor structure (ASIC) and, arranged above that, an optically active thin-film structure comprising in each case at least one layer made of doped and undoped amorphous silicon, spatially adjacent pixels in each case being formed in the horizontal plane, which pixels each have an optoelectronic transducer for converting incident light into an electric current proportional to the incident quantity of light, and also a charge store assigned to the optoelectronic transducer, the charge state of which charge store can be varied in a manner dependent on the light incident on the assigned optoelectronic transducer.

Abstract: To provide a nitride semiconductor element exhibiting low leakage current and high ESD tolerance, the nitride semiconductor element according to the present invention includes an active layer of nitride semiconductor that is interposed between a p-sided layer and an n-sided layer, which respectively consist of a plurality of nitride semiconductor layers, the p-side layer including a p-type contact layer as a layer for forming p-ohmic electrodes, the p-type contact layer being formed by laminating p-type nitride semiconductor layers and n-type nitride semiconductor layers in an alternate manner.

Abstract: The optical semiconductor apparatus includes, on an n-GaAs substrate, a surface-emitting semiconductor laser device and a photodiode integrated on the periphery of the laser device with an isolation region interposed there between. The laser device is composed of an n-DBR mirror, an active region, and a p-DBR mirror and includes a columnar layered structure with its sidewall covered with an insulating film. The photodiode is formed on the substrate and has a circular layered structure wherein an i-GaAs layer and a p-GaAs layer surrounds the laser device with an isolating region interposed between the i-GaAs and p-GaAs layers and the laser device. The diameter of the photodiode is smaller than the diameter of the optical fiber core optically coupled with the optical semiconductor apparatus. Since the laser device and the photodiode are monolithically integrated, the devices do not require optical alignment, and thus, facilitate optical coupling with an optical fiber.

Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element comprises: a sapphire substrate; a first single crystalline layer of AIN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN(0.8≦x≦0.97) and having a thickness of equal to or more than 0.3 &mgr;m and equal to or less than 6 &mgr;m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.

Abstract: A Peltier effect cooling device is formed in combination with an electronic device to form a unique thermal and electrical relationship. An electronic device to be cooled is placed in a serial electrical relationship between at least two thermoelectric couples while simultaneously being in thermal contact with a cold side of the cooler arrangement. The same current which produces the thermoelectric effect in the Peltier thermocouples also drives the electronic device. A balanced effect results as a higher driving current through the electronic device causes greater heating, it is offset by the added cooling due to a greater current in the thermocouples. In addition, a unique spatial arrangement provides improved heat distribution and transfer to a heat sink. Due to the unique shapes of Peltier elements, heat is pulled radially from a heat generating source and distributed at a peripheral region.

Abstract: An optoelectronic device and a method of making same. The optoelectronic device comprises a substrate, at least one dielectric waveguide in the substrate, and at least one active semiconductor layer physically bonded to the substrate and optically coupled to the at least one dielectric waveguide in the substrate, the at least one active semiconductor layer being able to generate light, detect light, amplify light or otherwise modulate amplitude or phase of light.

Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

Abstract: In order to reduce the possibility of a laser operating in multiple transverse modes at high power, the laser is provided with laterally asymmetric losses that discriminate against modes higher than the fundamental mode. One approach to doing this is form an asymmetric ridge waveguide in the laser, that allows the light of the higher order modes to leak out of the waveguide.

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Abstract: A semiconductor device includes an N channel MOS transistor. The N channel MOS transistor includes a first P type buried layer that isolates an N− epitaxial region formed on a P type substrate (P-SUB) from another N− epitaxial region, a drain formed in an N well in the N− epitaxial region, a source formed in a P well surrounding side faces of the N well so as to be separated from the N well, and a gate formed on each upper layer portion of the drain and the source. The MOS transistor also includes a second P type buried layer formed below the N well and the P well so as to be joined to the P well, and an N+ buried layer formed so as to be joined to the P type buried layer and the P-SUB. The N− epitaxial region, the P-SUB, and the first P type buried layer are connected to ground potential.

Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1-x-yN, wherein x+y=1, 0≦x≦1, and 0≦y≦1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: The present invention is directed to high frequency, high power or low noise devices such as low noise amplifiers, amplifiers operating at frequencies in the range of 1 GHz up to 400 GHz, radars, portable phones, satellite broadcasting or communication systems, or other devices and systems that use high electron mobility transistors, also called hetero-structure field-effect transistors. A high electron mobility transistor (HEMT) includes a substrate, a quantum well structure and electrodes. The high electron mobility transistor has a polarization-induced charge of high density. Preferably, the quantum well structure includes an AlN buffer layer, an un-doped GaN layer, and an un-doped InAlN layer.

Abstract: A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324. a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 that is composed of an undope In0.48Ga0.52P, an n+-type GaAs cap layer 328, a gate electrode 330 that is formed on the Schottky layer 327, is composed of LaB6 and has a Schottky contact with the Schottky layer 327 and ohmic electrodes 340 that are formed on the n+-type GaAs cap layer 328.

Abstract: A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-aligned relative to the self-aligned dielectric sidewall spacer providing a predetermined base-to-emitter spacing thereby. The emitter may be an n-type, InP material; the base can be a p-type InGaAs material, possibly carbon-doped. The fabrication method includes forming a emitter electrode on an emitter layer; using the emitter contact as a mask, anisotropically etching the emitter exposing the base layer; forming a self-aligned dielectric sidewall spacer upon the emitter and base; self-alignedly depositing a self-aligned base electrode; using the self-aligned base electrode as a mask, anisotropically etching the base layer to expose the subcollector; and depositing a collector electrode on the subcollector layer.

Abstract: An electrochemical device comprising at least one substrate (1,7), at least one electroconductive layer (2,6) at least one electrochemically active layer (3,5) capable of reversibly injecting ions, and an electrolyte (4), wherein the electrolyte (4) is a layer or a multilayer stack comprising at least one layer (4b) made of an ionically conductive material capable of reversibly injecting said ions but whose overall degree of oxidation is maintained essentially constant.

Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.

Abstract: In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.

Abstract: A silicidation blocking layer (SBL) pattern is formed on a substrate including an active region and a field region. The SBL pattern covers the field region and exposes the active region. A silicide layer is formed on the active region by reacting metal with silicon existing in the active region. An insulation layer is formed on the substrate including the silicide layer. An opening exposing the silicide layer is formed by selectively etching the insulation layer under a condition having an etching selectivity between the SBL and the insulation layer. Conductive material is filled up the opening. The field region of a substrate is sufficiently protected by the SBL pattern without any additional process so that the failure of a semiconductor device is effectively prevented because the flow of a leakage current through the field region is blocked.