Abstract: The present invention relates to an AC drive surface discharge type plasma display panel having an isosceles delta array type pixel. The background art has a problem of being apt to cause a wrong writing discharge and having a narrow writing voltage margin. Then, in the present invention, transparent electrodes for X electrode (T3, T4) in first and second pair subpixel regions (PSPR1, PSPR2) of an isosceles delta array type pixel (P1) are provided at portions farther away from a first write electrode (Wj(B)) in an isolated subpixel region (ISPR). Specifically, a central axis of the third transparent electrode (T3) along a vertical direction (v) is positioned closer to an extending portion (WAE) of a second write electrode (Wj(A)) from a vertical direction central axis of the first pair subpixel region (PSPR1).

Abstract: Methods and apparatus in accordance with the present invention may employ a layer of tungsten nitride having a ratio of nitrogen to tungsten that is below about 0.7 at and a layer of tungsten formed on the layer of tungsten nitride to obtain a conductive material.

Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Abstract: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts and electrical interconnection leads may also be substantially transparent. Methods for making and using such double-injection field-effect transistors are also disclosed.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.

Abstract: A ferroelectric capacitor and a method for manufacturing the same includes a lower electrode, a dielectric layer, and an upper electrode layer, which are sequentially stacked, wherein the dielectric layer has a multi-layer structure including a plurality of sequentially stacked ferroelectric films, and wherein two adjacent ferroelectric films have either different compositions or different composition ratios. Use of a ferroelectric capacitor according to an embodiment of the present invention, it is possible to hold stable polarization states of ferroelectric domains for a long retention time, and thus data written in the ferroelectric capacitor a long time ago can be accurately written, thereby improving the reliability of a ferroelectric random access memory (FRAM).

Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.

Abstract: Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Also disclosed are methods of forming the capacitor structures and capacitors in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.

Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal.

Abstract: In order to supply a semiconductor device having high-reliability, there are used a first capacitor electrode, a capacitor insulating film formed in contact with the first capacitor electrode and mainly composed of titanium oxide, and a second capacitor electrode formed in contact with the capacitor insulating film, and there is used a conductive oxide film mainly composed of ruthenium oxide or iridium oxide for the first capacitor electrode and the second capacitor electrode. Alternatively, there is used a gate insulating film having a titanium silicate film and titanium oxide which suppress leakage current.

Abstract: In a method for fabricating a semiconductor device including a PIP capacitor and a MOS transistor, an isolator film is formed on a semiconductor substrate and then etched to expose an active region of the substrate. An epitaxial film is then formed by performing a selective epitaxial silicon growth process on the active region. A first polysilicon film, a dielectric film and a second polysilicon film are then sequentially formed. Next, an upper electrode is created by patterning the second polysilicon film. After a lower electrode and a gate electrode are formed by patterning the first polysilicon film, a source and a drain of a source/drain region are formed into the epitaxial film. Subsequently, after an interlayer insulation film is created on a resultant structure, contact holes are formed thereinto and contacts connected to the upper electrode, the lower electrode, the gate electrode and the source/drain region are formed.

Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.

Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.

Abstract: A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.

Abstract: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.

Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

Abstract: A non-volatile SONOS memory device includes a semiconductor substrate having a source region and a drain region. A channel is formed between the source region and the drain region. A gate insulation layer including a nitride layer is formed over the channel, and a gate is formed over the gate insulation layer. The channel is a stepped channel including a top part, an inclined part and a bottom part.

Abstract: The present invention creates a semiconductor power component having an anode contact (502) on the reverse side; an emitter region (505) of a first conductor type (p+), on the reverse side, which is connected to the anode contact (502) on the reverse side; a drift zone (504, 514, 540) which is connected to the emitter region (505) that is on the reverse side and extends partially to the front surface; an MOS control structure (503, 506, 560, 508, 580, 509) on the front side, having a control contact (503) that is positioned in insulated fashion; a cathode contact (501) on the front side which is connected to a source region (506) and a first body region (508). Drift zone (504, 514, 540) has a first drift region (540) of second conductor type (n−), a second drift region (504) of second conductor type (n) and a third drift region (514) of first conductor type (p). First drift region (540) is a buried region. Second drift region (504) connects the front surface to first drift region (540).

Abstract: A semiconductor device has enhanced drain and gate structures where a high conductivity region 12 is added to enhance current conduction, and further region 23 with opposite polarity is included to improve breakdown voltage. Regions 12 and 23 are disposed in the epitaxial layer portion of the drain. A thicker insulator is also formed in the gate-to-drain region. Furthermore, a gate structure with a trench is formed in a portion of the drain region, having lateral and vertical gate electrode elements and thick gate to drain insulator. Gate capacitance and resistance are improved by the gate and drain structures of this invention.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.

Abstract: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit light, allowing a photodetector to respond to transmitted light to stimulate a retina, for example. Discrete electronic components may be placed in the three-dimensional street area of the integrated circuit package, yielding a completely integrated hermetic package that is implantable in living tissue.

Abstract: M pieces of n-well regions nW are provided on a main surface of a p-type silicon substrate 3, and p-well regions pW are provided among the n-well regions adjacent to one another. Moreover, each of the M pieces of n-well regions nW includes an n-type diffusion region nD and a p-type diffusion region pD1, which are formed therein. Furthermore, the p-well region pW includes a p-type diffusion region pD2 therein. The n-type diffusion region nD in a j-th of the n-well region nW is connected to the p-type diffusion region pD1 in a (j+1)-th of the n-well region 10. The p-type diffusion region pD1 in the first n-well region nW is connected to a first terminal 1. The n-type diffusion region nD in the M-th of the n-well region nW is connected to a second terminal 2.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract: The three-dimensional memory (3D-M) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, 3D-M has minimum impact to the layout of the CUT. The CUT with integrated 3D-M supports IC self-test. Moreover, with a large bandwidth with the CUT, 3DM-based IC self-test enables at-speed test.

Abstract: The present invention discloses an nF-opening-based mask-programmable read-only memory. Because its openings can be nx (n>1) wider than its address-selection lines, this memory can use less expensive opening mask. Other mask-programmable 3-D memory (3D-M) structures are also disclosed. The present invention makes further improvements to the 3D-M's peripheral circuits. Full-read mode and self-timing can be used to improve the speed and reduce the power consumption.

Abstract: A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

Abstract: A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.

Abstract: In a gallium phosphate crystal, a crystallographic Y-axis and a Z-axis that have been rotated about an X-axis counterclockwise through an angle &agr; is referred to as a Y′-axis and a Z′-axis, respectively, where the angle &agr; is in a range from 10° to 20°. A piezoelectric crystal material made of gallium phosphate is provided as a plate-shaped member which is elongate in an X-axis direction and cut from the gallium phosphate crystal parallel to an X-Z′ crystal plane of the gallium phosphate, and the plate-shaped member has sides parallel to an axis that is obtained by rotating the Y′-axis counterclockwise about the X-axis in an angular range from 1° to 3°.

Abstract: A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

Abstract: A magnetic bit structure for a magneto-resistive memory is disclosed that has bit ends that are sufficiently large to accommodate a minimum size contact or via hole. By providing such an arrangement, the magnetic bit structure may be fabricated using conventional contact and/or via processing steps. As such, the cost of manufacturing the device may be reduced, and the overall achievable yield may be increased.

Abstract: A shield device is provided in which a layer of deformable electrically conductive material is conformed to fit over the components [692] on the board. In one embodiment of the invention the deformnable material is conductive foam [600], such as metalized foam. One or both sides of the foam layer [6001 can be covered with dielectric material. Portions of the dielectric material and foam can be removed, such as from the bottom layer [615 ] to create insulating slants [615a] over the component. The board can be placed over the components, which are received in recesses in the shield which are either preformed or result from compression of the deformable material at the location of the components. In one embodiment of the invention, regions of a conductive layer are removed and the layer is placed over the components. A top layer [610] is placed thereover. The invention also relates to the method of foaming the board level shield.

Abstract: A diffraction-grating type sensor chip for analyzing a sample using surface plasmon resonance (SPR), and a method and apparatus for analyzing a sample using the sensor chip. The sensor chip includes a plurality of diffraction grating surfaces (5a-5i) which are disposed in the vicinity of a metal layer (3); the groove pitch and the groove orientation of each diffraction grating surface (5a-5i), in addition to the angle that each diffraction grating surface (5a-5i) forms with a predetermined reference plane (S0), are adjusted in such a manner that when the diffraction grating surfaces (5a-5i) are projected onto a predetermined projection plane, the groove orientations in the projection plane are identical while the groove pitches in the projection plane are different among the diffraction grating surfaces (5a-5i).

Abstract: In case of chlorine doping, a CdTe-base compound semiconductor single crystal used for an electro-optic element has a crystal which is set to chlorine concentration ranging from 0.1 ppmwt to 5.0 ppmwt and has no precipitation having diameter of 2 &mgr;m or above. In case of chlorine doping, an indium doping, a CdTe-base compound semiconductor single crystal used for an electro-optic element has a crystal which is obtained from a CdTe material melt, to which indium is doped at concentration ranging from 0.01 ppmwt to 1.0 ppmwt, according to a liquid phase epitaxial growth method and has a solidification ratio of 0.9 or below.

Abstract: The invention relates to an opto-electronic component for converting electromagnetic radiation into an intensity-dependent photocurrent, comprising a substrate (1) with a microelectronic circuit whose surface is provided with a first layer (7) which is electrically contacted thereto and made of amorphous silicon a-i:H or alloys thereof, and at least one other optically active layer (8) is disposed upstream from said first layer in the direction of incident light thereof (7). The invention also relates to the production thereof. The aim of the invention is to improve upon an opto-electronic component of tho above-mentioned variety in order to obtain high spectral sensitivity within the visible light range and, correspondingly, significantly reduce sensitivity to radiation in the infrared range without incurring any additional construction costs.

Abstract: An optical component, in particular an eye implant of a transparent material, to which there is added at least one transparent filler having a higher refractive index than that of the component material and of a particle size at which substantially no light scatter occurs in the component material.

Abstract: A semiconductor device includes a semiconductor region of a first conductive type. First and second regions of a second conductive type opposite to the first conductive type are provided in a surface of the semiconductor region in a predetermined interval. A third region of the first conductive type is provided between the first and second regions in the surface of the semiconductor region. A fourth region of the first conductive type is provided below the third region inside the semiconductor region to cover the whole of bottom of the third region at least.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.

Abstract: Provided is a semiconductor reliability evaluating apparatus for evaluating an electro-migration characteristic of a wiring layer which is capable of being formed simply and in a low cost using a reticle set, having a minimum number of reticles, which is capable of measuring an ordinary via plug resistance where the number of wiring layer is two. A first wiring layer and a second wiring layer are configured so that the first wiring layer is connected to the second wiring layer with a plurality of via plugs formed in an insulating layer which is placed between the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are made of metals having almost same specific resistances, and each different parasitic resistances are put to at least one of the first wiring layer and the second wiring layer connected to each of the plurality of via plugs to make the total resistance value of the current path through each of the plurality of via plugs different.