Abstract: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: A digital X-ray panel and method of fabricating an X-ray detector panel assembly is provided. The method includes forming a detector matrix on the detector substrate, forming a dam on the detector substrate circumscribing the detector matrix, forming a scintillator material on the detector matrix, and forming a hermetic covering on the scintillator material that at least one of extends to a surface of the dam and extends past the dam. The digital X-ray panel assembly includes a detector substrate, a detector matrix formed on said detector substrate, a dam formed on said detector substrate circumscribing the detector matrix, a scintillator material formed on the detector matrix, and a hermetic covering formed on the scintillator material that at least one of extends past the detector matrix and the dam, and extends past the detector matrix onto a surface of the dam.

Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.

Abstract: A semiconductor package utilizing insulating peripheral sealing portions and pattern leads and methods for manufacturing such semiconductor packages are provided. The semiconductor package includes a substrate on which a semiconductor chip is mounted. The substrate includes a plurality of substrate pads and the semiconductor chip includes a plurality of chip pads on an active surface. The semiconductor chip is surrounded by one or more peripheral sealing layers and conductive lead patterns are formed across the peripheral sealing layer(s) to connect the chip pads to corresponding substrate pads. The chip and lead patterns may be encapsulated and the substrate may also be provided with external connection structures such as solder balls to complete the package.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A semiconductor package for three-dimensional mounting is provided. The package includes a wiring substrate having a first surface on which a first wiring pattern is formed and a second surface on which a second wiring pattern is formed, the first wiring pattern and second wiring pattern being electrically connected to each other; a semiconductor chip placed on the first surface of the wiring substrate and electrically connected to the first wiring pattern; a sealing resin layer sealing the semiconductor chip and the first wiring pattern; a thickness direction wire passing through the sealing resin layer in a thickness direction and having one end electrically connected to the first wiring pattern and the other end exposed at the surface of the sealing resin layer; and a lower surface connecting electrode formed on the second surface of the wiring substrate and electrically connected to the second wiring pattern.

Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Abstract: The invention provides semiconductor devices that are excellent in mountability. The invention also provides manufacturing methods, circuit substrates and electronic equipments for the same. A method of manufacturing a semiconductor device includes mounting a semiconductor chip having electrodes on a substrate having wiring patterns, and forming conductive layers that electrically connect the electrodes and the wiring patterns in a manner to pass side surfaces of the semiconductor chip.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: A wafer-interposer assembly (10) includes a semiconductor wafer (12) having a plurality of semiconductor die (14) that have a plurality of first electrical contact pads (16). An interposer (22) is connected to the semiconductor wafer (12) such that a plurality of second electrical contact pads (26) associated with the interposer (22) are respectively connected to at least some of the first electrical contact pads (16) via conductive attachment elements (20). A communication interface (28) is integrally associated with the interposer (22) and electrically connected to at least some of the plurality of second electrical contact pads (26). The interposer (22) and the semiconductor wafer (12) are operable to be singulated into a plurality of chip assemblies.

Abstract: To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

Abstract: A depression is formed from a first surface of a semiconductor substrate on which is formed an integrated circuit. An insulating layer is provided on the inner surface of the depression. A first conductive portion is provided on the inside of the insulating layer. A second conductive portion is formed on the inside of the insulating layer and over the first conductive portion, of a different material from the first conductive portion. The first conductive portion is exposed from a second surface of the semiconductor substrate opposite to the first surface.

Abstract: Methods and apparatuses for packaging a microelectronic device. One embodiment can include a packaged microelectronic device comprising a microelectronic die, an interposer substrate, and a casing encapsulating at least a portion of the die. The microelectronic die can have a first side attached to the substrate, a plurality of contacts on the first side, and an integrated circuit coupled to the contacts. The die can also include a second side with a plurality of first interconnecting elements on the second side of the die, such as first non-planar features. The casing can include an interior surface and a plurality of second interconnecting elements on the interior surface, such as second non-planar features. The first non-planar features on the second side of the die mate with second non-planar features on the interior surface of the casing. Accordingly, delamination along the interface between the microelectronic die and the casing is inhibited.

Abstract: In one exemplary embodiment, a structure comprises a substrate having a top surface, and a die attach pad situated on the top surface of the substrate. The die attach pad includes a die attach region and at least one substrate ground pad region electrically connected to the die attach region. The die attach pad further includes a die attach stop between the die attach region and the at least one substrate ground pad region. The die attach stop acts to control and limit die attach adhesive flow out to the at least one substrate ground pad region during packaging so that the at least one substrate ground pad region can be moved closer to die attach region so that shorter bond wires for connecting the at least one substrate ground pad region to a die wire bond pad may be used during packaging.

Abstract: An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.

Abstract: An epoxy resin composition comprising (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, and (D) an effective flux component selected from among abietic acid, palustric acid, levopimaric acid and dihydroabietic acid is low volatile and exhibits improved wetting and adherent properties to solder balls. The epoxy resin composition is used to cover and encapsulate a semiconductor chip, especially as no-flow underfill material, forming a highly reliable semiconductor device.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: It is possible to prevent deterioration of a soldering portion and improve strength of thermal fatigue resistance by providing barrier metal layers on at least one of lead and land to cover parent materials comprising Cu-containing materials, feeding a soldering material between the lead and the land and allowing to contact in a fused condition with barrier metal layers and solidify, and thus soldering together the lead and the land.

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region.

Abstract: A new method is provided for the interface between a heat spreader and the substrate of a thermally improved PBGA package. The heat spreader interfaces with the substrate with the standoff of the heat spreader. The stand-off of the heat spreader is provided with an opening, the stand-off of the heat spreader is aligned with the substrate of the PBGA package by means of a copper pad that is provided over a second surface of the substrate. A gold stud bump or a solder bump are further provided over the surface of the copper pad for alignment purposes. Thermally conductive epoxy or solder is deposited over the opening of the heat spreader and therewith over the copper pad provided over a second surface of the substrate.

Abstract: An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.

Abstract: Ions are implanted into the dielectric layer and/or barrier layer over a semiconductor substrate to change the polish rates of either or both layers during formation of a shallow trench isolation (STI) structure. The ion implantation can change or affect the polish rates of the material and the polish selectivity, and reduce or minimize unwanted topography resulting from chemical mechanical polishing (CMP). After CMP, the resulting STI structure has a more uniform and smooth topography.

Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.

Abstract: An invention is provided for an overlapping row decode in a multiport memory. The overlapping row decode includes a first plurality of predecode wires positioned on a first metalization layer. The first plurality of predecode wires is configured to address wordline drivers of a first port. In addition, a second plurality of predecode wires is located on a third metalization layer above the first metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. The overlapping row decode further includes a plurality of wordline connections that are formed on a second metalization layer between the first metalization layer and the third metalization layer. The plurality of wordline connections includes a first portion and a second portion. The first portion of wordline connections is in communication with the first plurality of predecode wires and the wordline drivers of the first port.

Abstract: There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

Abstract: A semiconductor integrated circuit device able to configure a desired circuit in accordance with a circuit configuration instruction signal given from the outside and able to operate the configured circuit is provided. The semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements, and the desired circuit is configured by combining the circuit elements via said connection elements which become the conductive state or the nonconductive state in accordance with the control signals.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A vertical routing structure inside a substrate for connecting a pair of trace lines electrically. The trace lines are positioned on the top and bottom surface of a stack layer. The vertical routing structure includes a conductive rod and two bonding pads. The conductive rod passes through the stack layer such that the top and bottom surface of the conductive rod are also exposed on the top and bottom surface of the stack layer. In addition, a bonding pad is also attached to the top and bottom surface of the conductive rod respectively. The bonding pads are connected to the aforementioned trace lines. The two bonding pads have a transverse sectional area smaller than the transverse sectional area of the conductive rod. Thus, the vertical routing structure is able to reduce surface area needed to accommodate inter-layer connections and increase routing density within the substrate.

Abstract: A copper metallization structure includes a dielectric pattern formed on a surface of a substrate. Sequentially formed on the dielectric pattern are a first Ru layer and an oxide film. The copper metallization structure further includes a second Ru layer formed on the oxide film and a Cu layer formed on the second Ru layer.

Abstract: A semiconductor device having a multilayer structure is disclosed, which comprises at least two wiring layers, and a via contact formed between the at least two layers and made of the same metal wiring material as the metal wiring material of the at least two wiring layers, wherein the metal wiring material of the via contact contains an additive which is not contained in the metal wiring materials of the at least two wiring layers.

Abstract: A semiconductor device is provided which is capable of preventing corrosion of circuit portion and ensuring high reliability by optimizing a construction of outer-surrounding protecting walls that surround an internal element region to completely stop invasion of water from an edge portion of a semiconductor chip. The outer-surrounding protecting walls made up of a wiring layer and a via layer are formed in a manner to surround the internal element region and that a distance between an edge portion of the semiconductor chip and the outermost-surrounding protecting wall is 30 &mgr;m. The outer-surrounding protecting wall is so formed as to doubly or more surround the internal element region.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A packaging technology that fabricates a microelectronic package including build-up layers, having conductive traces, on an encapsulated microelectronic die and on other packaging material that surrounds the microelectronic die, wherein an moisture barrier structure is simultaneously formed with the conductive traces. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side. Packaging material(s) is disposed adjacent the microelectronic die side(s), wherein the packaging material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then formed on the first dielectric material layer to electrically contact the microelectronic die active surface.

Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.

Abstract: A method of fabricating a semiconductor device including: a first step of forming a through hole in a semiconductor element having electrodes on a first surface; and a second step of forming a conductive layer which is electrically connected to the electrodes and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface. The conductive layer is formed to have connecting portions on the first and second surfaces so that a distance between at least two electrodes among the electrodes is different from a distance between the connecting portions on at least one of the first and second surfaces, in the second step.

Abstract: A method of fabricating a semiconductor device including: a first step of forming a through hole in a semiconductor element having electrodes on a first surface; and a second step of forming a conductive layer which is electrically connected to the electrodes and is provided from the first surface through an inner wall of the through hole to a second surface of the semiconductor element which is opposite to the first surface. The conductive layer is formed to have connecting portions on the first and second surfaces so that a distance between at least two electrodes among the electrodes is different from a distance between the connecting portions on at least one of the first and second surfaces, in the second step.

Abstract: In the ceramic circuit board, within the through hole of the ceramic substrate is arranged the metal column which is 0 to 150 &mgr;m shorter relative to the thickness of the ceramic substrate; the metal circuit plates are attached to both surfaces of the ceramic substrate to stop up the through hole; and the metal column and the metal circuit plate are bonded together via the brazing material. For its manufacture, the metal column with brazing material is used that is made 40 to 140 &mgr;m longer relative to the thickness of the ceramic substrate by being formed of the metal column which is 0 to 150 &mgr;m shorter relative to the thickness of the ceramic substrate and has its both ends coated with the brazing material.

Abstract: A chip package structure and manufacturing process thereof is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

Abstract: A first level packaging assembly includes a chip-mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of external connection lands disposed on the first surface; a plurality of solder balls connected to the external connection lands; a plurality of internal connection lands disposed on the second surface; a plurality of solder joints connected to the internal connection lands including solder materials having lower melting temperature than the solder balls; a semiconductor chip defined by a third surface and a fourth surface opposite to the third surface, connected to the solder joints on the third surface; and an underfill resin sandwiched between the second and third surfaces so as to mold the solder joints.

Abstract: A method for making a semiconductor device includes mounting a die on a die-mounting substrate, providing an interposer on the substrate, forming a conductive strip that is laid on the interposer and that is electrically connected to a bonding pad of the die and to a contact of the substrate, forming an encapsulant layer on the interposer, and forming a solder bump that is electrically connected to the conductive strip and protrudes outwardly from the encapsulant layer.

Abstract: The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die. The invention also encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings.

Abstract: The resin-encapsulated semiconductor device of the present invention includes: a die pad provided by thinning a lower portion of a lead frame; a semiconductor chip mounted on the die pad; a plurality of leads provided by thinning an upper portion of the lead frame; a connection member for connecting the semiconductor chip and the lead with each other; a plurality of suspension leads connected to the die pad; and an encapsulation resin for encapsulating an upper portion of the lead frame. In this way, it is possible to further reduce the thickness of a resin-encapsulated semiconductor device, while upsetting the die pad. Furthermore, the stress occurring from the encapsulation resin is absorbed by the self flexural deformation of the die pad and the lead, which are thinned, thereby improving the connection reliability.

Abstract: Provided are a mold die for molding a chip array, molding equipment including such a mold die and a molding method utilizing such molding equipment. The mold die provides for the selective injection of mold resin through a corner gate controlled by a gate block whereby the flow of the mold resin is neither perpendicular nor parallel to the side surfaces of the semiconductor chips arranged in the chip array. In this manner failures associated with the sweeping effects of the mold resin flowing past the bonding wires on the semiconductor chips may be reduced.

Abstract: The resin-encapsulated semiconductor device of the present invention includes: a die pad provided by thinning a lower portion of a lead frame; a semiconductor chip mounted on the die pad; a plurality of leads provided by thinning an upper portion of the lead frame; a connection member for connecting the semiconductor chip and the lead with each other; a plurality of suspension leads connected to the die pad; and an encapsulation resin for encapsulating an upper portion of the lead frame. In this way, it is possible to further reduce the thickness of a resin-encapsulated semiconductor device, while upsetting the die pad. Furthermore, the stress occurring from the encapsulation resin is absorbed by the self flexural deformation of the die pad and the lead, which are thinned, thereby improving the connection reliability.

Abstract: The present invention provides a thermosetting resin composition useful as an underfilling sealing resin which enables a semiconductor device, such as a CSP/BGA/LGA assembly which includes a semiconductor chip mounted on a carrier substrate, to be securely connected to a circuit board by short-time heat curing and with good productivity, which demonstrates excellent heat shock properties (or thermal cycle properties); and permits the CSP/BGA/LGA assembly to be easily removed from the circuit board in the event of semiconductor device or connection failure. Similarly, the compositions are useful for mounting onto a circuit board semiconductor chips themselves.

Abstract: The preferred embodiments provide a lead frame wherein a first air vent 29 and a second air vent 30 are formed in an air vent forming region 32. When resin-molding, one end of this first air vent 29 is disposed within the cavity, whereby air in the cavity when resin-molding can be completely released to the outside of the cavity. As a result, a package after resin-molding includes no unfilled regions or voids, whereby a semiconductor device with excellent product quality can be provided. In the background, air in cavities could not be completely released when resin-molding since, for instance, one air vent was provided at a position apart from the cavity region, and unfilled regions or voids were created.

Abstract: An air intake deflector to deflect air towards twin carburetors including a specifically sized and configured element inserted inside an existing air intake adaptor and the air intake deflector being situated between two separate spaced apart holes leading to two separate carburetors.