Abstract: An organic TFT including an organic film, first and second electrodes each disposed in contact with opposite surfaces of the organic film each other; and a third electrode disposed at a specified distance from each of the first and second electrodes, the third electrode being applied with a voltage to control current flowing from one of the first and the second electrodes to the other through the organic film; and the organic film including a compound represented by general formula [1]. In this TFT, the carrier moves from one of the first and the second electrodes to the other in the direction of the film thickness of the organic film. The device structure realizes the enough short channel length. The organic film provides the higher mobility, thereby the organic TFT with the sufficiently higher speed response is realized.

Abstract: In the production of thin film transistor (TFT), a gate insulating film is formed to cover an active layer, a titanium nitride film is formed on the gate insulating film, and an aluminum film used as the gate electrode is formed on the titanium nitride film. The resulted configuration prevents the etching of the aluminum film from the insulating film side even if the etchant of aluminum enters the recessed portion at the edge of the active layer during the patterning of the gate electrode. Also in the anodizing process, when an oxide film is formed on the surface of the aluminum film, the oxidation of aluminum from the gate insulating film side is prevented even when the electrolyte solution enters the recessed portion at the edge of the active layer.

Abstract: The number of TFT (20), thin film transistors for controlling the supplied power to an element to be driven such as an organic EL element (50) which operates based on the supplied power, provided between the element to be driven and a power supply line VL, is equal to n, where n is an integer greater than or equal to two. The n TFTs (20) and corresponding element to be driven (50) are electrically connected by contact points, the number of which is less than or equal to (n−1). It is possible to improve the reliability as a semiconductor device and a display device, and, at the same time, to secure maximum actual operation region (illumination region for an illuminating element) of the element to be driven.

Abstract: A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.

Abstract: A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting substantially the same function as the lightly doped drain regions, wherein the lightly activated high impurity concentration regions are bounded with high impurity concentration regions serving as source and drain regions. The boundaries are self-aligned to edges of a gate electrode. Side regions of the gate electrode overlap the lightly activated high impurity concentration regions.

Abstract: There is a problem in that, in a liquid crystal display panel in which a color filter is formed on an opposing substrate, it is necessary to assemble an element substrate and the opposing substrate by extremely high precision position alignment, and when this precision is low, the aperture ratio decreases and the display becomes darker. With the present invention, red color filters (R) are formed on driving circuits (402, 403), peripheral circuits, and a color filter (405d) for protecting a pixel TFT portion (407) is formed for each pixel.

Abstract: An array of light emitting diodes (LED) are laid out as a dot matrix array as a display panel. Each LED is accessed by two dimensional addressing from a first set of parallel horizontal interconnections and a second set of orthogonal interconnections. The two sets of orthogonal interconnections are printed on two sides of a substrate. One of the two electrodes of an LED, which mounted on the top of the substrate, is fed through the substrate with a via hole and connected to the orthogonal interconnection at the bottom of the substrate. The size of the display panel is configurable by removing certain rows and/or columns. More than one partitioned blocks can be pieced together by aligning and coupling the corresponding orthogonal interconnections through a motherboard.

Abstract: A method for manufacturing an organic EL device in accordance with the invention includes: coating a composition including an organic EL material on a plurality of electrodes to form an organic EL layer on each electrode; defining an effectively optical area in which the plurality of electrodes are formed; and defining a coating area which is broader than the effectively optical area, on which the composition including an organic EL material is to be coated. According to this method, a uniform display device without uneven luminance and uneven chrominance within a pixel or among a plurality of pixels in the effectively optical area can be obtained.

Abstract: A LED of flip-chip design comprises a light emitting region and one or more transparent substrates overlying the light emitting region. The light emitting region includes a negatively doped layer, a positively doped layer, and an active p-n junction layer between the negatively doped layer and the positively doped layer. At least one of the substrates has a pyramidal shape determined by (1) the composition of electrically conductive or electrically non-conductive material, (2) the number of side surfaces, (3) the degree of offset of an apex or top surface, and (4) the slope angle of each side surface relative to a bottom surface.

Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a first cladding layer of a Group III nitride, a second cladding layer of a Group III nitride, and an active layer of a Group III nitride that is positioned between the first and second cladding layers, and whose bandgap is smaller than the respective bandgaps of the first and second cladding layers. The semiconductor structure is characterized by the absence of gallium in one or more of these structural layers.

Abstract: A high extraction efficiency, light-emitting diode having a reflective submount and methods for forming the LED. A light-emitting region is disposed between a top contact and a conductive holder. The region extends beyond an area underlying the top contact. An omni-directional reflector is disposed between the light-emitting region and the conductive holder. According to one embodiment, the reflector comprises one or more electrically conductive contacts configured to correspond to an area beyond the area underlying the top contact. According to one embodiment, the reflector comprises a dielectric layer having a refractive index of between about 1.10 and 2.25, contacts extending through the reflector, and a reflective conductive film.

Abstract: A light-emitting semiconductor device includes a stack of layers including an active region. The active region includes a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof. A superstrate substantially transparent to light emitted by the active region is disposed on a first side of the stack. First and second electrical contacts electrically coupled to apply a voltage across the active region are disposed on a second side of the stack opposite to the first side. In some embodiments, a larger fraction of light emitted by the active region exits the stack through the first side than through the second side. Consequently, the light-emitting semiconductor device may be advantageously mounted as a flip chip to a submount, for example.

Abstract: There is provided is a semiconductor laser device capable of simplifying fabricating processes with a simple construction and easily mounting two semiconductor laser elements and a monitoring PD on a compact package and a wire bonding method for the semiconductor laser device. There are provided a stem 100 provided with a plurality of lead pins 121 through 124, a sub-mount 160 that is die-bonded onto the stem 100 and has its surface formed integrally with a monitoring PD 140 and two semiconductor laser elements 131 and 132 that are die-bonded onto the sub-mount 160 and have emission light monitored by the monitoring PD 140. A first bonding surface i.e. anode electrode 183 of the monitoring PD 140 and a second bonding surface i.e. end surface 123a of a lead pin 123 that is approximately perpendicular to the first bonding surface are wire-bonded to each other.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells. Bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction. Cuts are formed at positions of the plate lines near the bit line contacts. The active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.

Abstract: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of said light receiving portions. The first and third transfer electrodes of the first layer are alternately arranged in a charge transfer direction, and the adjacent two of the first and third transfer electrodes extend in parallel to each other between the light receiving portions. With this solid-state image pickup device, the accumulated charge capacity of each transfer region composed of the adjacent transfer electrodes for two-phases is equalized and the area of the light receiving portion is increased irrespective of variations in processed dimension between the transfer electrodes.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: A semiconductor device capable of reducing manufacturing cost and on-state resistance is provided by selectively disposing a plurality of active regions (AR) on a main surface of a stainless steel substrate (1) and disposing a trench gate (7) so as to bury the area between the active regions (AR). The active regions (AR) have a multilayer structure that is made up of a drain layer (2) containing antimony (Sb) as an n-type impurity in a relatively high concentration (n+), a polysilicon layer (3) overlying the drain layer (2) and containing a p-type impurity, and a source layer (4) overlying the polysilicon layer (3) and containing an n-type impurity in a relatively high concentration (n+).

Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor sidewall 40 of TiAlN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a. The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42) via the conductor sidewall 40, dummy lower electrode 33b, dummy cell plug 30 and local interconnect 21b. The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.

Abstract: A thermally-stable ferroelectric memory is provided. The ferroelectric memory includes a lower electrode and a ferroelectric layer formed on the top surface of the lower electrode such that a domain having a dielectric polarization is set as a bit. The thickness of the ferroelectric layer is not greater than the size of the bit. Accordingly, a non-volatile ferroelectric memory which is thermally stable is provided, thereby realizing a reliable memory which can store information at high speed and high density and has improved memory retention.

Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Abstract: A structure and a manufacture method of a DRAM device with deep trench capacitors are described. Each capacitor has a collar oxide layer with different height for electrical isolation and leakage reduction. Further, the DRAM device has strip-type active areas to improve some optical errors and thus reduce sufficiently the contact resistance of a buried strap film of a capacitor.

Abstract: An apparatus and fabrication process for a capacitor formed in conjunction with a dual damascene process. A bottom capacitor plate is electrically connected to an overlying first conductive via formed according to the dual damascene process. A top capacitor plate is connected to an overlying second conductive via. A dielectric material is disposed between the top and the bottom plates. The capacitor is formed by successively forming the bottom plate, the dielectric layer, and the top plate, patterning these layers as required after their formation. The first conductive via is formed over and electrically connected to the bottom plate and the second conductive via is formed over and connected to the top capacitor plate thereby providing for interconnection of the capacitor to other circuit elements by way of the dual damascene conductive runners connected to the conductive vias.

Abstract: Integrated circuit capacitor electrodes include a first conductive ring on a face of an integrated circuit substrate. A second conductive ring is provided on the first conductive ring opposite the substrate. A third conductive ring also is provided on the first conductive ring opposite the substrate. The third ring is located at least partially within the second ring. A conductive layer electrically connects the first, second and third rings. To form the electrodes, a first conductive layer is conformally deposited in the areas in which the electrodes will be formed and on a mold oxide layer. A first buffer dielectric layer is deposited on the first conductive layer. The first buffer dielectric layer and the first conductive layer are etched to separate nodes of the first conductive layer. Recessed portions are formed by further etching the first conductive layer.

Abstract: Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

Abstract: A flash memory having a charge-storage dielectric layer. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

Abstract: The nonvolatile semiconductor memory device includes a first conductivity-type semiconductor substrate where an active region is created, a floating gate which is formed on the first conductivity-type semiconductor substrate, and a control gate which is formed on the floating gate. A first conductivity-type high concentration diffused region is formed in the non-overlapping region of the floating gate in the active region.

Abstract: Nonvolatile memory devices, such as NROM devices that have an oxide-nitride-oxide (ONO) layer beneath at least one word line structure, and methods for making same, are disclosed. The ONO layer is formed on a substrate, followed by a patterned photoresist layer being formed on the ONO layer. The patterned photoresist layer then serves as an implanting mask to form at least one bit line in the substrate, followed by a material layer being formed on the substrate. The material layer is planarized until the photoresist layer is exposed, and the photoresist layer is then removed. A polymer layer is formed, using a dielectric resolution enhancement coating technique, on exposed surfaces of the material layer, with the polymer layer serving as an etching mask to define the top oxide layer and the nitride layer of the ONO layer. The polymer layer and the material layer are then removed.

Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.

Abstract: Power MOSFET devices provide highly linear transfer characteristics (e.g., Id v. Vg) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Abstract: The invention concerns a monolithically integrated semiconductor component, having a first charge carrier region of a first charge carrier doping; at least two second charge carrier regions with opposite charge carrier doping, patterned within the first charge carrier region at a spacing from one another, and third charge carrier regions, with the first charge carrier doping, patterned within the second charge carrier regions, a PN transition being short-circuited between the second charge carrier regions and the third charge carrier regions via a contacting area (source connection), the first charge carrier region being equipped with a contact (drain connection), and the second charge carrier regions being invertable by means of a contacting area in the region between the first charge carrier region and the third charge carrier region; and having at least one Schottky diode connected in parallel with the charge carrier region and the charge carrier region.

Abstract: A metal-oxide-semiconductor trench-gate semiconductor device in which a substantially intrinsic region (40) is provided below the gate trench (20), which extends from the base of the trench, substantially across the drain drift region (14) towards the drain contact region (14a), such that when the drain-source voltage falls during turn-on of the device its rate of decrease is higher. This reduces the switching losses of the device. The substantially intrinsic region (40) may, for example, be formed by implanting a region below the trench (20) with a damage implant.

Abstract: A method of operating a vertical DMOS transistor associated with a Schottky diode, the method including diverting current from flowing through a body-to-drain pn junction diode to flowing through the Schottky diode when a metallic source contact becomes more positive than a drain of the DMOS transistor by forward conduction voltage of the Schottky diode to reduce the amount of source current reaching the substrate and reducing operational characteristics of parasitic devices associated with the integrated circuit.

Abstract: A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region in such a manner as to maintain a high sustaining breakdown voltage of the high-voltage MOS transistor, which is based on a voltage of the source offset region and a voltage of a substrate region directly under a gate insulating film during operation of the high-voltage MOS transistor.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: A semiconductor device comprises at least a semiconductor layer including source and drain areas of a first conductive type and of a high impurity concentration and a channel area positioned between the source and drain areas, an insulation layer covering at least the channel area, and a gate electrode positioned close to the insulation layer. The channel area at least comprises a first channel area of a low resistance, positioned close to the insulation layer and having a second conductive type opposite to the first conductive type, and a second channel area of a high resistance, having the first conductive type and positioned adjacent to the first channel area.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A silicon oxide film 3′, 3″ is formed on each of the main surfaces of a first silicon single crystal substrate 1 (bond wafer) and a second silicon single crystal substrate 2 (base wafer), and the first and second silicon single crystal substrates are then brought into close contact so as to locate the silicon oxide films 3′, 3″ in between in an atmosphere of a clean air supplied through a boron-releasable filter, to thereby produce an SOI wafer 10. The second silicon single crystal substrate 2 employed herein comprises a silicon single crystal substrate having a bulk resistivity of 100 &OHgr;·cm or above. In thus produced SOI wafer 10, the silicon oxide film 3 has a depth profile of boron concentration in which the boron concentration reaches maximum at a thickness-wise position. This ensures manufacturing of SOI wafer excellent in high-frequency characteristics.

Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.

Abstract: A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

Abstract: A semiconductor device according to the invention of the present application comprises a first semiconductor layer, a first insulating layer formed over the first semiconductor layer, a second semiconductor layer formed over the insulating layer, a protective element formed over the second semiconductor layer, an electrode pad, and a plurality of series-connected through holes for connecting the electrode pad and the protective element. Thus, a surge voltage applied across a diffused resistor can be lightened and hence an oxide film placed below the diffused resistor can be prevented from destruction.

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.

Abstract: A process and apparatus directed to forming metal plugs in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into the active areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.