Patents Issued in December 2, 2004
  • Publication number: 20040238864
    Abstract: The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventors: Nicholas H. Tripsas, Matthew S. Buynoski, Uzodinma Okoroanyanwu, Suzette K. Pangrle
  • Publication number: 20040238865
    Abstract: A semiconductor device having a ferroelectric capacitor is provided. The semiconductor device includes an interlayer insulating layer, a ferroelectric capacitor and an insulating side wall film. The interlayer insulating layer is formed on a substrate including an integrated circuit and has a contact hole exposing a part of the integrated circuit. The ferroelectric capacitor is formed by depositing a first electrode layer, a ferroelectric layer and a second electrode layer on the interlayer insulating layer in this order. The insulating side wall film covers a peripheral edge section of the ferroelectric capacitor and is spaced from a peripheral edge section of the contact hole. A wiring layer electrically connects the second electrode layer to the integrated circuit through the contact hole.
    Type: Application
    Filed: November 4, 2003
    Publication date: December 2, 2004
    Inventor: Takahisa Hayashi
  • Publication number: 20040238866
    Abstract: A ferroelectric element manufacturing method includes the steps of forming a buffer layer, which also functions as a sacrificial layer, on a single crystal substrate, forming a ferroelectric film on the buffer layer, separating the ferroelectric film and the single crystal substrate, and arranging the ferroelectric film that was separated from the single crystal substrate on an optional substrate.
    Type: Application
    Filed: March 18, 2004
    Publication date: December 2, 2004
    Inventors: Setsuya Iwashita, Takamitsu Higuchi, Hiromu Miyazawa
  • Publication number: 20040238867
    Abstract: In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer insulating layer pattern over the BC pads. The exposed sidewall of the interlayer insulating layer pattern is covered with an etch stop spacer. Also, the top surface of the interlayer insulating layer pattern is covered with an etch stop layer. Then, a plurality of bit line contact or BC plugs are formed to contact the tops of the BC pads. A protruded region, which extends in one direction, is preferably formed on the sidewall of the contact plug.
    Type: Application
    Filed: May 24, 2004
    Publication date: December 2, 2004
    Inventor: Je-Min Park
  • Publication number: 20040238868
    Abstract: A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a semiconductor substrate and includes at least one conducting region. A patterned bit line structure is formed atop of, and electrically isolated from, the insulating region of the deep trench structure and atop of, but contacting at least part of, regions of the semiconductor substrate. Exposed portions of the semiconductor substrate are etched to form at least one isolation trench adjoining the deep trench structure using the patterned bit line structure as an etch mask. The isolation trench is filled with a dielectric material. A contact region to the conducting region of the deep trench structure is formed within the dielectric material of the isolation trench and is electrically isolated from the bit line structure.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Applicant: Infineon Technologies North America Corp.
    Inventors: Norbert Arnold, Venkatachalam C. Jaiprakash
  • Publication number: 20040238869
    Abstract: A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.
    Type: Application
    Filed: August 13, 2003
    Publication date: December 2, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Yi-Chen Chen, Yi-Nan Chen
  • Publication number: 20040238870
    Abstract: There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.
    Type: Application
    Filed: March 8, 2004
    Publication date: December 2, 2004
    Inventor: Yuichi Nakashima
  • Publication number: 20040238871
    Abstract: A semiconductor device has a substrate and an active area formed within the same includes a first non-planar metallization level which is formed on the substrate and is in contact with an active area. Further, a second planar metallization level is arranged above the substrate spaced apart from the first metallization level and is connected to the first metallization level via a through connection.
    Type: Application
    Filed: March 11, 2004
    Publication date: December 2, 2004
    Applicant: Infineon Technologies AG
    Inventors: Christian Herzum, Ulrich Krumbein, Christian Kuhn, Hans Taddiken
  • Publication number: 20040238872
    Abstract: Provided are a method for manufacturing a high k-dielectric oxide film, a capacitor having a dielectric film formed using the method, and a method for manufacturing the capacitor. A high k-dielectric oxide film is manufactured by (a) loading a semiconductor substrate in an ALD apparatus, (b) depositing a reaction material having a predetermined composition rate of a first element and a second element on the semiconductor substrate, and (c) forming a first high k-dielectric oxide film having the two elements on the semiconductor substrate by oxidizing the reaction material such that the first element and the second element are simultaneously oxidized. In this method, the size of an apparatus is reduced, productivity is enhanced, and manufacturing costs are lowered. Further, the high k-dielectric oxide film exhibits high dielectric constant and low leakage current and trap density.
    Type: Application
    Filed: March 11, 2004
    Publication date: December 2, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Bum-seok Seo, Yo-sep Min, Young-jin Cho
  • Publication number: 20040238873
    Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.
    Type: Application
    Filed: March 12, 2004
    Publication date: December 2, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeoung-Mo Koo, Hee-Seon Oh
  • Publication number: 20040238874
    Abstract: A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 2, 2004
    Inventors: Bomy Chen, Dana Lee
  • Publication number: 20040238875
    Abstract: A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Hiroaki Nakai
  • Publication number: 20040238876
    Abstract: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming such devices. Between forming a polysilicon layer and a metal layer, an interface reaction preventing layer is created. This reaction preventing layer prevents a buildup of highly resistive materials that would otherwise occur when creating conventional semiconductor devices, as well as having other functions.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Inventors: Sunpil Youn, Seong-Jun Heo, Sung-Man Kim, Chang-Won Lee, Ja-Hum Ku, Siyoung Choi
  • Publication number: 20040238877
    Abstract: An electrically programmable and erasable memory cell and an array of such memory cells have a semiconductor substrate of a first conductivity type. A first and second regions of a second conductivity type are in the substrate, spaced apart from one another. A channel region is formed between the first region and the second region for the conduction of charges. A floating gate is on a portion of the channel and insulated therefrom. The floating gate has a length in the channel direction with a first end and a second end with a tip located between the first end and the second end. A control gate is spaced apart from the floating gate by an insulation layer with the control gate having a portion aligned with the tip to receive charges emitted from the tip of the floating gate.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: Sreeni Maheshwarla, Pavel Klinger
  • Publication number: 20040238878
    Abstract: A technique capable of improving the reliability, more particularly, the data retention characteristics in a semiconductor integrated circuit device having a non-volatile memory using a nitride film as a charge storage layer is provided. A control gate electrode of selecting nMIS is formed on a first region of a substrate via a gate insulator, and a charge storage layer of the memory nMIS is formed on a second region via an insulator so that the hydrogen concentration of the charge storage layer is 1020 cm−3 or less. After forming an insulator, a memory gate electrode of the memory nMIS is formed on the second region via the insulators and the charge storage layer, and an impurity is implanted into the region adjacent to the selecting nMIS and the memory nMIS to form a semiconductor region constituting a drain region and a source region of the memory cell.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 2, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Hidenori Sato, Tsutomu Okazaki
  • Publication number: 20040238879
    Abstract: The present invention provides a semiconductor memory device comprising one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein
    Type: Application
    Filed: May 25, 2004
    Publication date: December 2, 2004
    Applicants: FUJIO MASUOKA, SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Endoh, Fujio Masuoka, Shinji Horii, Takuji Tanigami, Yoshihisa Wada, Takashi Yokoyama, Noboru Takeuchi
  • Publication number: 20040238880
    Abstract: A nonvolatile semiconductor memory device includes memory cells including a first MOS transistor, and a boosting circuit including a capacitor element. The first MOS transistor includes a charge accumulation layer and a control gate formed on the charge accumulation layer with an inter-gate insulating film interposed therebetween. The capacitor element includes a first and a second semiconductor layers, a capacitor insulating film, and a third semiconductor layer. The first and second semiconductor layers are formed on a semiconductor substrate and separated from each other. The capacitor insulating film is formed on the top and side of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers and is made of the same material as that of the inter-gate insulating film. The third semiconductor layer is formed on the capacitor insulating film and is isolated electrically from the second semiconductor layer.
    Type: Application
    Filed: August 19, 2003
    Publication date: December 2, 2004
    Inventors: Shigeru Nagasaka, Fumitaka Arai, Akira Umezawa
  • Publication number: 20040238881
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Application
    Filed: February 4, 2004
    Publication date: December 2, 2004
    Inventor: Yoshio Ozawa
  • Publication number: 20040238882
    Abstract: A semiconductor device manufacturing method comprises forming a pn column so that the pn column is designed to have a strip form in the section of the substrate and have a repetitive pattern of a p-conduction type and an n-conduction type on the substrate surface over an area where plural semiconductor devices having the same structure are formed in a semiconductor substrate, forming residual constituent elements of the plural semiconductor devices having the same structure in areas where the repetitive patterns are located while the pn column serves as apart of the constituent element of each semiconductor device, and dicing the individual semiconductor devices into chips from the area where the plural semiconductor devices having the same structure are formed.
    Type: Application
    Filed: April 6, 2004
    Publication date: December 2, 2004
    Applicant: DENSO CORPORATION
    Inventors: Mikimasa Suzuki, Yoshiyuki Hattori, Kyoko Nakashima
  • Publication number: 20040238883
    Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 2, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
  • Publication number: 20040238884
    Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.
    Type: Application
    Filed: October 3, 2003
    Publication date: December 2, 2004
    Inventors: Masahiro Tanaka, Shinichi Umekawa, Tadashi Matsuda, Masakazu Yamaguchi
  • Publication number: 20040238885
    Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicant: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
  • Publication number: 20040238886
    Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formned on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.
    Type: Application
    Filed: December 23, 2003
    Publication date: December 2, 2004
    Inventors: Jae-Gab Lee, Bong-Joo Kang, Beom-Seok Cho, Chang-Oh Jeong
  • Publication number: 20040238887
    Abstract: A field-effect transistor has a channel disposed on a substrate, a source electrode connected to a starting end of the channel, a drain electrode connected to a terminal end of the channel, an insulator disposed on an upper or side surface of the channel, and a gate electrode disposed on the upper or side surface of the channel with the insulator interposed therebetween. The channel is made of a plurality of carbon nanotubes.
    Type: Application
    Filed: July 15, 2004
    Publication date: December 2, 2004
    Inventor: Fumiyuki Nihey
  • Publication number: 20040238888
    Abstract: Lest gate lead lines 122 which are readily corrodable in atmosphere should be exposed on the cutting surface formed at the time of separating an inner display area, which includes gate and drain terminals, in an eventual TFT substrate 100 from static electricity protection lead lines 4 and static electricity protection elements 19, gate terminal electrodes 115 which is formed from corrosion-resistant ITO are cut apart in the vicinity of the gate and drain terminals 3 and 8.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 2, 2004
    Inventors: Kyounei Yasuda, Hiroaki Tanaka
  • Publication number: 20040238889
    Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.
    Type: Application
    Filed: June 30, 2004
    Publication date: December 2, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra Mouli, Lyle Jones
  • Publication number: 20040238890
    Abstract: A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semi-conductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
    Type: Application
    Filed: February 18, 2004
    Publication date: December 2, 2004
    Inventors: Pierre Fazan, Serguei Okhonin
  • Publication number: 20040238891
    Abstract: It is intended to provide a multi-layered structure for fabricating an ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics and an ohmic electrode obtained by using it. On a III-V compound semiconductor substrate such as an n+-type GaAs substrate, a non-single crystal semiconductor layer such as a non-single crystal In0.7Ga0.3As layer, a metal film such as a Ni film, a metal nitride film such as a WN film and a refractory metal film such as a W film are sequentially stacked by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is annealed at 500 to 600° C., e.g. 550° C. for one second by, e.g. RTA method to fabricate an ohmic electrode.
    Type: Application
    Filed: July 18, 1997
    Publication date: December 2, 2004
    Inventors: MITSUHIRO NAKAMURA, MASARU WADA, CHIHIRO UCHIBORI, MASANORI MURAKAMI
  • Publication number: 20040238892
    Abstract: An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.
    Type: Application
    Filed: March 13, 2003
    Publication date: December 2, 2004
    Inventors: Mu-Kyoung Jung, Young-Wug Kim, Hee-Sung Kang
  • Publication number: 20040238893
    Abstract: A semiconductor device for use in includes a base and emitter shorted by means of a surface electrode. The surface electrode of a vertical-type bipolar transistor in which a P-type epitaxial growth layer and a P-type semiconductor substrate form the collector is electrically connected to the drain electrode of a lateral MOSFET by means of a metal electrode wiring. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the vertical-type bipolar transistor and is limited to a voltage equal to or less than the breakdown voltage of the lateral MOSFET that was to be destroyed.
    Type: Application
    Filed: March 15, 2004
    Publication date: December 2, 2004
    Inventors: Hiroshi Tobisaka, Tatsuhiko Fujihira, Shin Kiuchi, Yoshiaki Minoya, Takeshi Ichimura, Naoki Yaezawa, Ryu Saitou, Shouichi Furuhata, Yuichi Harada
  • Publication number: 20040238894
    Abstract: A protection element comprises a ring-shape gate electrode, an N+ drain region inside the ring-shape gate electrode, an N+ source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a through-hole, and the drain region is connected to an external pad. The shield plate electrode is connected to ground or to a power supply. Element isolation is achieved by the shield plate electrode, without forming a LOCOS or other element isolation oxide layer. By this means, blocking of thermal conduction by an oxide layer can be avoided to improve the heat dissipation and ESD resistance of the protection element.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 2, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20040238895
    Abstract: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 2, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Akiyoshi Mutou
  • Publication number: 20040238896
    Abstract: A semiconductor device, includes a semiconductor substrate; a first p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode; and a first n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode. The gate insulation layer of the first p-MOS transistor is of a silicon nitride oxide layer.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventor: Marie Mochizuki
  • Publication number: 20040238897
    Abstract: A semiconductor device comprising an active area of a MOSFET which is separated by an element isolation area on a semiconductor substrate, at least one gate electrode provided over the active area, and at least one source/drain contact formed on a surface of the active area at one side of the gate electrode, wherein the gate electrode has a shape to vary so that a gate length decreases with increasing a distance from a position of the source/drain contact along the gate electrode.
    Type: Application
    Filed: November 14, 2003
    Publication date: December 2, 2004
    Inventor: Amane Oishi
  • Publication number: 20040238898
    Abstract: The gate electrode of a high-voltage transistor having a high breakdown voltage is formed from a polysilicon layer having a larger average grain size, so that depletion of the gate electrode easily occurs. By utilizing this depletion, the electrical effective film thickness required by the gate dielectric film of the transistor can be increased. In contrast, the gate electrode of a high-performance transistor required to have a high speed and a large drive current is formed from a polysilicon layer having a smaller average grain size, so that depletion of the gate electrode hardly occurs. Accordingly, the electrical effective film thickness of the gate dielectric film of the transistor can be maintained at a small value.
    Type: Application
    Filed: May 5, 2004
    Publication date: December 2, 2004
    Applicant: Sony Corporation
    Inventor: Yuko Ohgishi
  • Publication number: 20040238899
    Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.
    Type: Application
    Filed: May 12, 2004
    Publication date: December 2, 2004
    Inventors: Helmut Fischer, Jens Egerer
  • Publication number: 20040238900
    Abstract: In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor elements of a second element formation portion (steady stress region) are electrically driven. Therefore, the second element formation portion in the peripheral circuit formation portion is located away from an outer STI region so as to be hardly affected by compressive stress.
    Type: Application
    Filed: April 6, 2004
    Publication date: December 2, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masaru Yamada, Yasutoshi Okuno
  • Publication number: 20040238901
    Abstract: The electronic device with a layer of mesoporous silica can be obtained by applying a composition comprising alkoxysilane, a surfactant and a solvent onto a substrate, and by subsequently removing the surfactant and the solvent. The customary dehydroxylation treatment is not necessary if the composition contains a mixture of tetra-alkoxysilane, particularly teatraethoxyorthosilicate (TEOS), and an alkyl-substituted alkoxysilane, particularly a phenyl-substituted, methyl-substituted or ethyl-substituted trialkoxysilane. If both silanes are present in a molar ratio of approximately 1:1, a layer with a dielectric constant of 2.5 or less is obtained.
    Type: Application
    Filed: March 8, 2004
    Publication date: December 2, 2004
    Inventors: Abraham Rudolf Balkenende, Femke Karina De Theije, Jan Cornelis Kriege
  • Publication number: 20040238902
    Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is. patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Inventor: Hsiao-Ying Yang
  • Publication number: 20040238903
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Application
    Filed: July 2, 2004
    Publication date: December 2, 2004
    Applicant: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20040238904
    Abstract: The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 2, 2004
    Inventors: Luigi Colombo, James J. Chambers, Antonio L. P. Rotondaro, Mark R. Visokay
  • Publication number: 20040238905
    Abstract: The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.
    Type: Application
    Filed: May 18, 2004
    Publication date: December 2, 2004
    Applicant: Lucent Technologies Inc.
    Inventors: Yuan Chen, Feng Li, Yi Ma, Kurt G. Steiner
  • Publication number: 20040238906
    Abstract: A static neutralizing roll follower includes a static charge dissipating device on a carrier movably held by a support. Sensors follow the changing diameter of a roll, and a control unit processes signals from the sensor to operate a drive mechanism to move the carrier with respect to the changing roll diameter. Consistent spacing is maintained between the dissipating device and the roll surface.
    Type: Application
    Filed: February 17, 2004
    Publication date: December 2, 2004
    Inventors: Scott R. McClintock, Michael F. Soffa
  • Publication number: 20040238907
    Abstract: Nanoelectromechanical switch systems (NEMSS) are provided that utilize the mechanical manipulation of nanotubes. Such NEMSS may realize the functionality of, for example, automatic switches, adjustable diodes, amplifiers, inverters, variable resistors, pulse position modulators (PPMs), and transistors. In one embodiment, a nanotube is anchored at one end to a base member and coupled to a voltage source that creates an electric charge at the tip of the nanotube's free-moving-end This free-moving end may be electrically controlled by applying an additional electric charge, having the same (repelling) or opposite (attracting) polarity as the nanotube, to a nearby charge member layer. A contact layer is located in the proximity of the free-moving end such that when a particular electric charge is provided to the nanotube (or charge member layer), the nanotube electrically couples with the contact layer.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventors: Joseph F. Pinkerton, John C. Harlan, Jeffrey D. Mullen
  • Publication number: 20040238908
    Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 2, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventor: Sakae Hashimoto
  • Publication number: 20040238909
    Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.
    Type: Application
    Filed: August 29, 2003
    Publication date: December 2, 2004
    Inventors: Suan Jeung Boon, Yong Poo Chia, Min Yu Chan, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua
  • Publication number: 20040238910
    Abstract: A transparent touch panel is structured by forming connecting layers that contain conductive metal powder dispersed in a resin, on ends of wiring patterns on a wiring board to which upper electrodes and lower electrodes are to be bonded. This structure can provide a transparent touch panel that ensures bonding of upper and lower substrates and the wiring board and stable electrical connection.
    Type: Application
    Filed: May 20, 2004
    Publication date: December 2, 2004
    Inventors: Shoji Fujii, Toshiharu Fukui, Tetsuo Murakami
  • Publication number: 20040238911
    Abstract: A photodetector array made in monolithic form, in which transistors are formed in a semiconductor substrate coated with several metallization levels and photodiodes are formed above a last metallization level, each photodiode having an upper region of a first conductivity type common to all photodiodes and an individual lower region forming a junction with the upper region in contact with a metallization of the last level, wherein each lower region is separated from the neighboring lower regions by an insulating material and is connected to the metallization through a via formed in at least one insulating layer.
    Type: Application
    Filed: May 19, 2004
    Publication date: December 2, 2004
    Inventor: Francois Roy
  • Publication number: 20040238912
    Abstract: The present invention relates to a GaN-based heterostructure photodiode comprising a P type layer, an N type layer, and an activity layer between the P type layer and the N type layer. The P type layer, the N type layer and the activity layer are made of GaN-based composition, and the activity layer is doped with borons so as to modulate the band gap between the P type layer and the N type layer. Therefore, the breakdown voltage can be increased and the light receiving ability can be promoted so that the photodiode to be a light receiving element can has a better performance for light detection.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Inventors: Mu-Jen Lai, Chiung-Yu Chang
  • Publication number: 20040238913
    Abstract: A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Inventors: Tae-Hun Kwon, Choel-Joong Kim, Suk-Kyun Lee