Abstract: Disclosed herein are an inspection apparatus for circuit board and an inspection process for circuit board, by which an anisotropically conductive elastomer sheet is prevented from causing trouble prematurely, long service life is achieved, stable electrical connection is attained to all electrodes to be inspected, and inspection can be conducted with high reliability even when a circuit board has projected electrodes to be inspected arranged at a small pitch, and the projected height of the electrodes to be inspected varies, and a wiring board for connection used in the inspection apparatus for circuit board.

Abstract: There is provided a semiconductor testing apparatus having a test head body having signal modules for processing the test signals, a plurality of connection cables electrically connected with the signal module and having connector pins at their ends, a plurality of types of connector housings for holding a plurality of connector pins, an interface plate having a plate body disposed on one face of the test head body and a plurality of connector blocks removably attached respectively to the plate body while storing a plural number of connector housings of either type among the plurality of types and a performance board for removably holding the electronic device and for electrically connecting the plurality of connector pins to the electronic device by being attached to the interface plate.

Abstract: A handling unit includes a frame, at least one arrangement module, and at least one chip carrier. The frame has at least one recess for the interchangeable mounting of at least one of the arrangement modules. The arrangement module has at least one receptacle for the mounting of at least one chip carrier. The chip carrier has at least one chip seat for holding a chip.

Abstract: An communication system having an on-chip transmitter circuit connected to a channel via an output connection pad and an on-chip receiver circuit connected to the channel via an input connection pad, wherein the on-chip transmitter circuit includes an equalizing output impedance and the on-chip receiver circuit includes an equalizing input impedance. The equalizing output impedance of the on-chip transmitter circuit is adapted to equalize the pad-capacitance of the output connection pad, whereas the equalizing input impedance of the on-chip receiver circuit is adapted to equalize the pad-capacitance of the input connection pad.

Abstract: In an integrated circuit implemented on a circuit board, output lines of an output circuit that outputs a logic signal are connected to the circuit board by soldering of a leadless terminal that cannot be seen as being implemented. A fault diagnosing unit tests an output voltage of the leadless terminal with respect to the circuit board as being implemented to determine whether the output voltage is a normal voltage or an abnormal voltage.

Abstract: An electromagnetic counter includes an electromagnetic counting mechanism in a frame, a plurality of number wheels at least one of which is configured to rotate through a predetermined angle in response to rotation of an electromagnetically motivated anchor, wherein each of the number wheels is disposed proximate a window provided in the front of a frame enclosing cover to form a readable display section. A mounting board supports a light emitting diode for illuminating the display section, and a wiring pattern that supplies electrical power to the light emitting diode. A reflective surface is provided on at least one of an internal surface of the cover member to reflect light from the light emitting diode toward the numbered wheels, the periphery of one or more of the numbered wheels, and indicia formed in the numbered wheels, to render the number wheels readily readable when illuminated by the light emitting diode.

Abstract: A contact-making apparatus for electrical connection of a unit under test to an electrical test device, having a plurality of electrical contacts which are associated with at least one holding element. The contact-making apparatus and preferably the holding element thereof, is provided with at least one marking which is in a defined position with respect to at least one of the contacts. The marking is detected for alignment of the apparatus and the unit. A corresponding method of use and a method of manufacture are also disclosed.

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Abstract: A lighting device includes a light-guiding rod and a light-emitting unit. The light-guiding rod includes a transparent hollow housing, the housing has two open ends and two insulating plugs for closing corresponding said two open ends. The light-emitting unit includes a transparent light-guiding plate, at least one light-emitting diode, a mounting substrate, and a plurality of conductive bumps. The transparent light-guiding plate is disposed in said housing. At least one light-emitting diode has a light-emitting surface; the surface is attached to a lower surface of said light-guiding plate. The mounting substrate has a wiring surface and a plurality of electric traces. A plurality of conductive bumps for connecting electrically said electric contacts of said at least one light-emitting diode to corresponding said electric traces in such a manner that said at least one light-emitting diode is mounted on said wiring surface of said mounting substrate.

Abstract: Disclosed is a picture quality testing apparatus and method of a liquid crystal display which can measure at least any one of gray inversion and color shift. An apparatus for testing the picture quality of a liquid crystal display includes a liquid crystal display for displaying a test pattern, an image pickup device for photographing the test pattern of the liquid crystal display, a measurer for measuring the transmittance of the test pattern photographed by the image pickup device, and a rotating means for rotating at least one of the liquid crystal display and the image pickup device while the image pickup device photographs the test pattern.

Abstract: An organic light emitting display array substrate on which display panels can be simultaneously tested on a substrate basis and a method of testing the display panels on the substrate is disclosed. In one embodiment, the organic light emitting display array substrate includes a plurality of panels formed on the substrate, a first wiring line group formed on each of the panels in a first direction, a pad unit formed on each of the panels to be electrically connected to the first wiring line group, a first power source line formed on each of the panels in the first direction to receive a first power source, and a second wiring line group formed on each of the panels in a second direction. The first wiring line group is electrically connected to a scan driver formed in each of the panels. The substrate can reduce test time and improve test efficiency. In addition, it can prevent a voltage drop and/or a signal delay.

Abstract: An exemplary hi-pot testing device (2) includes a testing table (20), a transfer table (21) movably supported on the testing table and configured to support a product (200) to be tested, and a hi-pot testing signal generator (27) under the testing table. The transfer table includes a top surface and a bottom surface, a first current input portion (23) at the bottom surface (202), a first power connector (234) embedded at the top surface, and electrically connecting to the first current input portion, and a first signal cable connector (25) arranged on the top surface. The first signal cable connector is grounded and configured to enable the product to be grounded. The hi-pot testing signal generator is configured to electrically connect with and electrically disconnect from the first current input portion of the transfer table.

Abstract: A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: A power supply trim control signal is produced by integrating differences between monitored and target values of the output voltage of a power supply. Register storage requirements are reduced by producing the target value from a nominal voltage value and one of a plurality of margin offsets selected in accordance with control data. The control data also selects between open and closed loop trim control. Stability is enhanced by changing the target value slowly in response to any change in the control data.

Abstract: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

Abstract: A driver circuit for outputting an output signal corresponding to an input signal given to the driver circuit, includes a voltage generating unit for outputting a basic output voltage corresponding to the input signal, a first buffer circuit for outputting an output voltage corresponding to the basic output voltage outputted by the voltage generating unit, a second buffer circuit, of which power consumption is larger than the first buffer circuit, for generating and outputting a voltage corresponding to the output voltage as the output signal, a simulating circuit including a simulating buffer circuit for generating a simulated voltage corresponding to the basic output voltage outputted by the voltage generating unit, the simulating buffer circuit having substantially the same characteristic as that of the first buffer circuit, and a controlling unit for controlling the basic output voltage outputted by the voltage generating unit based on the simulated voltage.

Abstract: A divider circuit receives an input signal and at least one phase adjustment control signal and supplies a phase adjustable output signal. The divider circuit includes a state machine providing N states, with no phase adjustment, to provide as the output signal the input signal divided by N. Each state of the state machine lasts for one period of the input signal. The divider circuit adjusts the phase of the output signal by changing the number of states that occur in one period of the output signal. In response to a control signal to decrement the phase of the output signal, the state machine skips at least one state for one period of the output signal. In response to a control signal to increment the phase of the output signal, the state machine inserts one or more states for one period of the output signal.

Abstract: A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The control signal may be based on at least one control signal coupled to tune a controllable oscillator. The control signal may be based on a frequency of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on the voltage swing of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on an output of the frequency divider circuit.

Abstract: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

Abstract: A power-on reset circuit has a reset starting circuit, a reset finishing circuit, and a latch circuit. The reset starting circuit generates a reset starting signal in response to a power voltage. When the power voltage reaches a predetermined reset finishing voltage, the reset finishing circuit generates a reset finishing signal. The latch circuit generates a power-on reset signal having a first state and a second state. In response to the reset starting signal, the latch circuit causes the power-on reset signal to transition to the first state. In response to the reset finishing signal, the latch circuit causes the power-on reset signal to transition to the second state.

Abstract: The present invention provides a system, apparatus and method for recovering a client signal clock. The present invention is able to more effectively remove jitter within a clock signal by providing a phase shifting element in the feedback of a PLL system to compensate for sudden changes in an input reference clock. The PLL system provides flexible clock recovery so that it can accommodate various payload types because it extracts a client clock signal independent of a corresponding justification count number.

Abstract: A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between a data signal and a plurality of clock signals to generate two proportional control signal and two integration control signal for respectively controlling the first charge pump and the second charge pump to generate a first current and a second current. The proportional load circuit and the integration load circuit respectively receive the first current and the second current to output a proportional voltage and an integration voltage. The voltage control oscillating circuit adjusts the phase and frequency of the plurality of clock signals in response to the proportional voltage and the integration voltage.

Abstract: A delay locked loop circuit is disclosed.

Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.

Abstract: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.

Abstract: A static latch (80) transfers input data (D) and its complement (DN) to an output terminal (100) and a complementary output terminal (98) when enabled and maintains the input data (D, DN) on the output terminals (100,98) when not enabled. The input data (D, DN) gate second and third transistors (86,88), the enable signal (G) gates a first transistor (90), such that when the latch (80) is enabled, the first and second transistors (98,86) and the first and third transistors (90,88) transfer the input data (D) and its complement (DN) to the specified output terminals (100,98) and when the latch (80) is disabled disconnects the input terminals (92,94) to maintain the current output values (Q,QN).

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

Abstract: A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors.

Abstract: An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude modulation-free oscillation leading to the generation of jitter free high frequency clock signals.

Abstract: A system and method are provided for producing two asymmetric duty cycle clock phases as outputs, where the duration of the active phase may be varied to generate clock signal having an asymmetric duty cycle. A circuit configured according to the invention includes a monostable clock generator configured to produce an asymmetric duty cycle clock phase from a reference clock input, a delayed phase generator configured to produce two clock phases whose falling edges are delayed with respect to the input signals, and a second phase generator configured to produce a second asymmetric duty cycle clock phase. The phase may be programmable by including a variable resistor network that can be varied in response to control signals.

Abstract: A variable resistance circuit includes a PIN diode circuit which adjusts an RF resistance for PIN diodes according to a control voltage, a first means which level-shifts one control voltage by a level shift circuit and applies a non-linear characteristic to the so level-shifted control voltage using a zener diode characteristic by a zener diode circuit, a second means which applies a voltage offset to the other control voltage by a weighting circuit, and an adding circuit which adds respective output voltages of the first means and the second means. When the output of the adding circuit is applied to the PIN diode circuit, the shift voltage of the level shift circuit, the zener characteristic of the zener diode circuit and the voltage offset of the weighting circuit are selected and adjusted to set the value of the RF resistance of the PIN diode circuit so as to change substantially linearly with respect to a change in control voltage.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: A level shifter circuit includes a level shifter unit and a latch unit. The level shifter unit receives two complementary input signals and converts the voltage levels of two complementary input signals. The latch unit latches the state of two output nodes before the low voltage supply is turned off. On condition that the low voltage supply is off, the level shifter circuit avoids current drainage and ensures the voltage level of the output. The invention has the advantages of small circuit size and being easy to design.

Abstract: A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current sources. The steering current generator has four current outputs and a switching matrix is provided to switch the current from the summing nodes to first and second selected ones of those outputs. The switching matrix is also connected to switch bleed currents to the other two of the current outputs.

Abstract: A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state.

Abstract: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.

Abstract: A switched current temperature sensing circuit comprises a BJT arranged to conduct a forced emitter current IE of the form Ifixed+(Ifixed/?), such that the base current is given by Ifixed/? and the collector current is given by Ifixed+(Ifixed/?)?(Ifixed/?)=Ifixed. Base current Ifixed/? is mirrored to the emitter, and a current source provides current Ifixed, which is switched between at least a first value I and a second value N*I such that the BJT's base-emitter voltage has a first value Vbe1 when Ifixed=I and a second value Vbe2 when Ifixed=N*I, such that: ?Vbe12=Vbe1?Vbe2=(nFkT/q)(ln N), where nF is the BJT's emission coefficient, k is Boltzmann's constant, T is absolute temperature, and q is the electron charge.

Abstract: A charge pump for generating an arbitrary voltage level includes “M” pieces of pump units PUi and “M+1” pieces of first switches Sj. The pump unit PUi includes a first terminal Ni,1 coupled to a reference voltage Vi,1, a second terminal Ni,2 coupled to a reference voltage Vi,2, a third terminal Ni,3, a fourth terminal Ni,4 and at least one capacitor Ci. Ci is charged by Vi,1 and Vi,2 during a first period, and a voltage is provided from Ni,4 by Ci according to a voltage at Ni,3 during a second period. The first switch Sj is adapted for electrically connecting the first terminal and the second terminal during the second period. The first and second terminals of Sk is coupled to Nk?1,4 and Nk,3, respectively. The first terminal of Si receives the input voltage and the second terminal of SM+1 outputs the output voltage.

Abstract: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.

Abstract: In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to an integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments.

Abstract: A bandgap reference voltage generating circuit includes a proportional to absolute temperature (PTAT) voltage generating means generating a PTAT voltage. A complementary to absolute temperature (CTAT) voltage generating means generates a CTAT voltage. A temperature coefficient determining means interconnects the PTAT voltage generating means and the CTAT voltage generating means.

Abstract: A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a second switch triggered by a backward trigger signal, a first operational amplifier generating a first drive signal while the first and second switches are on, a first transistor switch triggered to be on by a first drive signal to provide a current source loop, a third switch triggered by a forward trigger signal, a fourth switch triggered by a backward trigger signal, a second operational amplifier generating a second drive signal while the third and fourth switches are on, and a second transistor switch triggered to be on by a second drive signal to provide a current sink loop.

Abstract: A reference voltage generating circuit for outputting a reference voltage having a level varying depending on the operation mode of a semiconductor device is disclosed.