Abstract: OFF current of a TFT is reduced. There is provided a semiconductor device includung: a substrate; a shielding film formed so as to be in contact with the substrate; a planarization insulating film formed on the substrate so as to cover the shielding film; and a semiconductor layer formed so as to be in contact with the planarization insulating film. The semiconductor device is characterized in that the shielding film overlaps the semiconductor layer with the planarization insulating film sandwiched therebetween, and that the planarization insulating film is polished by CMP before the semiconductor layer is formed.

Abstract: Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1×B?A?13×B.

Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.

Abstract: With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern.

Abstract: A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor trench, removing the dummy gate to provide a gate trench, forming a dielectric layer in the capacitor trench and the gate trench, and forming a metal layer over the dielectric layer in the capacitor trench and the gate trench.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered insulator layer is then removed at the trench wall in order to define the region of the buried strap contact area. A liner layer is subsequently deposited in order to cover the inner capacitor electrode layer in the trench and the uncovered trench wall and thus to form a barrier layer. A spacer layer with the material of the inner electrode layer is then formed on the liner layer at the trench wall. Finally, the uncovered liner layer is removed above the inner electrode layer and the trench is filled with the material of the inner electrode layer in order to fabricate the buried strap contact.

Abstract: A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

Abstract: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided. The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and bottom of the opening. A dielectric layer is formed on the lower electrode, and an upper electrode is disposed on the dielectric layer. The dielectric layer preferably comprises a high k-dielectric layer such as tantalum oxide. The disclosed method comprises forming an ILD pattern with an opening that exposes a portion of a semiconductor substrate forming an optional silicide pattern on the exposed substrate, forming a lower electrode on the inner wall of the opening, and sequentially forming a dielectric layer and an upper electrode on the resulting structure.

Abstract: The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

Abstract: Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films 12 and 22, floating gates 14 and 24, dielectric films 16 and 26, control gates 18 and 28 on first and second memory cell areas 10 and 20 formed mutually adjacent to each other on a semiconductor substrate 30, a plurality of impurity area formation steps of forming sources and drains 32, 34, 36 and 38 on the first and second memory cell areas 10 and 20, and forming a connecting area 40 capable of forming an electric connection between one 32 of the source and drain of the first memory cell area 10 and one 36 of the source and drain of the second memory cell area 20.

Abstract: Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

Abstract: A vertical split gate memory cell of silicon-oxide-nitride-oxide-silicon (SONOS) type formed in a trench of a semiconductor substrate includes a first doping region, a second doping region, a conductive line, a conductive plug, a first insulating layer and a second insulating layer, wherein the conductive line and conductive plug serve as a select gate and a control gate of the vertical split gate memory cell, respectively. The first doping region of a first conductive type is underneath the bottom of the trench, whereas the second doping region of the first conductive type is beside the top of the trench. The conductive line serving as the select gate is formed in the bottom of the trench and in operation relation to the first doping region. The first insulating layer is between the conductive line and the first doping region for insulation. The conductive plug is formed above the conductive line, and insulated from the conductive line by the second insulating layer.

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Abstract: Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing a partial surface of the substrate. A spacer is formed surrounding both sidewalls of the mask film, and a recess is formed in the substrate. A gate oxide film, a gate electrode, a gate insulation film, a gate spacer, and source and drain regions are also formed. A resultant transistor structure has a small open critical dimension that improves process margin and provides uniformity to the recess depth, and removes a requirement that a bottom critical dimension of a subsequently formed self-aligned contact should be small. Degradation of the gate oxide film and increases in leakage current may also be prevented.

Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

Abstract: A method (and resulting structure) of forming a semiconductor device, includes implanting, on a substrate, a dopant and at least one species, annealing the substrate, the at least one species retarding a diffusion of the dopant during the annealing of the substrate.

Abstract: In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the width of the LDD can be defined by the geometry of the inclined planes.

Abstract: A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.

Abstract: An active type tunable wavelength optical filter having a Fabry-Perot structure is disclosed. A tunable wavelength optical filter which comprises a lower mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion; an upper mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion and which is spaced away from the lower mirror by a predetermined distance; a connecting means for connecting and supporting the lower mirror and the upper mirror to a semiconductor substrate; and electrode pads for controlling the gap between the lower mirror and the upper mirror by an electrostatic force and the method of manufacturing the same are provided.

Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

Abstract: A ferroelectric element manufacturing method includes the steps of forming a buffer layer, which also functions as a sacrificial layer, on a single crystal substrate, forming a ferroelectric film on the buffer layer, separating the ferroelectric film and the single crystal substrate, and arranging the ferroelectric film that was separated from the single crystal substrate on an optional substrate.

Abstract: The invention relates to an object (1) that is cut by means of a laser and a water beam and to further processing of the cut material. The object is glued on a carrier (3) that is provided with an adhesive and can be transparent for the radiation used in the water beam (7). The carrier can be a solid body and preferably a fibrous mat (3). Said body or mat is penetrated by the water beam. The object (1) or the cut material thereof is held on the carrier (3) before, during and after cutting through in such a way that said object or material does not change position. In a preferred embodiment, a silicon wafer is used as the object because of the high cutting exactness to be obtained. Other materials can also be used.

Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.

Abstract: A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract: A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gates. A first etch forms the gate structure. Following removal of the photoresist, a second etch completely removes the BARC. The silicon dioxide layer can be removed by a subsequent wet etch with HF.

Abstract: The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a semiconductor substrate (220). The process further includes forming a polysilicon layer (225) over the metal layer (210) and creating a protective layer (230) over the polysilicon layer (225). The process also includes placing an inorganic anti-reflective coating (235) over the protective layer (230). Other embodiments include a metal gate stack precursor structure (100) and a method of manufacturing an integrated circuit (300).

Abstract: A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-Sic is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30 s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.

Abstract: A method for dispersing and fixing particles on the bumps of a chip using an electrophoresis technology is provided. The particles and chip bumps are processed to carry charges by applying chemical bonding between metal and thiol with electric charges. The chip is placed in a reactor with a solution along with the conductive particles. The conductive particles are then migrated and fixed to the bonding locations on the bumps of a chip through an electrophoresis procedure. For conductive particles not carrying charges, they can sink naturally to the surface of chip bumps due to their higher density than water in the solution. An electroplating procedure is then applied to fix the conductive particles onto the bump.

Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Abstract: A method for fabricating a semiconductor device that prevents the occurrence of bowing and thickness reduction in a dual damascene method. As shown in FIG. 2(B), silicon nitride etching is performed on a semiconductor device in process of fabrication which has a section shown in FIG. 2(A). As a result, part of a copper film is oxidized and changes into oxide. Moreover, a CFx deposit is formed on it. By performing organic insulating film etching by the use of hydrogen plasma in FIG. 2(C), however, the oxide is deoxidized to copper and the CFx deposit is converted into a volatile compound and is removed.

Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).

Abstract: The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other embodiments are formed, at least in part, of boron nitride. Some such embodiments include a moisture barrier film that includes oxygen and/or carbon. Preferred embodiments of the copper diffusion barrier maintain a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.

Abstract: Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: There is provided a process for producing an integrated circuit, wherein not only can conductive fine particles be deposited efficiently and densely in minute wiring channels and connecting holes but also a circuit of low wiring resistance and high density can be formed and wherein a high-degree integration can be achieved to thereby bring about an economic advantage. In particular, there is provided a process for producing an integrated circuit, comprising coating a substrate provided with wiring channels with a coating liquid for integrated circuit formation containing conductive fine particles to thereby form an integrated circuit on the substrate, wherein the coating liquid for integrated circuit formation while being exposed to ultrasonic waves is applied to the wiring channels.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: The present invention is relates to a polishing method for polishing a semiconductor wafer (W) by pressing the semiconductor wafer (W) against a polishing surface (10) with use of a top ring (23) for holding the semiconductor wafer (W). A pressure chamber (70) is defined in the top ring (23) by attaching an elastic membrane (60) to a lower surface of a vertically movable member (62). The semiconductor wafer (W) is polished while a pressurized fluid is supplied to the pressure chamber (70) so that the semiconductor wafer (W) is pressed against the polishing surface (10) by a fluid pressure of the fluid. The semiconductor wafer (W) which has been polished is released from the top ring (23) by ejecting the pressurized fluid from an opening (62a) defined centrally in the vertically movable member (62).

Abstract: Biased plasma etch processes incorporating H2 etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Abstract: The invention provides a method of assaying at least one element in a material including silicon. The method includes the steps of decomposing a portion of the material with an etching agent to form a solution containing hexafluorosilicic acid and at least one element to be assayed, heating the solution to a temperature sufficient to transform a substantial portion of the hexafluorosilicic acid into silicon tetrafluoride and to cause at least some of the silicon tetrafluoride to evaporate, such that a solution for assaying is obtained in which the silicon content is reduced while and the elements to be assayed are conserved; and assaying at least one element contained in the solution. The invention is applicable to the field of manufacturing substrates or components for optics, electronics, or optoelectronics, and in particular to the field of quality control.