Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two regions. A first boosting voltage is applied to the first region of the string while a second larger boosting voltage is applied to the second region. The first region includes the addressed row or selected word line for programming. The boosting voltages are applied to the NAND strings of a block while the NAND strings are being inhibited from programming. In this manner, the second boosting voltage can be made larger without inducing program disturb on the memory cells receiving the larger boosting voltage. The boosted voltage potentials of the NAND string channels are trapped within the first region by lowering the boosting voltage on one or more bounding rows. The second boosting voltage is then lowered and data is applied to the bit lines of the NAND strings to select the appropriate strings for programming.

Abstract: A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

Abstract: A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.

Abstract: For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality of sense amplifier latches. The initial row of memory cells is deactivated while the latched data is retained in the sense amplifier latches. Another row of memory cells is identified in accordance with a predetermined row addressing sequence for the test data topology. The other row of memory cells is activated to write the retained latched data to the other row.

Abstract: Active control of body contacts in memory devices can provide variable substrate voltages during device operation. The body contacts can be used to adjust the body bias of switches in activated memory cells, while maintaining the body bias of switches in inactive memory cells. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line (“WL”) is activated.

Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.

Abstract: A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

Abstract: A method and an apparatus for restoring defective memory cells are provided. The apparatus includes memory, a memory scan controller, which scans the memory to see if the memory is defective when a system starts operating and transmits resulting defect information to a memory controller, and the memory controller, which converts an external address applied from a system controller into an internal address for accessing the memory and replaces a defective cell in the memory with spare memory provided therein so that when a request for access to the defective cell is issued by the system controller, spare memory, rather than the defective cell, can be accessed by the system controller.

Abstract: A non-volatile memory wherein bad columns in the array of memory cells can be removed. Substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. The bad column can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.

Abstract: A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an isolation controller which is enabled in response to the enabling signal, and outputs a control signal to periodically isolate the bridge-formed cell block from a sense amplifier array for a predetermined period in a standby mode in response to a periodic signal enabled at intervals of a predetermined time.

Abstract: Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.

Abstract: A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.

Abstract: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Abstract: Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.

Abstract: A random access memory includes a logic circuit coupled to a power supply of a column having a memory cell. The logic circuit adjusts the supply voltage for the memory cell in the column in accordance with a control signal. A control circuit is coupled to the logic circuit, which generates the control signal in accordance with an operation type and whether the column is selected, such that the logic circuit selects the supply voltage in accordance with the control signal. The cell may include high mobility devices to improve performance.

Abstract: Voltage regulator circuitry is provided that produces a stable programming-voltage on a programmable integrated circuit. The programmable integrated circuit has programming control circuitry that provides logic-level programming signals. A controllable voltage supply increases the strength of the logic-level programming signals to produce programming-voltage-level programming signals. The programming-voltage-level programming signals are used to program programmable elements such as flash transistors on the programmable integrated circuit. A temperature-insensitive diode-based voltage feedback circuit is connected to the output of the controllable voltage supply. The voltage feedback circuit provides a corresponding feedback voltage to the controllable voltage supply that the controllable voltage supply used to stabilize the magnitude of the programming-voltage-level programming signals.

Abstract: A power supply for on-chip memory on an integrated circuit powered by a voltage source includes an on-chip logic circuit, a voltage identification bus and an on-chip variable voltage regulator. The on-chip logic circuit receives power from an off-chip variable power supply and generates a voltage identification signal that provides control information regarding a desired current state of the off-chip variable power supply. The voltage identification bus receives the voltage identification signal from the on-chip logic circuit. The on-chip variable voltage regulator receives power from the voltage source. The on-chip voltage regulator is controlled by an on-chip voltage regulator control logic circuit that is in communication with the voltage identification bus.

Abstract: The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

Abstract: A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.

Abstract: A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

Abstract: A memory apparatus for supporting a multiprocessor function enables data of different characteristics to be stored in one memory, thereby reducing the area of on the system board and decreasing delay margins on the data bus. The memory apparatus has an instruction memory unit arranged to be included in one memory chip and at least one data memory unit. The instruction memory unit includes cell array blocks having nonvolatile ferroelectric c stores instruction information required for operating a central processing unit of a system. The data memory unit is connected to the central processing unit by a data bus and is provided with cell array blocks having nonvolatile ferroelectric capacitors and stores execution data required for the execution of the instruction information.

Abstract: A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

Abstract: A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: A semiconductor memory includes a control circuit for generating an internal read command signal depending on an externally applied read command signal. A clock generating circuit generates a system clock signal and a time shifted clock signal generated by a DLL circuit. A latency counter circuit comprises a first control circuit for generating a first control signal and a second control circuit for generating a second control signal. The first control signal is used to latch the internal read command signal in one of FIFO-latching cells. The latching is carried out in a system clock domain. The second control signal is used to release a time shifted internal read command signal from one of the FIFO-latching cells in a DLL clock domain. The relationship between first and second control signals determines a CAS latency by which data items appear at a data terminal synchronous with an externally applied clock signal.

Abstract: An object localising system comprises sensor devices at different sites, each sensor device being capable of detecting a signal from an object, and control means for repeatedly responding to the outputs of the sensor devices by selecting a sub-set of the devices and determining the amount by which the times at which the devices of the sub-set receive the signal are delayed with respect to each other to enable calculation of the current location of the object. Each sensor device can be switched between a master mode, in which the device is operable to transmit events derived from a signal from an object, and a slave mode, in which the device is responsive to such events from another sensor device for processing its own signal in order to determine the time delay between receipt of the signals by the sensors of the respective devices.

Abstract: This invention serves as a method and apparatus for delivering power to a series of remote sensors in an on hull sensor grid for the purpose of biasing the active circuitry on the sensors. It requires no physical connection between the source of power and the sensor. It works by delivering electrical energy across the insulating gap that separates the sensor from the hull by means of a displacement current. In particular, the method and device include a conducting layer interposed between inner and outer decouplers and a ground plane interposed between a bonding layer and the inner decoupler. An application of alternating current to the ground plane will activate the conducting layer and provide power to the sensors at a location of the outer decoupler. The inner decoupler acts as a capacitor and the ground plane further provides an electrical path back to the hull.

Abstract: The invention is illustrated as an underwater acoustic transducer comprising an active acoustic element for transducing sound and electrical signals; a front and rear housing element disposed on each side of the active acoustic element to define a corresponding front and rear acoustic chamber on each side of the active acoustic element; and a rear cover disposed on the rear housing element to provide tuning of the corresponding rear acoustic chamber. In the method of manufacturing the an underwater acoustic transducer, the method includes the step of selecting a port diameter and/or thickness of the front and rear housing elements according to an empirically tuned acoustic performance of the underwater acoustic transducer in combination with the facemask, helmet or headgear in or on which the underwater acoustic transducer is mounted.

Abstract: A medical dispenser being adapted to hold a number of medical doses and being adapted to determine when a user or patient gains access to one or more of the medical doses, the dispenser comprising: means for determining each of a first plurality of points in time or time intervals at which the user or patient should take a medical dose, means for detecting each of a second plurality of points in time where the user or patient gained access to the medical doses, means for providing to the user or patient information relating to a relation between the first and second pluralities, and wherein the providing means are adapted to, if the user gains access to the medication multiple times per point in time or time interval in the first plurality of points in time or time intervals, provide information relating to a relation between the pairs of one of the firs plurality of points in time or time intervals and a first of the second plurality of points in time occurring after the pertaining point in time of the first

Abstract: The calendar mechanism for a watch includes two rotating indicators provided with respective toothed wheels (11, 14), indicating for example the date and the phase of the moon or the day of the week, and drive lever (21) provided with two beaks (22, 23) for making the corresponding indicator move forward one step, depending upon whether it is pivoting in one direction or the other. The daily movement forward of the indicators is assured by a drive wheel (20) making one revolution per day and provided with a pin (38) which cooperates with a cam surface (33) of the drive lever. In order to correct the indicators independently of each other, a gear train (44) actuated by a control stem of the watch causes a correction wheel (50) to rotate, which acts on a nose of the drive lever (21) to pivot the latter selectively in one direction or the other.

Abstract: To provide a power reserve display mechanism having a mainspring remaining amount display showing a novel behavior and a mechanical timepiece having the same. A power reserve display mechanism of a mechanical timepiece includes a displacement conversion mechanism having a first rotation input portion coupled to a ratchet wheel and rotated in accordance with rotation of the ratchet wheel and a second rotation input portion coupled to a barrel wheel and rotated in accordance with rotation of the barrel wheel as well as an output portion moved linearly in one direction in accordance with rotation of the first rotation input portion and moved linearly in other direction in accordance with rotation of the second rotation input portion, and mainspring accumulating remaining amount display means provided at the output portion of the displacement conversion mechanism for displaying a mainspring accumulating remaining amount by a position along a linear line.

Abstract: There is provided a multifunction timepiece wherein the visibility of pointers can be improved, and increases in the thickness of the timepiece can be reduced. This timepiece includes a dial, an hour hand, a minute hand, a pointer, and a movement. The dial has a dial cover and a time display section on the inner periphery thereof. The hour hand is mounted on the time display section and has an hour hand rotating shaft disposed at a different position from the center position of the time display section. The minute hand is mounted on the time display section and has a minute hand rotating shaft disposed at a different position from the center position of the time display section. The pointer is mounted on the time display section and has a pointer rotating shaft. The dimension A from the pointer rotating shaft to the tip of the pointer is greater than the dimension B from the minute hand rotating shaft to the tip of the minute hand.

Abstract: The invention relates to a timepiece which has a resin bearing section. Moreover, the invention relates to a wheel train apparatus which has a resin bearing section. The invention is constituted by the timepiece provided with a gear wheel and supporting members which support the gear wheel, the supporting members being formed from a filler containing resin. Alternatively the invention is constituted by the wheel train apparatus provided with a gear wheel and supporting members which support the gear wheel, the supporting members being formed from a filler containing resin.

Abstract: This invention comprises a two part audio system in which all of the processing power is allocated to a small, lightweight satellite part that is the face unit. Mass storage, amplification, and wired power for recharging the face unit is provided by the other part, the base. The base runs either from a 120 volts AC source or 12 volts DC. The face unit contains a small amount of flash memory making it capable of carrying music normally stored on two or more compact discs (CDS).

Abstract: An information reproducing apparatus (1) for reproducing contents information recorded by a group unit on a recording medium, is provided with: an input device (80) through which a user input command to resume the reproduction of the contents information can be inputted; a reproducing device (30, 50, 60) for reproducing the contents information; and a control device (70) for (i) identifying a user input waiting mode in which the user input command through said input device is waited for, (ii) determining a position from which the reproduction of the contents information is to be resumed if the user input waiting mode continues for a predetermined time period and (iii) controlling said reproducing device to resume the reproduction of the contents information automatically from the determined position.

Abstract: An information recording medium having at least a read only area and a recording and reproducing area is composed of at least: a substrate; a recording layer formed on the substrate so as to record and reproduce information; and a light transmission layer having transparency formed on the recording layer. The information recording medium is further characterized in that a wobbling groove corresponding to the read only area and another wobbling groove corresponding to the recording and reproducing area is formed on the substrate without overlapping with each other, the recording and light transmitting layers are continuously adhered over at least two areas of the read only area and the recording and reproducing area, reflectivity of the recording layer is more than 5%, and a push-pull signal output T3 reproduced from the read only area and another push-pull signal output T4 reproduced from the recording and reproducing area before recording satisfies relations of T3?0.1, T4?0.1 and 1.5?T3/T4?0.5.

Abstract: It is an object of the present invention to provide an optical pickup astigmatism adjusting method capable of easily correcting an astigmatism even if the spot shape of a light beam converged on an optical disc is not a true circle. An optical pickup astigmatism adjusting system of the present invention finds an inter-focal distance L0 between a focal position where a light beam is converged in RAD direction and another focal position where a light beam is converged in TAN direction, and a further inter-focal distance L45 between a focal position where a light beam is converged in a direction inclined 45 degrees from RAD direction and another focal position where a light beam is converged in a direction inclined 45 degrees from TAN direction, thereby measuring an astigmatism in accordance with the inter-focal distances L0 and L45. Then, an installation angle of a reflection mirror is adjusted in accordance with the inter-focal distances L0 and L45, thus correcting the astigmatism.

Abstract: A optical scanning device (1) for scanning an information layer (2) with a radiation beam (25) in a writing mode and a reading mode comprises a radiation source (7) for emitting the beam and an objective lens (10) for converging the beam so as to form a scanning spot (19) in the information layer. The device also includes a scanning spot power switch (20) for switching the size of the cross-section of the beam between a first size at the writing mode and a second, larger size at the reading mode so as to switch the rim intensity of the beam between a first intensity level (Irim,writing) at the writing mode and a second, higher intensity level (Irim,reading) at the reading mode, thereby switching the light power of the scanning spot between a first power level (Pwriting) at the writing mode and a second, lower power level (Preading) at the reading mode.

Abstract: The present invention relates to an apparatus for reading from and/or writing to optical recording media, which has a tracking device, a four-quadrant detector, two summation points and a phase comparator for tracking in accordance with the differential phase detection method, and also various delay elements that can be set by a control device. The object of the present invention is to propose an apparatus of this type which exhibits the best possible compensation of the error in the track error signal and thus in the tracking signal, the said error being caused on account of the lens movement. To that end, the invention provides for analogue delay elements to be arranged upstream and digital delay elements to be arranged downstream of the summation points. The present invention is suitable for apparatuses for reading from and/or writing to optical recording media, such as CD, CDI, CD-ROM, DVD, CDR and others.

Abstract: A method of and a circuit for providing a playback signal, which is compensated for time delay, from a photodetector having a plurality of outputs. A time difference between a first signal corresponding to a part of the outputs of the photodetector and a second signal corresponding to another part of the outputs of the photodetector is detected and one of the first and second signals is temporally shifted to compensate for a time delay between different outputs of the photodetector. The temporally shifted signal is summed with the other signal to provide a playback signal. Accordingly, the time delay between the outputs of the photodetector is compensated, thereby increasing the degree of modulation of the data playback signal. In addition, distortion or degradation of the signal is suppressed and occurrence of errors in the playback signal is minimized, thereby improving the reliability of the playback signal.

Abstract: An optimal recording apparatus and method for optical recording media are disclosed which are capable of recording data on the optical recording medium under optimum conditions in an optical recording/reproducing apparatus. In accordance with the optimal recording apparatus and method, a reference power value recorded on an optical recording medium is first read out. Test data is then recorded onto a first field of a test data in the optical recording medium under a condition in which a recording power value is varied with reference to the read power value. The test data recorded on the first field is subsequently reproduced in order to determine an optimum recording power value from the reproduced characteristics. Based on the determined optimum recording power value, test data is recorded on a second field of the test area under a condition in which a format of recording signals is varied. The test data recorded on the second field is subsequently reproduced in order to determine an optimum write strategy.

Abstract: An error signal detection method includes detecting light incident through an objective lens after having been reflected and diffracted from a recording medium, as eight light portions in a matrix including four inner light portions and four outer light portions, wherein the rows and columns of the matrix are parallel to the tangential and radial direction of the recording medium, respectively; calculating a first sum signal by summing a detection signal from at least one outer light portion located in a first diagonal direction, and a detection signal from an inner light portion located in a second diagonal direction; calculating second sum signal by summing a detection signal from an inner light portion located in the first diagonal direction, and a detection signal from an outer light portion located in the second diagonal direction; and comparing phases of the first and second sum signals to detect a tilt error signal.

Abstract: An optical disk device capable of data recording. A tracking error signal is generated from return light from an optical disk, and the tracking error signal to which a tracking offset signal is further added is supplied to a tracking servo circuit. A tracking offset signal in accordance with the driving current when recording data is determined based on the relationship between the driving current of the laser diode and the optimum tracking offset. Tracking control is performed using a fixed tracking offset signal when reproducing data and using a tracking offset signal which is variable in accordance with the driving current when recording data.

Abstract: An optical information recording and reproducing apparatus that determines the quality of recorded information through a beta value from information on the amplitude of a reproduced signal and if the beta value is outside the permissible range, outputs information on error to a host computer. Immediately after the information is recorded the information is reproduced first and second kinds of information including information on the amplitude of the reproduced signal and performance information or error information obtained from a binarized signal of that reproduced signal, respectively are used to determine the quality of the reproduced signal. Recording power condition is changed based on the first kind of information and a recording pulse width condition or reproduction condition is changed based on the second kind of information to ensure the reliability of the information recorded.

Abstract: A main information area 31 capable of recording an information signal and a subsidiary information area 32 for recording subsidiary information that is different from the information signal are divided in one principal plane direction of a substrate, and an information layer for recording the information signal in the main information area 31 is provided also in the subsidiary information area 32, and medium identification information for distinguishing the medium optically is recorded in the information layer of the subsidiary information area 32 without changing the shape of the information layer. As a result, the medium identification information can be recorded in an optical recording medium 1 stably. In particular, the initialization of a phase change type optical recording medium and the recording of the medium identification information can be performed at the same time, so that the production process can be simplified, and the production costs can be reduced.

Abstract: An information recording method in which an energy beam is irradiated to a recording medium and a basic recording pattern is generated. The basic recording pattern has a first power level provides a first state and a second power level providing a second state. Based upon a period of a recording timing generating clock in a recording mode, and a relative velocity of the energy beam and the recording medium, there is formed a first sequence of the second state and the first state based upon parameters as a first small recording pattern, a second sequence which starts with the first state and ends with the first state as a second small recording pattern, a state in which the second small recording pattern follows said the small recording pattern as the basic recording pattern, and a state in which the basic recording patterns are repeated as a recording pattern.

Abstract: An information recording medium is provided, which comprises a plurality of recording layers and a first disc information area for storing parameters relating to access to the plurality of recording layers and formats relating to the plurality of recording layer. The first disc information area is provided in a first recording layer which is one of the plurality of recording layers.

Abstract: Certain embodiments of the present invention are directed at data storage devices capable of storing, reading and writing data to storage areas of nanometer dimensions. Certain embodiments are directed at devices wherein a fluid medium and particles are provided between a storage medium and an energy-emitting tip to channel energy from the tip to the storage medium. Certain embodiments are directed at devices wherein conductor molecules are attached to the surface of the storage medium and channel energy to the storage medium from an energy-emitting tip. Certain embodiments of the present invention are directed at methods of reading and writing to a storage medium by making use of intermediate particles and/or molecules to channel beams from a tip to a storage medium where data is stored.