Patents Issued in February 1, 2007
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Publication number: 20070024308Abstract: A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.Type: ApplicationFiled: October 5, 2005Publication date: February 1, 2007Inventors: Saeed Azimi, Son Ho
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Publication number: 20070024309Abstract: A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.Type: ApplicationFiled: October 5, 2005Publication date: February 1, 2007Inventors: Saeed Azimi, Son Ho
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Publication number: 20070024310Abstract: A method for finding the impedance of a device under test using an impedance measuring apparatus having a modem-type auto-balancing bridge, two or more measurement signals, each of which has a different phase with respect to the reference signals supplied to the modem inside said auto-balancing bridge, are applied to a device under test; the impedance of this device under test is measured when each of the measurement signals is applied to the device under test; and the impedance of this device under test is found using the above-mentioned phase and the impedance measurement value of each of these measurements.Type: ApplicationFiled: June 21, 2006Publication date: February 1, 2007Inventors: Koji Tokuno, Yoichi Kuboyama, Hideki Wakamatsu
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Publication number: 20070024311Abstract: Good device PASS/FAIL determination is realized by measuring timings of a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals. A semiconductor test apparatus comprises differential signal timing measurement means for outputting cross point information Tcross obtained by a timing of a cross point of one of differential signals, non-differential signal timing measurement means for outputting data change point information Tdata obtained by a timing of transition of a logic of the other non-differential signal output, phase difference calculation means for outputting a phase difference ?T between the cross point information Tcross and the data change point information Tdata, and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relationship of the DUT based on a predetermined threshold value.Type: ApplicationFiled: July 14, 2006Publication date: February 1, 2007Inventors: Masatoshi Ohashi, Toshiyuki Okayasu
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Publication number: 20070024312Abstract: A device for testing a plurality of integrated semiconductor circuits on wafers is disclosed. The device includes a support device for taking in and temperature control, particularly heating or cooling, of the wafer, a measuring board with electronic circuit units for a function check of the integrated semiconductor circuits disposed on the wafers, a test head, connected to the measuring board, with contact needles, the head which creates an electrical contact between the measuring board and the integrated semiconductor circuits, and at least one nozzle for introducing a purge gas onto the wafer surface, whereby the device is provided without a sealing enclosure and that the support device, measuring board, wafer, test head, and nozzle are exposed to the gas mixture of the atmosphere.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventors: Klaus Rittberger, Heinrich Wieczorek
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Publication number: 20070024313Abstract: A chuck top allowing reliable recognition of a wafer mounted on a wafer-mounting surface or on a chuck top conductive layer by a camera such as a CCD and hence allowing wafer inspection without problem is provided. The chuck top is used for a wafer prober mounting a wafer on the wafer-mounting surface for inspection, in which reflectance of a portion other than the portion for mounting the wafer of the wafer-mounting surface or the chuck top conductive layer is smaller than the reflectance of a peripheral end portion of the wafer to be inspected. The portion other than the portion for mounting the wafer of the wafer-mounting surface or the chuck top conductive layer of chuck top preferably has surface roughness Ra of at least 0.0001 ?m and at most 0.05 ?m.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventors: Katsuhiro Itakura, Masuhiro Natsuhara, Tomoyuki Awazu, Hirohiko Nakata
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Publication number: 20070024314Abstract: The present invention relates to a test system, and in particular relates to a test system capable of testing a plurality of chips simultaneously. The test system comprises a single-chip tester and a handler. The single-chip tester further comprises a pattern memory and a micro-processor. The pattern memory comprises a plurality of pattern units for respectively performing a function pattern test on the plurality of chips and generating a test result mapping to the plurality of chips. The micro-processor performs various tests and generating an interface control signal according to the test result. The handler initiates the micro-processor for performing various tests and receives the interface control signal to finish testing the plurality of chips. The pluralities of chips are set to the handler.Type: ApplicationFiled: July 31, 2006Publication date: February 1, 2007Inventors: Cheng-Yung Teng, Yi-Chang Hsu, Li-Jieu Hsu
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Publication number: 20070024315Abstract: A method and apparatus are provided for inspecting an electrical defectiveness of a liquid crystal display substrate. The method includes shorting ESD protection devices with a conductive shorting bar to form a current path on each of signal wirings of the substrate, supplying a current to the signal wirings, and determining a defectiveness of the signal wirings depending on the current flowing on the signal wirings.Type: ApplicationFiled: October 3, 2006Publication date: February 1, 2007Inventors: Jong Kim, Hyun Lee, Yong Cho, See Jeong
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Publication number: 20070024316Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.Type: ApplicationFiled: July 31, 2006Publication date: February 1, 2007Applicant: STMICROELECTRONICS LIMITEDInventor: Andrew Dellow
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Publication number: 20070024317Abstract: Integrated circuits with on-chip impedance matching techniques, which can be implemented to provide high precision and which greatly increase the precision of resistors integrated into the integrated circuit, are provided.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Inventor: James Hansen
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Publication number: 20070024318Abstract: A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Inventor: Mahesh Mamidipaka
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Publication number: 20070024319Abstract: A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.Type: ApplicationFiled: October 7, 2004Publication date: February 1, 2007Applicant: SIEMENS AKTIENGESELLSCHAFTInventors: Joachim Bangert, Christian Siemers
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Publication number: 20070024320Abstract: A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input terminal, the first and second transistors being interconnected at a first output terminal; third and fourth transistors connected between the first node and the generator transistor and having respective control terminals connected to a second input terminal, the third and fourth transistors being interconnected at a second output terminal; and first and second resistances connected between the first and second output terminals and interconnected at a second node. The transmitter includes a selective enabling circuit connected to the first and second nodes, and to a third node corresponding to a control terminal of the generator transistor.Type: ApplicationFiled: July 5, 2006Publication date: February 1, 2007Applicant: STMicroelectronics S.r.l.Inventors: Pierpaolo De Laurentiis, Hua Wang
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Publication number: 20070024321Abstract: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Inventors: Chien-Ting Lin, Liang-Wei Chen, Che-Hua Hsu, Meng-Lin Lee, Hui-Chen Chang, Wei-Tsun Shiau
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Publication number: 20070024322Abstract: A method and system for leakage current reduction in domino circuits is described. The system includes a domino circuit with a dynamic gate, a static gate, and a standby signal to set the domino circuit to an evaluate phase during an inactive mode. The inputs to the static gate are set to low and the inputs to the dynamic gate are set to high during the inactive mode. The standby signal may be an input to a device in the dynamic gate or an input to a latch coupled to the dynamic gate.Type: ApplicationFiled: August 1, 2005Publication date: February 1, 2007Inventors: Yibin Ye, Siva Narendra, Vivek De
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Publication number: 20070024323Abstract: To provide a broadband circuit from which a desired circuit characteristic is stably obtained over a wide frequency band with a small number of circuit devices and which can be easily designed. In the case of the broadband circuit to which a circuit device is connected through a transmission line including a signal transmission conductor, grounding conductor, and dielectric present between these conductors, an LILC 13 having a four-terminal line structure in which a pair of conductors are faced each other, having an impedance lower than that of a conductor connected to any terminal, and using a frequency band of an electromagnetic wave whose wavelength is shorter than a length approxmately four times of the length of the line as an object frequency band is inserted into the transmission line and used as a low impedance device to the electromagnetic wave of the object frequency band.Type: ApplicationFiled: March 24, 2004Publication date: February 1, 2007Inventor: Hirokazu Tohya
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Publication number: 20070024324Abstract: A circuit for sensing a current includes a first upper resistor having a first end coupled to a first end of a sense resistor, the sense resistor being configured to receive an input current. A second upper resistor has a first end coupled to a second end of the sense resistor, so that the sense resistor defines a first potential between the first and second ends of the sense resistor. A first lower resistor is provided between the first upper resistor and the ground. A second lower resistor is provided between the second upper resistor and the ground. An amplifier has a first input node and a second input node, the first input node being coupled to a node between the first upper resistor and the first lower resistor. The second input node is coupled to a node between the to the second upper resistor and the second lower resistor. The first and second input nodes defines a second potential corresponding to the first potential.Type: ApplicationFiled: July 31, 2006Publication date: February 1, 2007Applicant: IXYS CorporationInventor: Sam Ochi
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Publication number: 20070024325Abstract: A sense amplifier, including a first stage amplifier and a second stage amplifier, for compensating input offset voltage changes due to temperature variation of the sense amplifier. The first stage amplifier receives a data voltage and a reference voltage, and outputs a first data output and a second data output. The first stage amplifier receives an adjusted voltage, and is biased at an internal voltage. The second stage amplifier includes a latch, for level-shifting and amplifying the first and second data output, and is biased at an external voltage. The sense amplifier further includes a bias circuit, for generating the adjusted voltage according to temperature variation of the sense amplifier, to reduce the input offset voltage changes.Type: ApplicationFiled: August 1, 2005Publication date: February 1, 2007Inventor: Chung-Kuang Chen
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Publication number: 20070024326Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Robert Faust, John Upton
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Publication number: 20070024327Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 ?±10%) in the USB transceiver.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Applicant: Synopsys Inc.Inventors: Scott Howe, Dino Toffolon, Cameron Lacy, Euhan Chong
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Publication number: 20070024328Abstract: An output driver includes a pre-driver that generates first and second gate control signals at first and second nodes. The output driver also includes a main driver that generates an output signal from the first and second gate control signals. The pre-driver includes a capacitor and switches that turn on to forms capacitive current paths between the output node and the first and second nodes during transitions of the output signal for maintaining a slew rate of the output signal.Type: ApplicationFiled: July 7, 2006Publication date: February 1, 2007Inventor: Soon-Kyun Shin
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Publication number: 20070024329Abstract: Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I?) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q?) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.Type: ApplicationFiled: June 1, 2005Publication date: February 1, 2007Applicant: WiLinx, Inc.Inventors: Mohammad Heidari, Ahmad Mirzaei, Masoud Djafari, Rahim Bagheri
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Publication number: 20070024330Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.Type: ApplicationFiled: June 1, 2005Publication date: February 1, 2007Applicant: WiLinx, Inc.Inventors: Ahmad Mirzaei, Mohammad Heidari, Masoud Djafari, Rahim Bagheri
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Publication number: 20070024331Abstract: A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is varied from the initial voltage until an output clock signal from the voltage controlled delay line is detected by the bias generator.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Inventor: Feng Lin
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Publication number: 20070024332Abstract: A reliable, integrated POR (power-on-reset) circuit with a compact and small area. In one set of embodiments, the POR circuit comprises NMOS and PMOS devices, where a combination of the respective threshold voltages of the NMOS and PMOS devices is used to set the POR threshold. The NMOS and PMOS devices may be coupled in a configuration resulting in a POR threshold that is a function of the PMOS threshold voltage and a scaled version of the NMOS threshold voltage. The scaling factor may be a function of the transconductance parameters of the NMOS and PMOS devices. Additional NMOS devices may be configured in the POR circuit to provide hysteresis functionality, with one of the NMOS devices coupling to one of the original NMOS devices. The scaling factor used in determining the POR threshold in case of a falling supply voltage may then be a function of the transconductance parameters of the original NMOS and PMOS devices and the additional NMOS device coupling to one of the original NMOS devices.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventor: Scott McLeod
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Publication number: 20070024333Abstract: A power detection circuit has a first comparator block, a charge controller block, and a second comparator block. The first comparator block compares a supply voltage with a first threshold value, and the charge controller block controls the charging of a first capacitor according to an output signal of the first comparator block. The second comparator block compares the charge in the first capacitor with a second threshold value so as to produce a power detection signal, and wherein a second capacitor is interposed between the charge controller block and the first capacitor.Type: ApplicationFiled: February 23, 2006Publication date: February 1, 2007Inventor: Hideaki Suzuki
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Publication number: 20070024334Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.Type: ApplicationFiled: July 12, 2005Publication date: February 1, 2007Inventors: Shad Shepston, Yong Wang, Jason Culler
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Publication number: 20070024335Abstract: The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal ?in when transition is made from the stop mode to the DLL mode are excluded from the object detected by phase detector 20 such that phase difference ??? detected by phase detector 20 is within a prescribed range when said transition is performed. As a result, it is possible to lock the delay of clock signal ?din with respect to clock signal ?in at a desired value (e.g., “2?”), and it is possible to prevent locking to an undesired abnormal state.Type: ApplicationFiled: March 30, 2006Publication date: February 1, 2007Inventor: Hiroki Sato
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Publication number: 20070024336Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: ApplicationFiled: October 4, 2006Publication date: February 1, 2007Applicant: Marvell Semiconductor Israel Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Publication number: 20070024337Abstract: The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first nodes. The first charge/discharge path and the second charge/discharge path include: two first switching units, connected to the first nodes, and configured to control, according to an input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path; and a second switching unit, disposed between a second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge.Type: ApplicationFiled: June 28, 2006Publication date: February 1, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Chen Teh, Mototsugu Hamada
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Publication number: 20070024338Abstract: Programmable duty cycle adjustment circuitry may be provided to correct for duty cycle distortion in serial data transmission systems. Duty cycle adjustment may be performed prior to transmitting data signals across a transmission medium. Duty cycle adjustment may also be performed as it is received from the transmission medium. Programmable duty cycle adjustment circuitry may be configured to adjust the rising and falling edges of data signals. Programmable duty cycle adjustment circuitry may also be configured to adjust the common mode level of data signals. The amount of duty cycle adjustment may be determined by end-users or through negative feedback.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Sergey Shumarayev, Rakesh Patel
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Publication number: 20070024339Abstract: A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.Type: ApplicationFiled: July 27, 2005Publication date: February 1, 2007Inventor: Benjamin Haugestuen
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Publication number: 20070024340Abstract: Apparatus for configuring network media connections. A medium-dependent interface crossover includes a first input terminal set comprising a first input pair and a first enabling pair, a second input terminal set comprising a second input pair and a second enabling pair, and an output pair selectively outputting data corresponding to data signals received by the first input pair or the second input pair. A detection circuit detects the data, and outputs a selection signal according to the detected data. A selection circuit receives the data signals, and provides the data signals to the first input pair or the second input pair and selects the first enabling pair or the second enabling pair according to the selection signal.Type: ApplicationFiled: June 14, 2005Publication date: February 1, 2007Inventors: Wen-Cheng Yen, Chien-Sheng Chen, Yung-Hung Chen
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Publication number: 20070024341Abstract: An apparatus for regulating a switching device that couples an output locus with one of a first voltage locus and a second voltage locus in response to a driver unit includes: a voltage feedback unit coupling the driver unit with at least one of the first voltage locus and the second voltage locus. The feedback unit provides a voltage feedback signal to the driver unit. The driver unit responds to the voltage feedback signal to affect the coupling by the switching device.Type: ApplicationFiled: July 27, 2005Publication date: February 1, 2007Inventors: Patrick Muggler, David Baldwin, Roy Jones
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Publication number: 20070024342Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.Type: ApplicationFiled: October 2, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masaya Sumita, Shirou Sakiyama, Masayoshi Kinoshita
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Publication number: 20070024343Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.Type: ApplicationFiled: October 2, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masaya Sumita, Shirou Sakiyama, Masayoshi Kinoshita
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Publication number: 20070024344Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.Type: ApplicationFiled: October 2, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kaori Hatakeyama, Masaya Sumita, Keisuke Kishishita, Michio Numa
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Publication number: 20070024345Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.Type: ApplicationFiled: October 2, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventors: Masaya Sumita, Shirou Sakiyama, Masayoshi Kinoshita
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Publication number: 20070024346Abstract: A charge pump circuit includes terminals that are connectable with a flying capacitor and a charge capacitor, respectively, and driving transistors connected with the terminals, a power supply voltage, and a ground potential, for controlling the charging of the flying capacitor and the transfer of charges from the flying capacitor to the charge capacitor. By repeating alternately an operation of charging the flying capacitor and an operation of transferring charges stored in the flying capacitor to the charge capacitor according to control signals supplied to gates of the transistors, the power source voltage is stepped down or stepped up. At least one of the driving transistors has its gate to be connected to a driving buffer via an impedance element so that the control signal is supplied thereto via the driving buffer.Type: ApplicationFiled: July 18, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takahisa Takahashi, Toshinobu Nagasawa, Tetsushi Toyooka
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Publication number: 20070024347Abstract: A semiconductor integrated circuit includes a charge pump circuit for stepping down or stepping up a voltage supplied from a single voltage supply VDD and outputting the voltage, by repeating an operation of charging a flying capacitor C1 and transferring charges stored in the flying capacitor to a storage capacitor C2. During the operation of the charge pump circuit, current supply for charging the flying capacitor is carried out by a current mirror operation. The semiconductor integrated circuit thus obtained by including the charge pump circuit is characterized in that rush current on startup of charge pumping is reduced and that output performance of a DC-CD converter is not impaired.Type: ApplicationFiled: July 18, 2006Publication date: February 1, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshinobu Nagasawa, Tetsushi Toyooka, Keiichi Fujii
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Publication number: 20070024348Abstract: A charge pump circuit of a switching source includes: a transformer; a rectifier diode of a secondary side of the transformer located at a ground side of a secondary winding wire; a capacitor for a charge pump; a power source of which a voltage is applied so as to charge accumulated in the capacitor; and a boosting transistor connected between the capacitor and the power source. A transformer voltage generated at a cathode side of the rectifier diode is at least partially used as a gate-driving voltage of the boosting transistor.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventor: Kazuaki Nakayama
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Publication number: 20070024349Abstract: The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventor: Masaki Tsukude
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Publication number: 20070024350Abstract: A differential amplifier having a positive input terminal, a negative input terminal, an output terminal, a bias terminal and a ground terminal is provided. The differential amplifier comprises a differential pair circuit and a current mirror circuit. Wherein, the differential pair circuit is coupled to the positive input terminal, the negative input terminal, the output terminal, and the bias terminal of the differential amplifier. The current mirror circuit receives a constant current from a current source, and mirrors the constant current to the differential pair circuit. The current mirror circuit further connects to the ground terminal of the differential amplifier, and the terminal of the current mirror circuit receiving the constant current is coupled to a first source/drain terminal of a first PMOS transistor. A second source/drain and a gate of the first PMOS transistor are connected to the bias terminal and the output terminal of the differential amplifier, respectively.Type: ApplicationFiled: August 1, 2005Publication date: February 1, 2007Inventor: Chun-Sheng Huang
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Publication number: 20070024351Abstract: There is provided a circuit for generating an internal power voltage capable of stably controlling an internal power voltage before generating a reference voltage during an initial power-up operation of a semiconductor device. The circuit for generating an internal power voltage includes: an internal power reset controller for outputting a control signal in response to an activated reference signal and an external power voltage wherein the reference signal is activated after the external power voltage is inputted; and an internal power generator for generating the internal power voltage using the external power voltage in response to the activated reference signal wherein the internal power generator is disabled in response to the control signal.Type: ApplicationFiled: December 30, 2005Publication date: February 1, 2007Inventor: Yong-Gu Kang
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Publication number: 20070024352Abstract: A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.Type: ApplicationFiled: July 24, 2006Publication date: February 1, 2007Inventors: Shuyun Zhang, Yibing Zhao
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Publication number: 20070024353Abstract: Single port characterization of RF amplifier phase and amplitude transfer functions are developed by measuring the output of the amplifier as it is excited by a predetermined frequency over a series of bias steps. One bias step is chosen as a reference level. Amplitude characterization is obtained from measured magnitude at each step in the test sequence. Phase information is extracted from the same measurements by measuring phase and phase trajectory at a reference level, and subtracting measured phase information at a desired step in the test sequence from an estimation of the reference phase trajectory at that step. Reference measurements may be interspersed with other measurements.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventor: George Moore
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Publication number: 20070024354Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.Type: ApplicationFiled: March 2, 2006Publication date: February 1, 2007Inventor: Wai Lee
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Publication number: 20070024355Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.Type: ApplicationFiled: March 2, 2006Publication date: February 1, 2007Inventor: Wai Lee
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Publication number: 20070024356Abstract: In the present technique for power management of a power amplifier, an amplifier bank from a plurality of amplifier banks in a power amplifier that has been switched off for a longest period of time is assessed (826) to provide a lowest amplifier bank. With this lowest amplifier bank, an up-threshold that is associated to the lowest amplifier bank is assessed (828), followed by another assessment (820) of a current power output of the power amplifier. It is next determined (830) whether the current power output corresponds at least in a predetermined way to the up-threshold, and if so, the lowest amplifier bank is accordingly switched on (832).Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Leroy Plymale, Joseph Clark, Henry Nguyen, John Ruppel, Thomas Sears, Ronald Porco, Armando Jimenez
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Publication number: 20070024357Abstract: In the present technique for power management of a power amplifier, it is first determined (314) whether a counter value corresponds at least in a predetermined way to a counter threshold, and if so, a current status of at least one amplifier bank from a plurality of amplifier banks in a power amplifier is switched (316).Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Leroy Plymale, Joseph Clark, Henry Nguyen, John Ruppel, Thomas Sears, Ronald Porco, Armando Jimenez