Abstract: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 ?m or less, a height H is 0.5 ?m to 10 ?m, a diameter is 20 ?m or less, and an angle ? is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, the crystallinity is improved and the gettering of nickel elements proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.

Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: Semiconductor devices formed by depositing III-nitride compounds on lithium niobate and/or lithium tantalate substrates are disclosed. Also disclosed, are semiconductor devices formed by depositing lithium niobate and/or lithium tantalate on III-Nitrides and Silicon Carbide substrates. The semiconductor devices provide good lattice matching characteristics between the substrate and the material that is deposited upon the substrate. The method of forming such semiconductor devices, which is also disclosed, enables fabrication of periodically-poled devices in a manner that is advantageous in comparison to existing technologies.

Abstract: A semiconductor light-emitting device is made of a group III-nitride compound semiconductor expressed as AlxGayIn1?x?yN (where 0?x?1, 0?y?1, and 0?x+y?1). The semiconductor light-emitting device includes: a substrate made of SiC; a semiconductor layer which is placed above the substrate and has a light-emitting region; a multi-layered reflective layer which is placed between the substrate and the semiconductor layer and which reflects light produced in the light-emitting region; and a phase matching layer which is placed between the substrate and the multi-layered reflective layer and which reflects light produced in the light-emitting region and matches a phase of light reflected from a lower boundary surface of the multi-layered reflective layer and a phase of light reflected from a lower boundary surface of the substrate among light produced in the light-emitting region.

Abstract: A nitride semiconductor light emitting device including a light emitting diode and a diode formed on a single substrate, in which the light emitting diode and the diode use a common electrode. According to the present invention, an active layer and a p-type nitride semiconductor layer are each divided into a first region and a second region by an insulative isolation layer, and an ohmic contact layer is formed on the p-type nitride semiconductor layer contained in the first region. A p-type electrode is formed on the ohmic contact layer and is extended to the p-type nitride semiconductor layer contained in the second region. An n-type electrode is formed on the p-type nitride semiconductor layer contained in the second region, passes through the p-type nitride semiconductor layer and the active layer contained in the second region, and is connected to the first n-type nitride semiconductor layer.

Abstract: A light emitting diode (LED) structure includes a substrate with a surface and cylindrical photonic crystals, a first type doping semiconductor layer, a first electrode, a light emitting layer, a second type doping semiconductor layer and a second electrode. The first type doping semiconductor layer is formed on the substrate to cover the photonic crystals. The light emitting layer, the second type doping semiconductor layer and the second electrode are sequentially formed on a portion of the first type doping semiconductor layer. The first electrode is formed on the other portion of the first type doping semiconductor layer without being covered by the light emitting layer. Because the substrate with photonic crystals can improve the epitaxial quality of the first type doping semiconductor layer and increase the energy of the light forwardly emitting out of the LED, the light emitting efficiency of the LED is effectively enhanced.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.

Abstract: Between a terminal of an element to be protected and a GND terminal, a protecting element is connected, which includes a first n+ region, an insulating region and a second n+ region. The first n+ region is provided to have a columnar shape in a depth direction of a substrate, and the second n+ region is formed to have a plate shape and disposed so as to face a bottom of the first n+ region. Thus, it is possible to allow a very large static current to flow into a ground potential through a first current path and a second current path. Thus, electrostatic energy reaching an operation region of a HEMT can be significantly reduced while hardly increasing a parasitic capacity.

Abstract: In a field effect transistor having a quantum well is provided by a primary conduction channel, at least one secondary conduction channel immediately adjacent and in contact with the primary channel has an effect bandgap greater than the effective bandgap of the primary channel, and the modulus of the difference between the impact ionisation threshold IIT of the primary channel and the effective conduction band offset (the height of the step) between the primary and secondary channels being no more than 0.5 Eg (effective), or (alternatively) no more than 0.4 eV. Higher energy carriers which might otherwise cause impact ionization leading to runaway are thus diverted into the secondary channel allowing the device to run faster at increased voltages and/or to exhibit much greater resistance to runaway. The primary channel is prefereably of low bandgap material, for example InSb, InAs, InAs1-y, In1-xGaxAs.

Abstract: A semiconductor device includes a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used to form contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well structure. Thin capping layers are also provided to protect certain layers from oxidation. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).

Abstract: The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.

Abstract: An improved photoconductive semiconductor switch comprises multiple-line optical triggering of multiple, high-current parallel filaments between the switch electrodes. The switch can also have a multi-gap, interdigitated electrode for the generation of additional parallel filaments. Multi-line triggering can increase the switch lifetime at high currents by increasing the number of current filaments and reducing the current density at the contact electrodes in a controlled manner. Furthermore, the improved switch can mitigate the degradation of switching conditions with increased number of firings of the switch.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

Abstract: The invention provides a solid-state imaging device including a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated holes, an output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and a clear transistor that discharges carriers accumulated in the accumulation region. One of semiconductor regions that form the photo diode and the accumulation region function as a source region of the clear transistor. In the accumulation period, if generated carriers spill from the source region of the clear transistor in the accumulation period, the clear transistor discharges the spilled carriers through a channel of the clear transistor in order to prevent the spilled carriers from entering the accumulation region of adjacent pixels.

Abstract: An imaging area is provided on a surface of a semiconductor substrate, and light-receiving portions and transfer channels are provided in the imaging area. A group of transfer electrodes extends in a direction crossing the transfer channels on the imaging area. A group of transfer signal lines, which are provided for every transfer signal of each phase along the periphery of the imaging area on the semiconductor substrate, is included. A transfer signal line connected to a transfer electrode having a large surface area on the transfer channel, of the group of the transfer electrodes, has an electrical resistance smaller than that of a transfer signal line connected to a transfer electrode having a small surface area on the transfer channel in the group of the transfer electrodes.

Abstract: A semiconductor imager structure having a photodiode being provided as a well region formed within a substrate layer and a transistor electrically connected to the photodiode and having a terminal that has a same electrical potential as the photodiode. The well region of the photodiode having an extended portion so that at least a portion of the terminal of the transistor has the same electrical potential as the photodiode is formed within the extended portion of the well region of the photodiode.

Abstract: A magnetoresistive element including a free layer having rotatable magnetization, in which information is recorded in the magnetoresistive element by the rotation of the magnetization of the free layer, is provided. The free layer is a laminate that includes at least one ferromagnetic sublayer composed of a ferromagnetic material and at least one low-saturation-magnetization ferromagnetic sublayer having a lower saturation magnetization than that of the ferromagnetic sublayer.

Abstract: The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Abstract: A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum oxide layer, forming a second layer of insulating material on portions of the aluminum oxide layer not covered by the spaced-apart dots of material, forming a conductive layer above the second layer of insulating material and the plurality of spaced-apart dots of material, and removing excess portions of the layer of conductive material and the second layer of insulating material.

Abstract: A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.

Abstract: The invention relates to a method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features: a semiconductor body (100) having a first side (101) and a second side (102), a drift zone (30) of a first conduction type which is arranged in the region between the first and the second sides (101, 102) and is formed for the purpose of taking up a reverse voltage, a field electrode arrangement arranged in the drift zone (30) and having at least one electrically conducted field electrode (40; 40A–40E; 90A–90J) arranged in a manner insulated from the semiconductor body (100), an electrical potential of the at least one field electrode (40; 40A–40E; 90A–90J) varying in the vertical direction of the semiconductor body (100) at least when a reverse voltage is applied.

Abstract: An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.

Abstract: A lateral short-channel DMOS includes an epitaxial layer formed on a semiconductor substrate. A first conductivity-type well is formed in the epitaxial layer. A second conductivity-type well is formed in the first conductivity-type well and includes a channel forming region. A source region is formed in the second conductivity-type well. A first conductivity-type ON resistance lowering well is formed in the epitaxial layer so as to contact the first conductivity-type well but not the second conductivity-type well, and includes a higher concentration of a first conductivity-type dopant than the first conductivity-type well. A drain region is formed in the first conductivity-type ON resistance lowering well. A gate electrode is formed above and insulated from at least the channel forming region.

Abstract: A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a second silicon layer is located below the first silicon layer and the buried oxide area.

Abstract: An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device or may be connected to a reference voltage. The device may be used in digital or analog circuits.

Abstract: An overvoltage-proof light-emitting diode has a lamination of light-generating semiconductor layers on a first major surface of a silicon substrate. A front electrode in the form of a bonding pad is mounted centrally atop the light-generating semiconductor layers whereas a back electrode covers a second major surface of the substrate. An overvoltage protector, of which several different forms are disclosed, is disposed between the bonding pad and the second major surface of the substrate. The bonding pad and back electrode serves as electrodes for both LED and overvoltage protector. As seen from above the device, or in a direction normal to the first major surface of the substrate, the overvoltage protector lies substantially wholly beneath the bonding pad.

Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Abstract: A semiconductor device, which is arranged in a semiconductor body (1), and which comprises at least one source region (4) and at least one drain region (5), each being of the first conductivity type, and at least one body (8) of the second conductivity type, arranged between source region (4) and drain region (5), and at least one gate electrode (10) which is isolated with respect to the semiconductor body (1) via an isolation layer (9). Said isolation layer (9) comprises polarizable particles, which are composed of a nanoparticulate isolating core and a sheath of polarizable anions or polarizable cations. The isolation layer (9) exhibits a high dielectric constant ?.

Abstract: A storage device comprises a probe and storage cell having moveable parts that are actuatable to plural positions to represent respective different data states. The probe interacts with the moveable parts to selectively actuate the moveable parts to the plural positions.

Abstract: In a semiconductor device in which a control circuit region and a power transistor region are formed, a first dummy region is formed between a ground side transistor composing a push-pull circuit and the control circuit region while a second dummy region is formed between the ground side transistor and the end part of a semiconductor substrate. The first and second dummy regions have a conductive type different from that of the semiconductor substrate. The second dummy region is connected electrically to a part of the semiconductor substrate between the ground side transistor and the first dummy region.

Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.

Abstract: An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator component, and a contact layer. The intermediate conductive layer may contact a structure of the semiconductor device. The insulator component, which is fabricated from a thermally and electrically insulative material, may be sandwiched between the intermediate conductive layer and the contact layer, which may substantially envelop the insulator component.

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor.

Abstract: Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: Provided is a method of producing a semiconductor package including at least two rows of leads in which the leads of each row separately connecting a semiconductor chip to an external substrate. The method includes: forming a lead frame, the lead frame including a die pad and a plurality of leads arranged about the die pad; attaching an adhesive tape to a surface of the lead frame covering at least substantially the die pad and the plurality of leads; removing portions of the leads and the adhesive tape disposed in a dividing region and thereby separating at least some of the plurality of leads to form multiple rows of leads; and mounting a semiconductor chip on the die pad, electrically connecting the semiconductor chip with the lead frame, and molding the lead frame and the semiconductor chip to provide a semiconductor package. The adhesive tape attached at undesirable locations of the lead frame is preferably removed after provision of the semiconductor package.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: The semiconductor device comprises a substrate (10) with a first (1) and an opposed second side (2), at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering (16), which device is further provided with bond pad regions (14). The protective security covering (16) comprises a substantially non-transparent and substantially chemically inert security coating (16), and the bond pad regions (14) are accessible from the second side of the substrate (10). The semiconductor device can be suitable made with a substrate transfer technique, in which a second substrate (24) is provided at the protective security covering (16).

Abstract: A wafer level package includes a device wafer having a micro device, and bonding pads which are connected to the micro device, and formed at one surface of the device wafer, via connectors extending from the bonding pads to the other surface of the device wafer, external bonding pads formed at the other surface of the device wafer and connected to the bonding pads through the via connectors, and a cap structure bonded to one surface of the device wafer so as to allow the micro device to be insulated and hermetically sealed.

Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.

Abstract: The present invention provides a semiconductor integrated device which can suppress high-frequency noise and which can thus stabilize the output voltage and power supply voltage of the reference voltage generating circuit. This semiconductor integrated device comprises a reference voltage generating circuit, a first bonding pad which is connected to the output of this reference voltage generating circuit, a lead which is connected to this first bonding pad via a first bonding wire, a second bonding pad which is connected to this lead via a second bonding wire, and a circuit which generates high-frequency noise and is connected to this second bonding pad.

Abstract: A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.

Abstract: Arrangements are used to supply power to a semiconductor package.

Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.