Abstract: A physical layer device communicates over a cable and includes a cable tester that determines a cable status, which includes an open status, a short status and a normal status. The cable tester includes a pretest module that senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A digital signal processor (DSP) communicates with the cable and that has a digital gain parameter. A cable length estimator communicates with the DSP and estimates cable length based on the digital gain parameter.

Abstract: A method automatically tests a parameter of an electronic component to determine whether the component has an acceptable value. The method employs an automatic electronic component testing machine having at least first and second measurement positions where the parameter can be measured. The testing process itself may falsely cause the value to appear to be unacceptable when the value is actually acceptable. The method places the component in a first measurement position and measures the parameter in the first position, thereby generating a first measured parameter value. The method also places the component in a second measurement position and measures the parameter in the second position, thereby generating a second measured parameter value. The method rejects the component only if all measured values are unacceptable, whereby the probability of falsely rejecting the component is less than if only a single measuring step were performed.

Abstract: In a high frequency circuit property measurement method, prior to property measurements of a high frequency circuit with RF measurement probe heads, RF measurement probe heads are calibrated using a calibration pattern comprising a signal line having a characteristic impedance and extending on a dielectric substrate, a first GND pad having one end disposed close to and at an interval from a first end of the signal line, a second GND pad having one end disposed close to and at an interval from a second end of the signal line, and a conductor electrically coupling the first GND pad to the second GND pad.

Abstract: Determining the RF shielding effectiveness of a shielding structure including measuring RF isolation between a first and a second element of a directional coupler and providing a first measurement result, placing a shielding structure so that a part of the shielding structure is substantially between the first element and the second element of the directional coupler, measuring RF isolation between the first element and the second element of the directional coupler RF and providing a second measurement result, and determining the shielding effectiveness of the shielding structure based at least in part on the first and the second measurement result.

Abstract: A measurement device for measuring a thickness of a film layer over a substrate utilizes a microwave source and a resonant cavity having an open side. A microwave signal is introduced at a first end of the resonant cavity with the open side against a surface measurement sample having a film layer over a substrate, and an output signal detector senses the output power of the signal at a far end of the resonant cavity. A processor uses a difference in the resulting resonant frequency of the cavity from that using a substrate without the film layer to determine the thickness of the film layer.

Abstract: An antenna device for determining the filling level of a filling material in a container (tank) comprising an essentially flat array antenna with an emitting area for emitting measuring signals towards the surface of the filling material and a holder for holding the array antenna over an opening of the container and to be connected to the rim of the opening in at least two points of attachment. Further, a protective dielectric cover covers the emitting area, the dielectric cover having an extension larger than the opening in order to extend over the rim of the opening. The antenna device provides several advantages, such as a very efficient sealing of the container opening, a very clean solution towards the container and a very effective protection of the array antenna.

Abstract: A system for unobtrusively measuring bioelectric signals developed by an individual includes multiple sensors, one or more of which constitutes a capacitive sensor attached to a holding device. The holding device serves as a mounting structure that holds sensors in place within a wearable garment. The holding device and sensors are horizontally and vertically adjustable relative to the garment, while the sensors are pressed against the individual and prevented from undesirable shifting upon movement of the individual.

Abstract: A method for determining capacitance includes alternately charging a capacitor to a first voltage and discharging the capacitor to a second voltage, generating an output signal having a frequency that is a function of a time period, and determining the capacitance based on the frequency of the output signal. The time period is selected from at least one of: (a) a time period needed to charge the capacitor from the second voltage to the first voltage and (b) a time period needed to discharge the capacitor from the first voltage to the second voltage.

Abstract: A guide for tip to transmission path contact includes a guide insulator with at least one passageway defined therein. The passageway has a tip passageway end and a transmission path passageway end. The guide insulator has an adhesive surface with adhesive associated therewith. The adhesive may be semi-permanent or permanent adhesive. The adhesive is for securing the guide insulator such that the passageway allows access to the transmission path. When not in use, the adhesive may attach the guide insulator to a nonstick surface of a backing surface.

Abstract: There is provided a prober that includes a chuck, a support base that supports the chuck, a first inner shield that shields the chuck, and an outer shield that encloses the chuck and the first inner shield. The outer shield is connected to a chassis, the chuck is connected to a first connector by a first cable, and the first inner shield is connected to a second connector by a second cable with an impedance device in between.

Abstract: A interconnect assembly features a prefabricated interconnect structure metallurgically bonded to a terminal of a larger structure. Fabrication of the interconnect structure's independently and separate from the larger structure enables the use of economic mass fabrication techniques that are well-known for miniature scale sheet metal parts. During fabrication, positioning and attachment, each interconnect structure is combined with and/or held in a carrier structure from which it is separated after attachment to the terminal. The interconnect structure is configured such that an attachment tool may be brought into close proximity to the attachment interface between the interconnect structure and the terminal for a short and direct transmission of bonding energy onto the attachment interface. The attachment interface provides for an electrically conductive and a bending stress opposing mechanical connection between the interconnect structure and the terminal.

Abstract: An integrated printed circuit board and test contactor for high speed semiconductor testing having an alignment housing with a cavity for receipt and positioning of the integrated circuit to be tested, a printed circuit board having a non-conductive elastomer portion positioned along a surface of the printed circuit board and an electrically balanced microwave transmission line structure having flexible fingers for transmitting test signals from the integrated circuit through the printed circuit board. A U-shaped ground element extends around the microwave transmission line structure.

Abstract: A mixed signal test system for testing a semiconductor device having both an analog function and a digital function achieves improved resolution and low cost. The test system is formed of a functional test unit for testing a digital function of a device under test (DUT), an analog test unit (ATU) for testing an analog function of the DUT, and a synchronous control unit for synchronizing operations between the functional test unit and the analog test unit. The analog test unit includes a digitizer for converting an analog output of the DUT into a digital signal, and an acquisition memory for storing the digital signal from the digitizer in specified addresses. The wave form of the analog output is repeated by a plurality of cycles and a sampling clock for the digitizer is phase shifted by a predetermined amount for each cycle.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: Disclosed is an inspection sensor and inspection apparatus capable of accurately inspecting the shape of a conductive pattern. A sensor element 12a includes an MOSFET, and an aluminum electrode (AL) serving as a passive element 80. The passive element or aluminum electrode 80 is connected to the gate of a MOSFET 81 and the source of a MOSFET 82. A voltage VDD is supplied from a power supply circuit 18 to the drain of the MOSFET 81, and the source of the MOSFET 81 is connected to the drain of a MOSFET 83. A reset signal is entered from a vertical selection section 14 into the gate of the MOSFET 82, and the voltage VDD is supplied from the power supply circuit 18 to the drain of the MOSFET 82. A selection signal is entered from the vertical selection section 14 into the gate of the MOSFET 83, and an output from the source of the MOSFET 83 is entered into a lateral selection section 13.

Abstract: According to one embodiment a system is disclosed. The system includes a tester having a power supply, an integrated circuit device under test (DUT) and a transient compressor (TC) coupled between the tester and the power supply to stabilize power delivered to the DUT by injecting current into the path between the power supply and the DUT.

Abstract: An apparatus for diagnosing a fault in a semiconductor device includes an laser applying unit, a detection/conversion unit, and a fault diagnosis unit. The semiconductor device is held at a state where no bias voltage is applied thereto. The laser applying unit then applies a pulse laser beam having a predetermined wavelength to the semiconductor device so as to two-dimensionally scan the semiconductor device with the pulse laser beam. The detection/conversion unit detects an electromagnetic wave generated from a laser applied position in the semiconductor device, and converts the detected electromagnetic wave into a time-varying voltage signal that corresponds to a time-varying amplitude of an electric field of the electromagnetic wave. The fault diagnosis unit derives an electric field distribution in the semiconductor device on the basis of the time-varying voltage signal to perform fault diagnosis on the semiconductor device.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: Signal transmission technology for transmitting 20–50 GHz band digital high speed signals, while keeping to the system structure and element structure of the prior art is provided. A signal transmission system is provided in which the driver and the receiver comprise the logic circuit and the memory circuit for a transistor extending an entire electronic circuit, and wherein the driver is connected to the receiver via a signal transmission line, and to the power source Vdd via the power source/ground transmission line, and the receiver circuits and the driver and receiver all have substantially differential input and differential output, and at the output terminal of the substantially differential output of the driver there are no connections to a power source or a ground and the receiver receives signals by detecting potential difference of a substantially differential input signal and there are no distribution wires in the signal transmission lines.

Abstract: A bus has two power consumption modes. A variable bus termination impedance is controlled to provide different bus termination impedances. A controller is coupled to the bus and includes a variable clock having different frequencies that are selectively provided to the controller. The impedance is increased or decreased responsive to the frequency being provided to the controller.

Abstract: A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.

Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.

Abstract: A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.

Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals DO thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Abstract: A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.

Abstract: A silicon-on-insulator (SOI) sense amplifier for sensing bit values stored in a memory cell, includes first and second input field effect transistors (FETs), connected to first and second cross-coupled CMOS inverter FET pairs. The input FETs are implemented as floating body FETs, which decreases gate capacitances and increases sense operation speed. History effect problems are minimized as threshold voltage differences are kept small.

Abstract: A semiconductor device includes a differential signal output circuit that outputs a differential signal, an amplitude control signal generation circuit that generates an amplitude control signal to control an amplitude of the differential signal for the differential signal output circuit, and a center voltage level control signal generation circuit that generates a center voltage level control signal to control a center voltage level of the differential signal. The differential signal output circuit outputs the differential signal having the center voltage level based on the center voltage level control signal and an output level based on the amplitude control signal. A forming region of the center voltage level control signal generation circuit and a forming region of the differential signal output circuit are provided near each other on a semiconductor substrate where operation characteristics of transistors formed respectively in the two forming regions become equal.

Abstract: Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.

Abstract: A delay-locked loop (DLL) architecture is provided that includes a voltage controlled delay line, a sample-and-hold circuit and an amplifier circuit. The voltage controlled delay line may have a plurality of buffer stages to provide a first clock signal and a second clock signal. The sample-and-hold circuit may receive signals corresponding to the first clock signal and the second clock signal. The sample-and-hold circuit may provide two sampled signals based on the received signals. Additionally, the amplifier circuit may be coupled to the sample-and-hold circuit and the voltage controlled delay line. The amplifier circuit may provide a control voltage to the buffer stages of the voltage controlled delay line based on the sampled signals received from the sample-and-hold circuit.

Abstract: In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Abstract: A DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first phase error signal; a sigma-delta modulator (SDM) coupled to the up-down counter for generating a second phase error signal according to the counting signal; an adder coupled to the SDM and the phase detector for summing the first phase error signal and the second phase error signal to generate a sum signal; a clock generator for generating a plurality of candidate clock signals according to a reference clock; and a multiplexer coupled to the clock generator and the phase detector for selecting one of the candidate clock signals to be the clock signal inputted into the phase detector according to the sum signal.

Abstract: Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

Abstract: In a duty adjustment circuit, a clock signal is frequency-divided to ½n by a frequency divider. In a first frequency doubler among n cascade-connected frequency doublers, the divided clock signal is delayed by a variable delay portion according to a control signal. The exclusive logical sum of the delayed signal and the divided clock signal in the frequency-doubling portion doubles the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, and is compared with a reference voltage by a comparison control portion. A control signal is fed back to the variable delay portion to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: Disclosed is a high-efficiency phase shift modulation method suitable for use in a traditional DC/AC single-phase full-bridge inverter. In this method, phase-shifted signal timing is used to modulate a duty cycle so that a power transistor is operated in a zero voltage switching state. As such, noises and switching loss of a switching device when turned on or off, may be reduced and thus efficiency of the inverter may be promoted. With this high-efficiency phase shift modulation method, at least the following advantages may be achieved: lower switching stresses, lower switching losses and thus increased conversion efficiency, lower electromagnetic interferences (EMIs) and no additional circuit required and thus easier realization of a controller for the inverter.

Abstract: A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to “inject” the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an “injection point.” The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.

Abstract: A clocking system for a memory that accomplishes these and other objectives has an external clock. A clock shaper has an input coupled to the external clock and an access clock at an output. A first delay block has an input coupled to the external clock and an output coupled to a master of an output register. A slave of the output register is coupled to the external clock. By having the master clock trailing the slave clock a temporary transparency window condition is created at the output register, allowing an improved cycle time (speed) prime bin distribution.

Abstract: Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.

Abstract: Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.

Abstract: An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

Abstract: A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

Abstract: Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

Abstract: A signal transmission amplifier circuit has a transmission gate with an input coupled to an input signal. A cross coupled latch is coupled to an output of the transmission gate and has a signal output. A reference generating circuit is coupled to the cross coupled latch.

Abstract: The drain of a power transistor M1 is connected to the non-inverting input terminal of an operational amplifier A and the drain of a transistor M2 is connected to the inverting input terminal of the operational amplifier A to make substantially equal the drain voltages of the power transistor M1 and the transistor M2, of which the gates are connected together and of which the sources are connected together. The drain current of the transistor M2 is outputted via a detection terminal 13 as a current signal proportional to the drain current of the power transistor M1.

Abstract: A variable capacitance charge pump system has a charge pump circuit with a variable capacitance. A pump clock driver circuit has a clock signal and is coupled to an input of the charge pump circuit. A feedback system has an enable signal coupled to an input of the pump clock driver circuit.

Abstract: The present invention provides a voltage booster circuit for effectively supplying a boosted voltage of a stable level despite of small area. The voltage booster circuit of the present invention includes: an oscillator for generating a basic pulse signal; a phase divider for dividing a frequency of the basic pulse signal to output a plurality of pulse signals having predetermined phase difference; a first to a fourth charge pumps for outputting a boosted voltage in response to a correspondent pulse signal among the plurality of pulse signals; and a drive controller for controlling the oscillator to maintain the boosted voltage to have a desired level.

Abstract: A semiconductor integrated circuit device according to a first aspect of the present invention includes: a first internal power source voltage generating circuit which includes a voltage boosting circuit and a level determining circuit, and outputs a first internal power source voltage, the voltage boosting circuit boosting a voltage based upon a voltage boosting start instruction signal after putting on a power supply, and the level determining circuit which generates a first control signal when an output voltage from the voltage boosting circuit reaches a first level and generates a second control signal for stopping the voltage boosting of the voltage boosting circuit when the output voltage from the voltage boosting circuit reaches a second level higher than the first level; a first control circuit which generates a first action start instruction signal based upon the voltage boosting start instruction signal and the first control signal; and a second internal power source voltage generating circuit which

Abstract: The present invention discloses a circuit for controlling a timing of overdriving a core voltage (internal voltage) which is a driving voltage of a sense amplifier of a memory device and a duration of the overdriven core voltage, and a method for easily measuring the timing and duration. A device for controlling an operation of an internal voltage generator includes an internal voltage driver for outputting an internal voltage to an output terminal, an internal voltage over-driver for compensating for a potential level of the output terminal, and a controller for controlling an enable timing and a disable timing of the internal voltage over-driver. The controller receives a first control signal and outputs a second control signal, and the second control signal is generated after a predetermined time from reception of the first control signal, an operation of the internal voltage over-driver being controlled according to the second control signal.