Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

Abstract: A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

Abstract: A photodiode array 1 is provided with an n-type silicon substrate 3. A plurality of photodiodes 4 are formed in array on the opposite surface side to an incidence surface of light L to be detected, in the n-type silicon substrate 3. Spacers 6 having a predetermined height are provided in a region not corresponding to regions where the photodiodes 4 are formed, on the incidence surface side of the light L to be detected, in the n-type silicon substrate 3.

Abstract: A functional perovskite cell formed on a silicon substrate layer and including a functional layer of bismuth ferrite (BiFeO3 or BFO) sandwiched between two electrode layers. An intermediate template layer, for example, of strontium titanate allows the bismuth ferrite layer to be crystallographically aligned with the silicon substrate layer. Other barrier layers of platinum or an intermetallic alloy produce a polycrystalline BFO layer. The cell may be configured as a non-volatile memory cell or a MEMS structure respectively depending upon the ferroelectric and piezoelectric character of BFO. The films may be grown by MOCVD using a heated vaporizer.

Abstract: A functional perovskite cell formed on a silicon substrate layer and including a functional layer of bismuth ferrite (BiFeO3 or BFO) sandwiched between two electrode layers. An optional intermediate template layer, for example, of strontium titanate allows the bismuth ferrite layer to be crystallographically aligned with the silicon substrate layer. Other barrier layers of platinum or an intermetallic alloy produce a polycrystalline BFO layer. The cell may be configured as a non-volatile memory cell or a MEMS structure respectively depending upon the ferroelectric and piezoelectric character of BFO. Lanthanum substitution in the BFO increases ferroelectric performance. The films may be grown by MOCVD using a heated vaporizer.

Abstract: A method for manufacturing a ferroelectric capacitor includes steps of: (a) forming a first crystalline barrier layer; (b) forming a second crystalline barrier layer composed of nitride by nitriding the first crystalline barrier layer; (c) forming a first electrode above the second crystalline barrier layer; (d) forming a ferroelectric film on the first electrode; and (e) forming a second electrode on the ferroelectric film.

Abstract: A bottom electrode (52) made of Ir, an initial layer (53), a core layer (54) and a termination layer (55) of a PZT film, and a top electrode (56) made of IrO2, are formed on an underlining film (51). The initial layer (53) is formed in a low oxygen partial pressure with a thickness of 5 nm. The thickness of the core layer (54) is set to 120 nm. The termination layer (55) is set to be an excess Zr layer. In other words, as for the composition of the termination layer (55), “Zr/(Zr+Ti)” is set to be larger than 0.5, and in the termination layer (55) Zr is contained more excessively than the morphotropic phase boundary composition.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.

Abstract: Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and P pillars of P conductivity type, arranged alternately in a direction from a center portion of the active region to an outer portion thereof to encircle each other in a horizontal direction. The N and P pillars are formed in a closed shape.

Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.

Abstract: The semiconductor device, in which a flaking of a layer or an element is prevented, is provided. A bonding pad section 13 of a semiconductor device 1 includes a polysilicon film 131, a barrier metal film 133 provided on the polysilicon film 131 and a metallic electrode 134 provided on the barrier metal film 133. The surface roughness of the surface of the polysilicon film 131 in the side of the barrier metal film 133 is equal to or larger than 3 nm. Further, the polysilicon film 131 contains substantially no phosphorus.

Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.

Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.

Abstract: A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that carriers are trapped or erased more easily in accordance with a variation in grading energy level. Therefore, the carriers are stored more effectively and the probability that the electric leakage occurs is reduced substantially.

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers.

Abstract: The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: A phase change material, a PRAM including the same, and methods of manufacturing and operating the same are provided. Insulating impurities may be uniformly distributed over an entire or partial region of the phase change material. The PRAM may include a phase change layer including the phase change material. The insulating impurity content of the phase change material may be 0.1 to 10% (inclusive) the volume of the phase change material. The insulating impurity content of the phase change material may be adjusted by controlling the power applied to a target including the insulating impurities.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: An offset spacer for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate, and an offset mask layer is formed over the surface of the gate electrode and the substrate. The offset mask may be formed of an oxide layer and acts as a mask during implanting, such as pocket implants and lightly-doped drain implants. A second implant spacer may be formed on top of the offset mask layer adjacent the gate electrode, and another implant process may be performed to form deeply-doped drain regions.

Abstract: An array substrate includes a substrate, a thin film transistor, a passivation layer, a pixel electrode and a storage capacitor. The thin film transistor includes a gate electrode formed on the substrate, a gate insulation layer formed on the substrate having the gate electrode, a semiconductor layer formed on the gate insulation layer and a data electrode formed on the semiconductor layer. The passivation layer is formed on the substrate having the data electrode and the pixel electrode is electrically connected to the data electrode through a contact hole formed through the passivation layer. The storage capacitor includes a first storage capacitor electrode that is spaced apart from the gate electrode of the thin film transistor and a second storage capacitor electrode that is formed on the gate insulation and including a same material as the pixel electrode.

Abstract: A non-volatile memory and fabricating method thereof are provided. First, a plurality of raised bit lines is formed on the substrate. The raised bit lines are paralleled one another, and extended in the same direction. Then, a charge trap layer is formed on the substrate. Afterwards, a plurality of word lines paralleled to one another is formed on the raised bit lines and filled up the gaps between the raised bit lines. Besides, the word lines are extended in another direction crossed by the direction of the raised bit lines. Because the non-volatile memory adopts design of raised bit lines, dopant diffusion induced by thermal processes of the buried bit lines can be avoided.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise off. In an embodiment, the source and drain are preferably self aligned to the gate, and preferably the gate is first defined as a conductive sidewall to an etched pad. Dielectric sidewalls are then defined over the gate, which in turn defines the positioning of the source and drain in a predetermined spatial relationship to the gate. In a preferred embodiment, the source and drain comprise conductive sidewalls buttressing the dielectric sidewalls. The channel of the device preferably comprises randomly oriented carbon nanotubes formed on an insulative substrate and isolated from the gate by an insulative layer.

Abstract: An electro-optical device includes: an electro-optical device substrate; step portions having a concave shape that are formed on a predetermined insulating film of the electro-optical device substrate; side wall portions each of which is formed on a side surface of the concave step portion between the surface of the insulating layer and the bottom of the step portion and has an upward convex curved surface, the surface of the curved surface being continuously formed with the surface of the insulating film at the top of the concave step portion; and capacitive elements each of which is formed on the step portion and the side wall portion and has a lower electrode layer, an upper electrode layer, and a dielectric layer interposed between the lower electrode layer and the upper electrode layer.

Abstract: A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor film. The pair of source/drain regions is thinner than the remainder of the semiconductor film other than the source/drain regions. The thickness difference between the pair of source/drain regions and the remainder of the semiconductor film is in a range from 10 angstrom (?) to 100 angstrom. The total process steps are reduced and the operation characteristic and reliability of the device are improved.

Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.

Abstract: A semiconductor integrated circuit device and a method of fabricating the same are provided. An embodiment of the semiconductor integrated circuit device includes a substrate having a cell region and a peripheral circuit region. A recess channel transistor may be formed in the cell region and include a source/drain region, a recess channel formed between the source/drain region, a gate insulation layer formed in the recess channel, and a gate formed on the gate insulation layer in a self-aligned manner. A planar channel transistor may further be formed in the peripheral circuit region and include a source/drain region, a planar channel formed between the source/drain region, a gate insulation layer formed in the planar channel, and a gate formed on the gate insulation layer in a self-aligned manner.

Abstract: A semiconductor device includes: a semiconductor layer provided with a P-channel field-effect transistor and an N-channel field-effect transistor that have a common gate electrode, a field plate provided to a back surface of the semiconductor layer with a first insulating layer therebetween and commonly for a channel of the P-channel field-effect transistor and a channel of the N-channel field-effect transistor, and a second insulating layer placed under the field plate.

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.

Abstract: A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided.

Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

Abstract: Cell placement areas in which a plurality of standard cells are placed in bands are provided on a semiconductor substrate of a semiconductor integrated circuit device. The cell placement areas have N- and P-wells formed in the cell placement areas, and a deep N-well formed in the substrate underneath the N- and P-wells. Substrate-bias supply cells, which are placed in each of the cell placement areas and have one side the height of which is the same as that of the bands of the cell placement areas, apply a substrate bias to the standard cells through the P-well. The substrate-bias supply cells are disposed one after another in the vertical direction and periodically along the horizontal direction. Many wiring traces for supplying substrate bias are eliminated by using the deep N-well and P-well as wiring routes regarding a power supply for supplying substrate bias.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first dummy active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.

Abstract: A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running direction in the channel and a pair of gate electrodes 3-1 and 3-2 facing the vertical channel 5, respectively, via the pair of gate insulation films 6-1 and 6-2, wherein the pair of insulation films have different thicknesses t1 and t2. It is also possible that the pair of gate insulation films 6-1 and 6-2 have different permittivities ?1 and ?2 and that the pair of gate electrodes have different work functions ?1 and ?2. Thus, it is possible to set the threshold voltage of the dual-gate field effect transistor to a desired value when fabricating it. Furthermore, it is possible to avoid the problem of an increase in subthreshold slope that occurs in the prior art.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.

Abstract: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A hydrogen concentration and a nitrogen concentration in the film can be increased by the increase of the flow rate of H2. Besides, the hydrogen concentration and the nitrogen concentration in the film can be decreased to heighten an oxygen concentration by the increase of the flow rate of N2O. The gate insulating film ensures the stability and reliability of the characteristics of the TFT, such as the threshold voltage (Vth) and sub-threshold constant (S value) thereof.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract: A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.

Abstract: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.

Abstract: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

Abstract: A wafer level package process includes: providing a device substrate, in which one surface of the device substrate includes a plurality of devices; providing a cap substrate and forming a plurality of cavities on one surface of the cap substrate, in which the location of each cavity is corresponding to the location of each device of the devices substrate; forming a protective cap in each cavity by utilizing the cavity as a mold; aligning each cavity of the cap substrate to each device of the device substrate and connecting the protective cap on the device substrate, such that each of the protective caps covers each device; and removing the cap substrate from the protective cap.

Abstract: A radiation sensor (10) comprises a support (1), a cavity (2) which may be a recess or a through hole formed in one surface of the support (1), a sensor element (4, 4a, 4b) formed above the cavity (2), preferably on a membrane (3) covering the cavity (2), and electric terminals (5, 5a, 5b) for the sensor element (4, 4a, 4b). The cavity (2) in the surface of the support (1) has a fully or partly rounded contour (2a).

Abstract: A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semiconductor layer. A Schottky electrode is selectively formed on the first nitride semiconductor layer to come into contact with the top surface of the second nitride semiconductor layer, and an ohmic electrode is formed thereon so as to be spaced apart from the Schottky electrode.

Abstract: The invention relates to a high-speed diode comprising a semiconductor body (1), in which a heavily n-doped zone (8), a weakly n-doped zone (7) and a weakly p-doped zone (6) are arranged successively in a vertical direction (v), between which a pn load junction (4) is formed. A number of heavily p-doped islands (51-57) spaced apart from one another are arranged in the weakly p-doped zone (6). In this case, it is provided that the cross-sectional area density of the heavily p-doped islands (51-57) is smaller in a first area region (100) near to the edge than in a second area region (200) remote from the edge.

Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 ?, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

Abstract: A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

Abstract: A semiconductor device and methods for protecting a semiconductor device. In an example, the semiconductor device may include a semiconductor substrate including at least one electrostatic discharge (ESD) protection device, at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug and a passivation layer disposed on less than all of the metal interconnection line. In an example method, a semiconductor device may be protected by diverting at least a portion of an electron build-up from an accumulation point to one or more protective circuits along one or more conductive paths, the electron build-up, without the diverting, sufficient to cause an ESD at the accumulation point. In another example, a semiconductor device may be protected by exposing one or more conductive lines to a fuse opening to avoid an ESD by diverting an electron build-up at the fuse opening to one or more ESD protection devices.